Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is a final office action in response to the communication filed 7/17/2025.
Claims 1-22 are currently pending.
Claims 17-22 have been withdrawn.
Claims 1-16 have been examined.
Response to Arguments
Applicant's arguments filed 7/17/2025 have been fully considered but they are not persuasive.
With regards to the drawing objection, the Examiner appreciates the applicants attempt to explain that the features of claim 7 are shown in Fig. 8. However that was not the intended objection the drawing. The Examiner was attempting to bring Applicant’s attention to that the language of claim 13, which was partially quoted in the objection was not understood to be shown in the drawing. Currently the drawing objection is maintained because the Examiner still does not see where in the drawings the MOSTFETs discussed in claim 13 are connected to the second, third and fourth FETs in the way that is described in claim 13. In response to this Office action, if Applicant maintains that the features are shown in the drawings, the Examiner kindly requests a detailed explanation to provide support and clarity of record.
With regards to the claim objections, while the Applicant is welcome to be their own lexicographer, the Examiner is currently maintaining the claim objection, in light of the Applicant believing that the Examiner was discussing claim 7 in the drawings despite the Examiner discussing language they believed was clearly from claim 13 and therefore the Applicant’s remarks did not address the Examiner’s objection.
Applicant's arguments filed 7/17/2025 have been fully considered but they are not persuasive. With regards to claim 1, Applicant argues (Response, page 2) Qin doesn’t teach that the gate structures are one the same gate dielectric because the gate structures 4031C and 4031D are not on the same gate dielectric as claimed. The Examiner understood the term “a gate dielectric” in claim 1 to be discussing the material properties of a layer and not a particular type of structure therefore the BRI of the claim would allow for two separate gate dielectric structures that are the channel region Applicant has support both for devices with one gate such as depicted in at least Figure 1and devices with the gate dielectric layer being two separate dielectric layers/structures beneath the gate electrodes as they have support for in paragraph [0036] of their specification and Fig. 6. If Applicant wants the claim to be read as applying on to planar devices then they are encouraged in any response to this action to amend the claims to clarify scope to specify ‘a single gate dielectric layer’ or similar.
With regards to Claim 2, on page 3 of the remarks, Applicant argues that Qin is not the opposite of the substrate 401. However, a second side is not limited to only being the bottom surface of a substrate under BRI, the first side is understood interpreted to be the top most surface of the substrate, and the second side is understood any side of the substrate that is below that surface. The third and fourth electrodes on surface below the top surface and therefore can be considered the second side. If the bottom side or bottom surface is intended then it is suggested that such language be utilized in the claim.
Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The Examiner believes that the claim language can be found in the art presented under the broadest reasonable interpretation of what is claimed.
Applicant's arguments filed 7/17/2025 regarding claim 7 starting on page 3 have been fully considered but they are not persuasive. Applicant essentially argues that the 103 rejection is not valid for the same reasons as the rejection for claim 1. Examiner maintains that Qin properly rejects the language of claim 1 as stated above and for similar reasons maintains that claim 7 is properly rejected.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show the language of claim 13 such as that the connections of first n-channel MOSFET, second n-channel MOSFET, and second p-channel MOSFET are connected respectively first electrodes, third electrodes, second electrodes, and fourth electrodes connected to second, third, and fourth FETs ( Fig. 7 only appears to show one MOSFET connected to control FETS nor is it shown in Fig. 12 when showing the controller) as described in the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 7-14 objected to because of the following informalities:
While not reaching the level of being indefinite, the over use of some of the terms in the claims made it hard to determine what was being claimed.
Suggested language for claim 7 may be:
a first field-effect transistor (FET) being FET1 comprising first and second electrodes on a gate dielectric of the FET1 being G1F1 and G2F2, third and fourth electrodes on the substrate of the FET being G3F1 and G4F1, a fifth electrode on a source region of the FET being SF1, and a sixth electrode on a drain region of the FET being DF1;
…
wherein
G1F1, G1F2, G1F3, and G1F4 are connected.
Suggested language for claim 13 may for example be:
a first p-channel metal-oxide semiconductor FET (MOSFET) being PMOS1 comprising a source electrode connected to a supply voltage terminal of PMOS1, a gate electrode of PMOS1 connected to the input voltage terminal, and a drain electrode of PMOS1 coupled to eachG1F1, G1F2, G1F3, and G1F4 respectively;
Carrying such changes throughout the claims would help clarify connections between the FETs and MOSFETs, especially when we get above 2 FETs. Examiner asks the applicant to consider either this or other clarifying the language throughout the claim set to better assist in clarity.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claims 1, 2, 5 and 6 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Qin et al. US 20190019897 A1 (hereinafter Qin).
Regarding claim 1:
a substrate; (Qin, Fig 4, substrate layer 401)
a source region; (Qin, Fig 4, the region directly in contact with the first source structure 4041 would be default be a source region)
a drain region; (Qin, Fig 4, the region directly in contact with 405 would by default be a drain region)
a channel region between the source region and drain region; (Qin, Fig. 4, first channel layer 4061 would have a channel region that is between the source and drain regions)
a gate dielectric on the channel region; (Qin, Fig. 4, gate dielectric 4021C and 4021D being made of gate dielectric material which is on the channel region 4061 4062)
first and second electrodes on the gate dielectric; and (Qin, Fig. 4, a third gate structure 4031C and fourth gate structure 4031D on the gate dielectric 4021C and 4021D)
third and fourth electrodes on the substrate. (Qin, Fig 4, first gate structure 4032A and second gate structure 4032B are on the substrate 401)
Regarding claim 2:
The apparatus of claim 1, wherein the source region, drain region, and channel region are proximate to a first side of the substrate (Qin, Fig. 4, source region 4041, drain region 405 channel region 4061 4062 are all above the substrate, therefore on a first side of the substrate. )
the gate dielectric is on the first side of the substrate (Qin, Fig. 4 gate dielectric 4021 C and 4021 D is on are above the substrate, therefore on the first side of the substrate.)
and the third electrode and fourth electrode are on a second side of the substrate opposite the first side. (Qin, Fig. 4, [0023] the first and second gate structures 4032A and 4032B are in a first and second groove in an upper surface of the substrate which can be considered the second side of the substrate that is opposite the first side.)
Regarding claim 5:
The apparatus of claim 1, wherein the source region, drain region, and channel region extend from a first side of the substrate, (Qin, Fig. 4, source region 4041 4042, drain region 405 channel region 4061 4062 are all above the substrate, therefore extend from a first side of the substrate.)
the gate dielectric is on an outer surface of the channel region extending from the first side of the substrate,(Qin, Fig. 4 gate dielectric 4021 C and 4021 D is on are above the substrate, therefore extend from the first side of the substrate)
and the third electrode and fourth electrode are on a second side of the substrate opposite the first side. (Qin, Fig. 1, electrodes 1032A and 1032B are on the opposite side of electrodes 1032C and 1032C)
Regarding claim 6:
The apparatus of claim 1, further comprising a fifth electrode on the source region (Qin, Fig. 4, a first source structure 4041) and a sixth electrode on the drain region. (Qin, Fig. 4, drain 405)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7-12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Uyemura (2002), Static Logic Gates. In: CMOS Logic Circuit Design. Springer, Boston, MA. (hereinafter Uyemura), and in further view of Qin and Meiser et al. US 20170257025 A1 (hereinafter Meiser).
Regarding claim 7:
Uyemura discloses:
a first field-effect transistor (FET) comprising first [electrode] , …, a fifth electrode on a source region of the FET, and a sixth electrode on a drain region of the FET; (Uyemura, page 119, “An nFET-pFET group with a common gate is called a complementary.” Therefore, the first FET can be a pFET.)
a second FET comprising first [electrode], …, a fifth electrode on a source region of the FET, and a sixth electrode on a drain region of the FET, (Uyemura, page 119, “An nFET-pFET group with a common gate is called a complementary.” Therefore, the second FET can be a nFET.)…
the first electrode of the first FET, the first electrode of the second FET… are connected,” (Uyemura, page 119, “An nFET-pFET group with a common gate is called a complementary.”)
Uyemura does not teach:
Second electrodes on a gate dielectric of the FET, or third and fourth electrodes on the substrate of the FET, of the first, second, third, and fourth FETs or:
“a third FET …;
a fourth FET …;
wherein:
the first electrode of the first FET, the first electrode of the second FET, the first electrode of the third FET, and the first electrode of the fourth FET are connected;
the second electrode of the first FET, the second electrode of the second FET, the second electrode of the third FET, and the second electrode of the fourth FET are connected;
the third electrode of the first FET, the third electrode of the second FET, the third electrode of the third FET, and the third electrode of the fourth FET are connected; and
the fourth electrode of the first FET, the fourth electrode of the second FET, the fourth electrode of the third FET, and the fourth electrode of the fourth FET are connected.”
Qin, which teaches a FET having two top gate and two bottom gate structures that opposite each other (Qin, Abstract), discloses:
first and second electrodes on a gate dielectric of the FET, (Qin, Fig. 4, a third gate structure 4031C and fourth gate structure 4031D on the gate dielectrics 4021C and 4021D which are made of the same material)
third and fourth electrodes on the substrate of the FET, (Qin, Fig 4, first gate structure 4032A and second gate structure 4032B are on the substrate 401)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Uyemura to have first and second electrodes on a gate dielectric of the FET and third and fourth electrodes on the substrate of the FET as taught by Qin for purposes of reducing a parasitic effect in a high frequency mode. (Qin, Abstract)
Uyemura and Qin do not disclose:
“a third FET …;
a fourth FET …;
wherein:
the first electrode of the first FET, the first electrode of the second FET, the first electrode of the third FET, and the first electrode of the fourth FET are connected;
the second electrode of the first FET, the second electrode of the second FET, the second electrode of the third FET, and the second electrode of the fourth FET are connected;
the third electrode of the first FET, the third electrode of the second FET, the third electrode of the third FET, and the third electrode of the fourth FET are connected; and
the fourth electrode of the first FET, the fourth electrode of the second FET, the fourth electrode of the third FET, and the fourth electrode of the fourth FET are connected.”
Meiser, which teaches the use of multi-gated FETs (specifically double gated FETs) in devices including and inverter (Meiser, Abstract), discloses:
The following annotated Fig. 10B has been annotated by Examiner will be used in discussion:
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a third FET …; (Meiser, annotated Fig. 10B, FET3)
a fourth FET …; (Meiser, annotated Fig. 10B, FET4)
wherein:
the first electrode of the first FET, the first electrode of the second FET, the first electrode of the third FET, and the first electrode of the fourth FET are connected; (Meiser, annotated Fig. 10B the first electrode of the FET1, FET2, FET3, and FET4 are connected via controller unit 541.)
the second electrode of the first FET, the second electrode of the second FET, the second electrode of the third FET, and the second electrode of the fourth FET are connected; (Meiser, annotated Fig. 10B the second electrode of the FET1, FET2, FET3, and FET4 are connected via controller unit 541.)
the third electrode of the first FET, the third electrode of the second FET, the third electrode of the third FET, and the third electrode of the fourth FET are connected; and (Meiser, annotated Fig. 10B the third electrode of the FET1, FET2, FET3, and FET4 are connected via controller unit 541.)
the fourth electrode of the first FET, the fourth electrode of the second FET, the fourth electrode of the third FET, and the fourth electrode of the fourth FET are connected. (Meiser, annotated Fig. 10B the fourth electrode of the FET1, FET2, FET3, and FET4 are connected via controller unit 541.)
Meiser, which teaches the use of multi-gated FETs (specifically double gated FETs) in devices including and inverter, discloses a “controller unit 541 drives appropriate gate signals for the four double-gate FETs 530” thereby disclosing electrical connection of a multi-gated device. (Meiser, [0098].) Therefore, it would have been obvious to one skilled in the art to modify the device of Uyemura and Qin to modify the device to electrically connect the respective second, third, and fourth gate electrodes of the first, second, third, fourth, fifth, sixth, seventh, and eighth FETs as provided by Meiser for the purpose for providing appropriate gate signals.
Regarding claim 8, Meiser and Qin teach the elements of claim 7, as recited above.
Uyemura further teaches the first, second, third, and fourth FET being a complementary pair of nFET and pFET d devices. (Uyemura, page 119, “ An nFET-pFET group with a common gate is called a complementary pair.)
Meiser further teaches:
the fifth electrode (Meiser, annotated Fig. 10B, F1E5) of the first FET is connected to a supply voltage terminal; (Meiser, annotated Fig. 10B, F1E5 is electrically connected to the supply voltage)
the sixth electrode (Meiser, annotated Fig. 10B, F2E6) of the second FET (Meiser, annotated Fig. 10B, FET2) is connected to a supply voltage terminal; (Meiser, annotated Fig. 10B, F2E6 is electrically connected to the supply voltage)
the sixth electrode (Meiser, annotated Fig. 10B, F3E6) of the third FET (Meiser, annotated Fig. 10B, FET3) is connected to a ground terminal; and (Meiser, annotated Fig. 10B, F3E6 is electrically connected to the ground terminal)
the fifth electrode (Meiser, annotated Fig. 10B, F4E5) of the fourth FET (Meiser, annotated Fig. 10B, FET4) is connected to a ground terminal. (Meiser, annotated Fig. 10B, F4E6 is electrically connected to a ground terminal)
Meiser does not go into the details of the doping of the FETs of the inverter. However, Uyemura, which discloses CMOS Logic Device and in specific Chapter 3 discusses CMOS inverter design (Uyemura, page 119,) discloses that the basic inverter design requires a complementary pair of nFET-pFET. (See Uyemura, Section 3.1, pages 119- 120 and Fig. 3.2) Therefore it would have been prima facia obvious to a person skilled in the art to design a PMOS invert with complementary pairs of nFET and pFET devices for the purpose of designing an inverter as claimed by claim 8.
Regarding Claim 9:
The following annotated drawing will be used in discussion with Uyemura regarding claim 9 and 10 (NOR gate CMOS logic):
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Uyemura, Meiser and Qin disclose all the elements of claim 7.
Uyemura explicitly further discloses:
a fifth field-effect transistor (FET)… a fifth electrode on a source region of the FET, and a sixth electrode on a drain region of the FET; (Uyemura, Fig. 5.16 annotated, FET 5)
a sixth FET …. a fifth electrode on a source region of the FET, and a sixth electrode on a drain region of the FET; (Uyemura, Fig. 5.16 annotated, FET 3)
wherein:
the first electrode of the fifth FET, the first electrode of the sixth FET, … are connected; (Uyemura, Fig. 5.16 annotated, FET 5 and FET 6 are electrically connected. )
the sixth electrode of the first FET is connected to the fifth electrode of the fifth FET; (Uyemura, Fig. 5.16 annotated, connection point A)
the fifth electrode of the second FET is connected to the fifth electrode of the sixth FET; (Uyemura, Fig. 5.16 annotated, connection point B).
Uyemura explicitly disclosing a two input NOR gate.
Uyemura further discloses that an N-input NOR gate can be constructed by using complementary structuring with N nFETs in parallel, and N pFETs in series. (Uyemura, page 213, section 5.3.4 N-Input NOR) Therefore, Uyemura implicitly discloses the third FET, fourth FET, seventh FET, and eighth FET as well as the wiring construction in order to have a four input NOR gate.
Qin further discloses:
first and second electrodes on a gate dielectric of the FET, (Qin, Fig. 4, a third gate structure 4031C and fourth gate structure 4031D on the gate dielectrics 4021C and 4021D which are made of the same material)
third and fourth electrodes on the substrate of the FET, (Qin, Fig 4, first gate structure 4032A and second gate structure 4032B are on the substrate 401)
Therefore, the fifth, sixth, seventh, and eight FETs may be quad gate FET devices.
Meiser further discloses a “controller unit 541 drives appropriate gate signals for the four double-gate FETs 530” (Meiser, [0098]) thereby disclosing electrical connection of a multi-gated device. Therefore, it would have been obvious to one skilled in the art to modify the device of Uyemura and Qin to modify the device to electrically connect the respective second, third, and fourth gate electrodes of the first, second, third, fourth, fifth, sixth, seventh, and eighth FETs as provided by Meiser for the purpose for providing appropriate gate signals for control for use as a NOR gate.
Regarding claim 10, Uyemura, Qin, and Meiser teach the elements of claim 9 as recited above.
Uyemura explicitly further discloses:
the fifth FET is a p-channel FET; (Uyemura, annotated Fig. 5.16)
the sixth FET is a n-channel FET and the sixth electrode of the sixth FET is connected to a supply voltage terminal; (Uyemura, annotated Fig. 5.16, the sixth electrode is electrically connected to VDD by virtue of being on the same device.)
Furthermore, Uyemura implicitly discloses “the seventh FET is a p-channel FET, and the eighth FET is a n-channel FET and the fifth electrode of the eighth FET is connected to a ground terminal,” by necessity of the requirements of a 4-input NOR gate.
The following annotated drawing will be used in discussion with Uyemura regarding claim 11 and 12 (NAND gate CMOS logic):
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Regarding claim 11, Uyemura, Qin and Meiser teach the elements of claim 7 as recited above.
Uyemura further discloses:
a fifth field-effect transistor (FET)… a fifth electrode on a source region of the FET, and a sixth electrode on a drain region of the FET; (Uyemura, Fig. 5.5 annotated, FET 5)
a sixth FET …. a fifth electrode on a source region of the FET, and a sixth electrode on a drain region of the FET; (Uyemura, Fig. 5.5 annotated, FET 3)
wherein:
the first electrode of the fifth FET, the first electrode of the sixth FET, … are connected; (Uyemura, Fig. 5.5 annotated, FET 5 and FET 6 are electrically connected. )
the sixth electrode of the first FET is connected to the fifth electrode of the fifth FET; (Uyemura, Fig. 5.5 annotated, connection point A)
the fifth electrode of the second FET is connected to the fifth electrode of the sixth FET; (Uyemura, Fig. 5.5 annotated, connection point B).
Uyemura explicitly disclosing a two input NAND gate.
Uyemura further discloses that an N-input NAND gate can be constructed by using complementary structuring with N nFETs in parallel, and N pFETs in series. (Uyemura, page 213, section 5.3.4 N-Input NOR) Therefore, Uyemura implicitly discloses the third FET, fourth FET, seventh FET, and eighth FET as well as the construction in order to have a four input NAND gate.
Qin further discloses:
first and second electrodes on a gate dielectric of the FET, (Qin, Fig. 4, a third gate structure 4031C and fourth gate structure 4031D on the gate dielectric 4021C and 4021D which are made of the same material)
third and fourth electrodes on the substrate of the FET, (Qin, Fig 4, first gate structure 4032A and second gate structure 4032B on the substrate 401)
Therefore, the fifth, sixth, seventh, and eight FETs may be quad gate FET devices.
Meiser further discloses a “controller unit 541 drives appropriate gate signals for the four double-gate FETs 530” (Meiser, [0098]) thereby disclosing electrical connection of a multi-gated device. Therefore, it would have been obvious to one skilled in the art to modify the device of Uyemura and Qin to modify the device to electrically connect the respective second, third, and fourth gate electrodes of the first, second, third, fourth, fifth, sixth, seventh, and eighth FETs as provided by Meiser for the purpose for providing appropriate gate signals for control for use as a NAND gate.
Regarding claim 12, Uyemura, Qin and Meiser teach the elements of claim 7 as recited above.
Uyemura explicitly discloses:
the fifth FET is a p-channel FET and the fifth electrode of the fifth FET is connected to a supply voltage terminal; (Uyemura, annotated Fig. 5.5, FET5, the fifth electrode is by necessity electrically connected to ground by virtue of being on the same device.)
the sixth FET is a n-channel FET; (Uyemura, annotated Fig. 5.5, FET6)
Furthermore, Uyemura implicitly discloses “the seventh FET is a p-channel FET, and the eighth FET is a n-channel FET and the fifth electrode of the eighth FET is connected to a ground terminal,” by necessity of the requirements of a 4-input NAND gate.
Regarding claim 15, Uyemura, Qin and Meiser teach the elements of claim 7 as recited above.
Qin further discloses:
wherein the first, second, third, and fourth FETs are planar FETs. (Qin, Fig. 4 depicts a planer FET.)
Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over Uyemura, Qin, and Meiser as applied to claim 7 above, and further in view of Baumgartner et al. US 20100187575 A1 (hereinafter Baumgartner).
Regarding claim 16, Uyemura, Qin, and Meiser teach the elements of claim 7 as recited above.
Uyemura, Qin, and Meiser does not appear to disclose "wherein the first, second, third, and fourth FETs are FinFETs".
Baumgartner, which teaches an electronic device with multiple gate field-effect transistors (MUG-FET) (Baumgartner, [0003]), discloses:
wherein the first, second, third, and fourth FETs are FinFETs. (Baumgartner, [0046], the multiple gate FET made on FIN-FET.")
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Uyemura, Qin, and Meiser to have the first, second, third, and fourth FETs are FinFETs as modified by Baumgartner for purposes of having lower power consumption and enhanced device performance. (Baumgartner, [0046].)
Allowable Subject Matter
Claims 3, 4, 13, and 14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 3, the closest prior art would be a combination of Qin and Huang et al. US 20220166426 A1 (hereinafter Huang), as Qin teaches all the limitations of claim 2 and Huang teaches “wherein the source region is a first doped region (Huang, Fig. 2, the first drain/source body region 112 has a second conductivity type 114 and is near the first source contact [0041-0042]) in the substrate and the drain region is a second doped region in the substrate (Huang, Fig 2, the second drain/source body region 122 has a second conductivity type 124 and is near the second source contact 126).
However, neither Qin or Huang appear to teach “the apparatus further comprises a third doped region in the substrate and a fourth doped region in the substrate,
wherein the third and fourth doped regions in the substrate are opposite polarity from the first and second doped regions, the third electrode is on the third doped region, and the fourth electrode is on the fourth doped region.”
Regarding Claim 4, the closest prior art would be a combination of Qin and Huang because Qin teaches all the limitations of claim 2 and Huang teaches:
“wherein the first electrode is nearer to the first doped region than the second doped region,(Huang, Fig. 2, first gate 134 is near the first doped region 114)
the second electrode is nearer to the second doped region than the first doped region (Huang, Fig. 2, second gate 136 is near the second source contact 126)”.
However, neither Qin or Huang appear to teach “the third doped region is nearer to the first doped region than the second doped region, and
the fourth doped region is nearer to the second doped region than the first doped region.”
Regarding Claim 13, the closest prior art would be a combination of Uyemura, Qin, and Meiser as described above for claim 7. It would be a logical variation of the controller unit 541 to be comprised of traditional MOSFETs like those of described in claim 13 for the purpose of driving the appropriate gate signals however the wiring does not appear to be disclosed in Meiser regarding the controller.
The second closest art would be a combination of Uyemura, Qin, Meiser, and Hanagami which includes a black box input device 205 which is connected to an intermediate circuit 210. Where the input device receives an input signal which are transformed into the first intermediate signals to the intermediate circuit 210. (Hanagami, Fig. 2, [0029].) However, Hanagami does not appear to teach the wiring as described claim 13.
Regarding Claim 14 the closest prior art would be a combination of Uyemura, Qin, Meiser, and Hanagami where the output circuit 215 receives the intermediate signals from the intermediate circuit 215 and provide an output signal that is in a logical state equivalent to that of the input signal. (Hanagami, Fig. 2, [0031].) However, Hanagami does not appear to disclose the wiring as described by claim 14.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wen et al. US 20160056295 A1 – Fig. 8A teaches a pFET and nFET inverter design used in SRAM.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HEIM KIRIN GREWAL/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812