Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 2 and 10 are withdrawn from considerations pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on December 23, 2024.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed December 29, 2025. Claims 1, 9, 21, and 23 are amended. Claims 5, 11, and 22 are cancelled. Claims 28-30 are newly added. Claims 2 and 10 remain withdrawn. The Examiner notes that claims 1, 3-4, 6-9, 12-14, 21, 23, and 25-30 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 is rejected under 35 U.S.C. 103 as being unpatentable over Peng (US 2021/0343645 A1) in view of Kim (US 2020/0373331 A1).
With respect to claim 1, Peng teaches in Fig. 1A-1D:
An integrated circuit (integrated circuit 100a) comprising:
a first semiconductor device (transistor including semiconductor layers 104 above strip structure 120a) having a first semiconductor region (104 above 120a) extending between a first source region and a first drain region (epitaxy structures 150a on either side of the semiconductor regions);
a second semiconductor device (transistor including semiconductor layers 104 above strip structure 120b) having a second semiconductor region (104 above 120b) extending between a second source region and a second drain region (epitaxy structure 150b on either side of 104 above 120b);
a gate structure (gate structure 130) comprising a conductive gate layer (gate conductive layer 136) and a gate dielectric layer (gate dielectric layer 134),
the gate structure extending over the first semiconductor region and the second semiconductor region (see Fig. 1C);
a gate cut structure (para. 34, “dielectric layer 176 and underlying dummy fins 160 are capable of functioning as insulating gate-cut structures”) comprising a dielectric material (dielectric layer 176),
the gate cut structure being between the first semiconductor device and the second semiconductor device such that the gate cut structure interrupts the conductive gate layer and extends through an entire height of the conductive gate layer (see Fig. 1C),
wherein a first distance between the gate cut structure and the first semiconductor region is substantially the same as a second distance between the gate cut structure and the second semiconductor region (see Fig. 1C, gate cut appears to be centered between the semiconductor regions);
a dielectric layer (dielectric layer 114) beneath the gate cut structure (176 and 160) and the gate structure (130), such that a bottom surface of the gate cut structure and a bottom surface of the gate structure both physically contact a top surface of the dielectric layer (162 and 134 of 160 and 130 physically contact 114, see Fig. 1C);
a conductive layer (backside via 115) beneath the dielectric layer (114);
and a dielectric liner (dielectric liner 112) on outer sidewalls of both the conductive layer (115) and the dielectric layer (114),
wherein the dielectric liner (112) has a different material composition compared to the dielectric layer (114) (para. 22 “the dielectric layer 114 and the dielectric liner 112 include different materials.”)
wherein the first and second semiconductor (transistors above dielectric strips 120a and 120b) devices are on or above a semiconductor substrate (substrate 300),
Peng fails to teach:
and the conductive layer is within the semiconductor substrate or extends below a top surface of the semiconductor substrate
Kim teaches in Fig. 19C:
and the conductive layer (power delivery structure 160 and buried rail 150) is within the semiconductor substrate or extends below a top surface of the semiconductor substrate (horizontal portion of semiconductor layer 110)
Peng discloses the claimed invention except for the conductive layer within a semiconductor substrate. Kim teaches that it is known to include a buried rail and power delivery structure within and/or below a semiconductor substrate as shown in Fig. 19C. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to arrange the conductive layer below the semiconductor substrate, as taught by Kim in order to arrange a power distribution structure such that power is stably provided to a small device even with many wires and contacts within the device (para. 128). See MPEP 2144.
Claims 3, 7-8, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Peng (US 2021/0343645 A1) and Kim (US 2020/0373331 A1) as applied to independent claim 1 above in view of Xie (US 10,832,916 B1).
With respect to claim 3, Peng/Kim teaches all limitations of independent claim 1 upon which claim 3 depends. Peng further teaches:
wherein the gate cut structure is a first gate cut structure and the integrated circuit further comprises a second gate cut structure (see annotated Fig. 1C below)
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Peng/Kim fails to teach:
a second gate cut structure between the second semiconductor device and a third semiconductor device.
Xie teaches:
wherein the gate cut structure is a first gate cut structure (portion of 332 and 328 between 304-1 and 304-2) and the integrated circuit further comprises a second gate cut structure (portions of 332 and 328 between 304-3 and 304-4) between the second semiconductor device (transistor comprising fin 304-2) and a third semiconductor device (transistor comprising fin 304-4)
Peng/Kim teaches the claimed invention except there is only one gate cut structure between a first and second device. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a second gate cut structure between second and third semiconductor devices as taught by Xie, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04.
With respect to claim 7, Peng/Kim teaches all limitations of independent claim 1 upon which claim 7 depends. Peng/Kim fails to teach:
wherein the gate cut structure has a width between 5 nm and 20 nm
Xie teaches:
wherein the gate cut structure has a width between 15 to 35 nm col 9, lines 62-64 “the symmetric gate cut 1101 may have a width or horizontal thickness in the range of 15 to 35,”).
It has been ruled that “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists” (MPEP 2144.05(I)). In the instant case, the claimed range of 5 nm to 20 nm overlaps with the range of 15 to 35 nm of the prior art and is therefore obvious. For example, it would be obvious to modify the device of Peng to teach a gate structure with a width within the range taught by Xie chosen to make a gate cut structure with a width in the range of 5 nm to 20 nm for the purpose of “reducing the size of structural features and/or to provide a greater amount of structural features for a given chip size” (col. 1 lines 11-13)
With respect to claim 8, Peng/Kim teaches all limitations of independent claim 1 upon which claim 8 depends. Peng/Kim does not teach:
A die comprising the integrated circuit of claim 1
Xie further teaches:
A die comprising the integrated circuit (col. 14, lns. 5-9 “Various structures described above may be implemented in integrated circuits. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die”)
Peng/Kim discloses the claimed invention except for the implementation of the integrated circuit on a die. Xie discloses that it is known in the art to implement a similar integrated circuit on a die. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Peng/Kim to implement the integrated circuit of claim 1 on a die as taught by Xie because printing integrated circuits on dies is well known practice in semiconductor packaging. See MPEP 2144.
With respect to claim 8, Peng further teaches:
wherein the dielectric layer (114 above 115) is a first dielectric layer (see annotated Fig. 1C below) and the integrated circuit further comprises a second dielectric layer beneath the second gate cut structure that is different from the first dielectric layer (see annotated Fig. 1C), wherein a bottom surface of the second gate cut structure (portion of 160 above second dielectric layer) and a bottom surface of the gate structure (130) both physically contact a top surface of the second dielectric layer.
With respect to claim 28, Peng further teaches:
wherein the dielectric layer (portion of 114 above 115) is a first dielectric layer and the integrated circuit further comprises a second dielectric layer beneath the second gate cut structure that is different from the first dielectric layer (see annotated Fig. 1C above),
wherein a bottom surface of the second gate cut structure (see annotated Fig. 1C above) and a bottom surface of the gate structure (130) both physically contact a top surface of the second dielectric layer (see annotated Fig. 1C above).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Peng (US 2021/0343645 A1), Kim (US 2020/0373331 A1), and Xie (US 10,832,916 B1) as applied to claim 3 above and further in view of Subramanian (US 2019/0305111 A1).
With respect to claim 4, Peng/Xie as applied above teaches all limitations of claims 1 and 3 upon which claim 4 depends.
Peng/Xie does not explicitly teach:
The integrated circuit of claim 3, wherein the first gate cut structure has a first width and the second gate cut structure has a second width that is smaller than the first width.
Subramanian teaches in Figs. 11A-11C:
wherein the first gate cut structure (gate endcap isolation structure 1150) has a first width and the second gate cut structure (gate endcap isolation structure 1126) has a second width that is smaller than the first width (para. 98, “The gate endcap isolation structure 1126 has a width narrower than a corresponding width of gate endcap isolation structure 1150”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Subramanian into the device of Peng/Kim/Xie to include gate cut structures with different widths. The ordinary artisan would have been motivated to modify Peng/Kim/Xie in the manner set forth above for the purpose of separating adjacent fins with different spacings (para. 200 of Subramanian.)
Claims 6, 9, 11-12, 14, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Peng (US 2021/0343645 A1), Kim (US 2020/0373331 A1), Xie (US 10,832,916 B1) and Hwang (Solid State Technology 59.5 (2016)).
With respect to claim 6, Peng/Kim teaches all limitations of claim 1 upon which claim 6 depends.
With respect to claim 6, Peng teaches in Fig. 1A-1D that the gate cut structure appears to be equidistant to the two semiconductor regions but does not teach a process tolerance. Therefore, Peng does not explicitly teach:
wherein the first distance between the gate cut structure and the first semiconductor region is within 1 nm of the second distance between the gate cut structure and the second semiconductor region.
Xie teaches in Fig. 1, col 4, lines 24-26:
wherein the first distance between the gate cut structure and the first semiconductor region is within 1 nm of the second distance between the gate cut structure and the second semiconductor region (The aligned gate cut 101 represents an ideal case, where the gate cut 101 is perfectly aligned between the adjacent fins 104 and has a small critical dimension 10)
Although Xie discloses a critical dimension uniformity of 5 nm (col 4, lines 44-47) resulting in not all manufactured devices being in precise alignment it can be assumed that during production there will be devices that fall within the 1 nm tolerance of claim 6.
Peng/Kim discloses the claimed invention except for specifying that the uniformity of the distances is within 1 nm. Xie discloses that it is known in the art to provide a distances that are perfectly aligned. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide Peng/Kim with the distances between the gate cut and the semiconductor structures to be within 1 nm of each other in order to improve the uniformity of the device. See MPEP 2144.
Alternatively, Hwang teaches on page 20, column 2, line 2-4:
“Sophisticated software algorithms have also been developed to use process trends, chamber calibration data, and wafer metrology information to automatically create the appropriate thermal maps. With this capability, incoming non-uniformity can be reduced to less than 0.5 nm CDU after etch”
Therefore, using the methods of Hwang it would be possible to create the ideal device of Peng/Kim/Xie that is perfectly aligned to less than 1 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Hwang into the device of Peng/Kim/Xie to use an etching method with a CDU under 0.5 nm. The ordinary artisan would have been motivated to modify Peng/Xie in the manner set forth above for the purpose reducing non-uniformity to less than 0.5 nm (page 20, col. 2, lines 2-4 of Hwang.)
With respect to claim 9, Peng teaches in Fig. 1A-1D:
An electronic device, comprising:
an integrated circuit comprising a first semiconductor device (transistor including semiconductor layers 104 above strip structure 120a) having a first semiconductor region (104 above 120a) extending between a first source region and a first drain region (epitaxy structures 150a on either side of the semiconductor regions);
a second semiconductor device (transistor including semiconductor layers 104 above strip structure 120b) having a second semiconductor region (104 above 120b) extending between a second source region and a second drain region (epitaxy structure 150b on either side of 104 above 120b);
a gate structure (gate structure 130) comprising a conductive gate layer (gate conductive layer 136) and a gate dielectric layer (gate dielectric layer 134),
the gate structure extending over the first semiconductor region and the second semiconductor region (see Fig. 1C);
a gate cut structure (para. 34, “dielectric layer 176 and underlying dummy fins 160 are capable of functioning as insulating gate-cut structures”) comprising a dielectric material (dielectric layer 176),
the gate cut structure being between the first semiconductor device and the second semiconductor device such that the gate cut structure interrupts the conductive gate layer and extends through an entire height of the conductive gate layer (see Fig. 1C),
a dielectric layer (dielectric layer 114) beneath the gate cut structure (176 and 160) and the gate structure (130), such that a bottom surface of the gate cut structure and a bottom surface of the gate structure both physically contact a top surface of the dielectric layer (162 and 134 of 160 and 130 physically contact 114, see Fig. 1C);
a conductive layer (backside via 115) beneath the dielectric layer (114);
and a dielectric liner (dielectric liner 112) on outer sidewalls of both the conductive layer (115) and the dielectric layer (114),
wherein the dielectric liner (112) has a different material composition compared to the dielectric layer (114) (para. 22 “the dielectric layer 114 and the dielectric liner 112 include different materials.”)
wherein the first and second semiconductor (transistors above dielectric strips 120a and 120b) devices are on or above a semiconductor substrate (substrate 300),
Peng does not teach:
and the conductive layer is within the semiconductor substrate or extends below a top surface of the semiconductor substrate
a chip package comprising one or more dies, at least one of the one or more dies comprising
wherein a first distance between the gate cut structure and the first semiconductor region is within 1.5 nm of a second distance between the gate cut structure and the second semiconductor region, wherein each of the first distance and the second distance is measured in an imaginary horizontal plane that passes through each of the gate cut structure, the first semiconductor region, and the second semiconductor region
Kim teaches in Fig. 19C:
and the conductive layer (power delivery structure 160 and buried rail 150) is within the semiconductor substrate or extends below a top surface of the semiconductor substrate (horizontal portion of semiconductor layer 110)
Peng discloses the claimed invention except for the conductive layer within a semiconductor substrate. Kim teaches that it is known to include a buried rail and power delivery structure within and/or below a semiconductor substrate as shown in Fig. 19C. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to arrange the conductive layer below the semiconductor substrate, as taught by Kim in order to arrange a power distribution structure such that power is stably provided to a small device even with many wires and contacts within the device (para. 128). See MPEP 2144.
Xie teaches in Fig. 1A, col 4 lines 26-29 and col 14, lines 5-20:
a chip package comprising one or more dies (col 14, lines 5-20), at least one of the one or more dies comprising a first semiconductor device
wherein a first distance between the gate cut structure and the first semiconductor region is within 1.5 nm of a second distance between the gate cut structure and the second semiconductor region, wherein each of the first distance and the second distance is measured in an imaginary horizontal plane that passes through each of the gate cut structure, the first semiconductor region, and the second semiconductor region (The aligned gate cut 101 represents an ideal case, where the gate cut 101 is perfectly aligned between the adjacent fins 104 and has a small critical dimension 10).
Although Xie discloses a critical dimension uniformity of 5 nm (col 4, lines 44-47) resulting in not all manufactured devices being in precise alignment it can be assumed that during production there will be devices that fall within the 1.5 nm tolerance of claim 9.
Peng/Kim discloses the claimed invention except for specifying that the uniformity of the distances is within 1.5 nm and that the integrated circuit is implemented in a chip package comprising one or more dies. Xie discloses that it is known in the art to provide distances that are perfectly aligned. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide Peng/Kim with the distances between the gate cut and the semiconductor structures to be within 1.5 nm of each other in order to improve the uniformity of the device and to implement the IC on a chip package comprising one or more dies because printing integrated circuits on dies that are included in chip packages is a well-known practice in the art. See MPEP 2144.
Alternatively, Hwang teaches on page 20, column 2, line 2-4:
“Sophisticated software algorithms have also been developed to use process trends, chamber calibration data, and wafer metrology information to automatically create the appropriate thermal maps. With this capability, incoming non-uniformity can be reduced to less than 0.5 nm CDU after etch”
Therefore, using the methods of Hwang it would be possible to create the ideal device of Peng/Kim/Xie that is perfectly aligned to less than 1.5 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Hwang into the device of Peng/Kim/Xie to use an etching method with a CDU under 0.5 nm. The ordinary artisan would have been motivated to modify Peng/Xie in the manner set forth above for the purpose reducing non-uniformity to less than 0.5 nm (page 20, col. 2, lines 2-4 of Hwang.)
With respect to claim 12, Peng teaches:
wherein the gate cut structure is a first gate cut structure and the at least one of the one or more dies further comprises a second gate cut structure (portions of 332 and 328 between (see annotated Fig. 1C above)
Xie further teaches:
wherein the gate cut structure is a first gate cut structure (portion of 332 and 328 between 304-1 and 304-2) and the at least one of the one or more dies further comprises a second gate cut structure (portions of 332 and 328 between 304-3 and 304-4) between the second semiconductor device (transistor comprising fin 304-2) and a third semiconductor device (transistor comprising fin 304-4)
Peng/Xie/Hwang as combined above teaches the claimed invention except there is only one gate cut structure between a first and second device. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a second gate cut structure between second and third semiconductor devices as taught by Xie, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04.
With respect to claim 14, Peng/Kim/Xie/Hwang does not explicitly teach:
The electronic device of claim 9, further comprising a printed circuit board, wherein the chip package is attached to the printed circuit board.
However, it would be obvious to one of ordinary skill in the art to incorporate a chip package into a printed circuit board as this is standard practice in the art and/or so as to enable integration of the device of Peng/Xie/Hwang into more complex devices via a PCB so as to achieve the level of integration disclosed by Xie (col 14, lines 18-22, “The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor”)
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Peng (US 2021/0343645 A1) in view of Kim (US 2020/0373331 A1), Xie (US 10,832,916 B1) and Hwang (Solid State Technology 59.5 (2016)) as applied to claim 12 above and further in view of Subramanian (US 2019/0305111 A1).
With respect to claim 13, Peng/Kim/Xie/Hwang as applied above teaches all limitations of claims 9 and 12 upon which claim 13 depends.
Peng/Kim/Xie/Hwang fails to teach:
wherein the first gate cut structure has a first width and the second gate cut structure has a second width that is smaller than the first width
Subramanian teaches in Figs. 11A-11C:
wherein the first gate cut structure (gate endcap isolation structure 1126) has a first width and the second gate cut structure (gate endcap isolation structure 1150) has a second width that is smaller than the first width (para. 98, “The gate endcap isolation structure 1126 has a width narrower than a corresponding width of gate endcap isolation structure 1150”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Subramanian into the device of Peng/Xie/Hwang to include gate cut structures with different widths. The ordinary artisan would have been motivated to modify Peng/Xie/Hwang in the manner set forth above for the purpose of separating adjacent fins with different spacings (para. 200 of Subramanian.)
With respect to claim 29, Peng further teaches:
wherein the dielectric layer (114) is a first dielectric layer (see annotated Fig. 1C above) and the at least one of the one or more dies further comprises a second dielectric layer beneath the second gate cut structure that is different from the first dielectric layer (see annotated Fig. 1C above),
wherein a bottom surface of the second gate cut structure (see annotated Fig. 1C above) and a bottom surface of the gate structure (130) both physically contact a top surface of the second dielectric layer (see annotated Fig. 1C above).
Claims 21, 22, 26-27, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Xie (US 10,832,916 B1) in view of Peng (US 2021/0343645 A1) and Kim (US 2020/0373331 A1).
With respect to claim 21, Xie teaches:
a first semiconductor device (transistor that comprises fin 304-1) having a first semiconductor region (fin 304-1 and portions of channel layers 310 above it) extending in a first direction (vertical in Fig. 14) between a first pair of source (source/drain 318 in Fig. 5B) or drain regions (318 in Fig. 5B);
a second semiconductor device (device comprising the transistors comprising fins 304-2 and 304-3) having a second semiconductor region (fins 304-2 and 304-3 and portions of channel layers 310 above it) extending in the first direction between a second pair of source (318 in Fig. 5B) or drain regions (318 in Fig. 5B);
a third semiconductor device (transistor comprising fin 304-4) having a third semiconductor region (fin 304-4 and portion of channel layers 310 above it) extending in the first direction between a third pair of source (318 in Fig. 5B) or drain regions (318 in Fig. 5B);
a gate structure (334) comprising a conductive gate layer (col 10, lines 18-19 “gate conductor layer”) and a gate dielectric layer (col. 10, lns. 16-19 “The gate structures 334 may include a gate dielectric layer that is conformally deposited followed by formation of a gate conductor layer”), the gate structure extending over the first semiconductor region (fin 304-1) and the second semiconductor region (fin 304-2) (Fig. 14);
a first gate cut structure (332 that filled symmetric gate cut 1101 and portion of 328 between first and second device) comprising a dielectric material (col 10, lines 6-7, “the dielectric material 332 may comprise SiN, SiCO, SiC, or another suitable material”), the first gate cut structure being between the first semiconductor region and the second semiconductor region along a second direction (left to right on Fig. 14) orthogonal to the first direction,
a second gate cut structure (portion of 332 that filled asymmetric gate cut 1103 and portion of 328 between second and third device) comprising a dielectric material (col 10, lines 6-7, “the dielectric material 332 may comprise SiN, SiCO, SiC, or another suitable material”), the second gate cut structure being between the second semiconductor region and the third semiconductor region (Figs. 14) along the second direction, and extending through an entire height of the gate structure (332+328 e between 304-3 and 304-4 extends through the entire height of 334)
a dielectric layer (portion of STI layer 306 between 304-3 and 304-4, col. 6, ln. 42 “may be formed of a dielectric material”) beneath the second gate cut structure (332+328 between 304-3 and 304-4) and the gate structure (334), such that a bottom surface of the gate cut structure (bottom surface of self aligned isolation layer 328) and the gate structure (bottom surface of 334) both physically contact a top surface of the dielectric layer (top surface of 306);
and wherein the second gate structure has a different width (width at the top of the portion of 328 between 304-3 and 304-4) along the second direction than the first gate cut structure (width of 328 between 304-1 and 304-2)
and wherein the first, second, and third semiconductor devices (transistors comprising fins 304-1, 304-2, and 304-4, respectively) are on or above a semiconductor substrate (substrate 302),
Xie does not explicitly teach in the embodiment of Figs. 3-14:
wherein a first distance between the first gate cut structure and the first semiconductor region along the second direction is substantially the same as a second distance between the first gate cut structure and the second semiconductor region along the second direction;
wherein a third distance between the second gate cut structure and the second semiconductor region along the second direction is substantially the same as a fourth distance between the second gate cut structure and the third semiconductor region along the second direction,
a conductive layer beneath the dielectric layer
and a dielectric liner on outer sidewalls of both the conductive layer and the dielectric layer,
wherein the dielectric liner has a different material composition compared to the dielectric layer.
and the conductive layer is within the semiconductor substrate or extends below a top surface of the semiconductor substrate.
Xie teaches in Fig. 1A, col 4 lines 26-29:
“The aligned gate cut 101 represents an ideal case, where the gate cut 101 is perfectly aligned between the adjacent fins 104 and has a small critical dimension 10”
Therefore, the embodiment of Fig. 14 of Xie modified by the teaching of the embodiment of Fig. 1 in which ideal gate cuts are centered between fins teaches:
wherein a first distance (see annotated Fig. 14 below) between the first gate cut structure (portion of 328 between 304-1 and 304-2 and symmetric portion of 332) and the first semiconductor region (304-1) along the second direction is substantially the same as a second distance (see annotated Fig. 14 below) between the first gate cut structure and the second semiconductor region (304-2 and 304-3) along the second direction (See Fig. 14 below, the distances are taken to be the distances between the edge of the semiconductor regions and the first bisecting line through the midpoint between the semiconductor regions, which falls within the first gate cut structure);
wherein a third distance (see annotated Fig. 14 below) between the second gate cut structure (328 between 304-3 and 304-4 and asymmetric part of 332) and the second semiconductor region (304-2 and 304-3 and channel layers 310 above them) along the second direction is substantially the same as a fourth distance (see annotated Fig. 14 below) between the second gate cut structure (328 between 304-3 and 304-4 and asymmetric part of 332) and the third semiconductor region (304-4 and portions of channel layers 310 above it) along the second direction (See Fig. 14 below, the distances are taken to be the distances between the edge of the semiconductor regions and the second bisecting line through the midpoint between the semiconductor regions, which falls within the second gate cut structure);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of the embodiment of Fig. 1 of Xie into the embodiment of Fig. 14 of Xie. The ordinary artisan would have been motivated to modify Xie in the manner set forth above for the purpose of reducing the critical dimension of the gate cute structure (col 4, lines 24-36.)
Peng teaches in Fig. 1A-1D:
a conductive layer (backside via 115) beneath the dielectric layer (114);
and a dielectric liner (dielectric liner 112) on outer sidewalls of both the conductive layer (115) and the dielectric layer (114),
wherein the dielectric liner (112) has a different material composition compared to the dielectric layer (114) (para. 22 “the dielectric layer 114 and the dielectric liner 112 include different materials.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Peng into the device of Xie to include a conductive layer beneath the dielectric layer with a dielectric liner surrounding the conductive and dielectric layer. The ordinary artisan would have been motivated to modify Xie in the manner set forth above for the purpose of integrating a backside power rail into the device (abstract of Peng).
Kim teaches in Fig. 19C:
and the conductive layer (power delivery structure 160 and buried rail 150) is within the semiconductor substrate or extends below a top surface of the semiconductor substrate (horizontal portion of semiconductor layer 110)
Peng/Xie discloses the claimed invention except for the conductive layer within a semiconductor substrate. Kim teaches that it is known to include a buried rail and power delivery structure within and/or below a semiconductor substrate as shown in Fig. 19C. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to arrange the conductive layer below the semiconductor substrate, as taught by Kim in order to arrange a power distribution structure such that power is stably provided to a small device even with many wires and contacts within the device (para. 128). See MPEP 2144.
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With respect to claim 26, Xie/Peng/Kim does not teach:
wherein the first gate cut structure and the second gate cut structure each has a width between 5 nm and 20 nm.
Xie teaches:
wherein the first gate cut structure (col 9, lines 62-64, “symmetric gate cut structure may have a width in the range of 15 to 35 nm”) and the second gate cut structure (col 10 lines 1-2 “the asymmetric gate cut 1103 may have a width or horizontal thickness in the range of 15 to 35 nm) each has a width between 15 nm and 35 nm.
It has been ruled that “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists” (MPEP 2144.05(I)). In the instant case, the claimed range of 5 nm to 20 nm overlaps with the range of 15 to 35 nm of the prior art and is therefore obvious. For example, it would be obvious to make a gate cut structure with a width in the range of 5 nm to 20 nm for the purpose of “reducing the size of structural features and/or to provide a greater amount of structural features for a given chip size” (col. 1 lines 11-13)
With respect to claim 27, Xie further teaches:
wherein the dielectric layer is a first dielectric layer (portion of 306 between 304-3 and 304-4) and the integrated circuit further comprises a second dielectric layer (portion of STI layer 306 between 304-1 and 304-2) beneath the first gate cut structure that is different from the first dielectric layer
With respect to claim 30, Peng further teaches:
wherein the second dielectric layer has a greater thickness compared to the first dielectric layer.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Xie (US 10,832,916 B1) in view of Peng (US 2021/0343645 A1) as applied to claim 22 above and further in view of Subramanian (US 2019/0305111 A1).
With respect to claim 23, Xie/Peng teaches all limitations of claim 22 upon which claim 23 depends.
Xie/Peng fails to teach:
wherein the first gate structure is wider than the second gate cut structure along the second direction.
Subramanian teaches:
wherein the first gate cut structure (gate endcap isolation structure 1150) is wider than the second gate cut structure (gate endcap isolation structure 1126) along the second direction. (para. 98, “The gate endcap isolation structure 1126 has a width narrower than a corresponding width of gate endcap isolation structure 1150”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Subramanian into the device of Xie/Peng to include gate cut structures with different widths. The ordinary artisan would have been motivated to modify Xie/Peng in the manner set forth above for the purpose of separating adjacent fins with different spacings (para. 200 of Subramanian.)
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Xie (US 10,832,916 B1) in view of Peng (US 2021/0343645 A1) as applied to independent claim 21 above and further in view of Hwang (Solid State Technology 59.5 (2016))
With respect to claim 25, Xie/Peng teaches all limitations of claim 21 upon which claim 25 depends. Xie further teaches:
wherein the first distance is within 1 nm of the second distance, and the third distance is within 1 nm of the fourth distance
Although Xie discloses a critical dimension uniformity of 5 nm (col 4, lines 44-47) resulting in not all manufactured devices being in precise alignment it can be assumed that during production there will be devices that fall within the 1 nm tolerance of claim 25. Furthermore, even in cases of slight misalignment the distances can be measured such that the first and second distances and third and fourth distances are equal as long as the midpoint between the semiconductor regions is within the gate cut structure.
Alternatively, Hwang teaches on page 20, column 2, line 2-4:
“Sophisticated software algorithms have also been developed to use process trends, chamber calibration data, and wafer metrology information to automatically create the appropriate thermal maps. With this capability, incoming non-uniformity can be reduced to less than 0.5 nm CDU after etch”
Therefore, using the methods of Hwang it would be possible to create the ideal device of Xie that is perfectly aligned to less than 1 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Hwang into the device of Xie/Peng to use an etching method with a CDU under 0.5 nm. The ordinary artisan would have been motivated to modify Xie/Peng in the manner set forth above for the purpose reducing non-uniformity to less than 0.5 nm (page 20, col. 2, lines 2-4 of Hwang.)
Response to Arguments
Applicant’s arguments with respect to claims 1, 9, 21, and their dependents have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897