DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/15/2025 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 22 and 32-38 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 22, the limitation “a core region” is unclear as to how it is related to the core region recited in claim 21.
Regarding claim 32, the limitations “a first (second) gate insulating layer disposed between the first (second) tubular gate pattern and a first (second) channel portion, of the channel portions, inserted into the central area of the first (second) tubular gate pattern,” is unclear as to what element is required to be “inserted into the central area of the first (second) tubular gate pattern.” It is further unclear because “a first (second) channel portion, of the channel portions, inserted into the central area of the first (second) tubular gate pattern,” appears to contain punctuation which renders the meaning indefinite.
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 21-28 and 30-31, 39-41, 43-51 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Imai et al. (US 2019/0267391; herein “Imai.”).
Regarding claim 21, Imai discloses in Figs. 1-31B and related text a semiconductor memory device, comprising:
a stacked body including conductive patterns (46, see [0213]) and interlayer insulating layers (32, see [0148]) that are alternately stacked;
a lower channel portion (601/602/62 and lower portion of 160, see [0172], [0184], [0187]) passing through the stacked body;
a memory layer (50, see [0188]) disposed between the stacked body and the lower channel portion;
an upper channel portion (e.g. at least an upper portion of 160, see [0209]) disposed on the lower channel portion;
a gate insulating layer (e.g. 150 and 165, see [0191] and [0203]) enclosing a sidewall of the upper channel portion and extending between an upper section of the memory layer (upper section of 50) and the lower channel region;
a first gate pattern (e.g. 152, see [0196]) enclosing a portion of a sidewall of the gate insulating layer;
a separation insulating pattern (170’, see [0217]) contacting a first portion of the first gate pattern; and
wherein a semiconductor layer (160, see [0207]) of the upper channel portion fills a core region (the region of 160 which is defined by 150 at outer sides of the region) defined by the gate insulating layer at a level where the first gate pattern is disposed.
Regarding claim 22, Imai further discloses wherein the lower channel portion comprises:
a channel layer (601/602, see [0172] and [0184]) extending along an inner wall of the memory layer;
a core insulating layer (62, see [0187]) disposed within a core region defined by the channel layer; and
a semiconductor pattern (e.g. bottom portion of 160, see [0209]) disposed between the core insulating layer and the upper channel portion.
Regarding claim 23, Imai further discloses wherein the gate insulating layer (150 and 165 are the gate insulating layer) extends to a space between the first gate pattern (152) and the lower channel portion (601/602/62 and lower portion of 160).
Regarding claim 24, Imai further discloses
wherein the first gate pattern has a second portion extending from the first portion, and
wherein the first portion of the first gate pattern protrudes higher than the second portion of the first gate pattern in a longitudinal direction of the upper channel portion (note that one can choose “portions” of 152 such that the claimed limitation is met).
Regarding claim 25, Imai further discloses a conductive contact (88, see [0257]) disposed on the upper channel portion.
Regarding claim 26, Imai further discloses wherein a width of the conductive contact (88) is greater than a width of the upper channel portion (160).
Regarding claim 27, Imai further discloses
a second gate pattern (154, see [0020]) contacting a second portion of the first gate pattern,
wherein each of the gate insulating layer (e.g. in an interpretation where 150, 165 and additionally 175’ are the gate insulating layer) and the upper channel portion (160) protrudes higher than each of the first gate pattern (152) and the second gate pattern (154) in a first direction towards the conductive contact.
Regarding claim 28, Imai further discloses wherein the upper channel portion (160) protrudes higher than the gate insulating layer (150, 165 and 175’) in the first direction.
Regarding claim 30, Imai further discloses
a second gate pattern (154, see [0020]) contacting a second portion of the first gate pattern,
wherein the first gate pattern (152) includes a conductive barrier layer (e.g. TiN, see [0196]), and
wherein the second gate pattern (154) includes a metal layer (e.g. W or WN, see [0219]-[0220]).
Regarding claim 31, Imai further discloses wherein each of the first gate pattern (152) includes refractory metal (see [0196] and [0219]-[0220]).
Regarding claim 51, Imai further discloses a top of the conductive contact (88) is wider than a top of the upper channel portion (e.g. top of 160) (see Fig. 31A).
Regarding claim 39, Imai discloses in Figs. 1-31B and related text a semiconductor memory device, comprising:
a stacked body including conductive patterns (46, see [0213]) and interlayer insulating layers (32, see [0148]), the conductive patterns and the interlayer insulating layers being parallel to a plane, the conductive patterns being alternately arranged with the insulating layers in a first direction (vertical as in Fig. 24A) intersecting the plane;
a separation insulating pattern (e.g. 165 and 170’, see [0191] and [0217]) disposed over the stacked body, the separation insulating pattern including a horizontal portion (e.g. at least a portion of 165) parallel to the plane and a vertical portion (e.g. at least a portion of 170’) extending from the horizontal portion in the first direction;
a plurality of first channel portions (601/602/62, see [0172], [0184], [0187]) passing through the stacked body;
a memory layer (50, see [0188]) disposed between the stacked body and each of the plurality of first channel portions;
a plurality of second channel portions (e.g. at least a portion of 160, see [0209]) respectively disposed on the plurality of first channel portions and passing through the horizontal portion of the separation insulating pattern, the plurality of second channel portions including a first group of second channel portions (e.g. group at top of Fig. 24B) and a second group of second channel portions (e.g. group at bottom of Fig. 24B), the vertical portion of the separation insulating pattern being disposed between the first group of second channel portions and the second group of second channel portions;
a first select line (e.g. 152/154 on top of Fig. 24B, see [0196] and [0220]) surrounding the first group of second channel portions (see Fig. 24B) and extending over the horizontal portion of the separation insulating pattern (extending over 165, see Fig. 24A);
a second select line (e.g. 152/154 on bottom of Fig. 24B) surrounding the second group of second channel portions and extending over the horizontal portion of the separation insulating pattern (extending over 165, see Fig. 24A);
a gate insulating layer (e.g. 150, see [0203]) disposed between a sidewall of each of the plurality of second channel portions (160) and a corresponding one of the first select line and the second select line;
wherein a semiconductor layer (160, see [0207]) of each of the plurality of second channel portions fills a core region (the region of 160 which is defined by 150 at outer sides of the region) defined by the gate insulating layer at a level where each of the first and second select lines is disposed.
Regarding claim 40, Imai further discloses
wherein the vertical portion of the separation insulating pattern (the at least a portion of 170’) includes a first surface facing the first select line and a second surface facing the second select line (see Fig. 24B),
wherein the first surface includes a first groove (see Fig. 24B), and
wherein the second surface includes a second groove (see Fig. 24B).
Regarding claim 41, Imai further discloses
wherein the first group of second channel portions (group of 160 at top of Fig. 24B) includes a first side-second channel portion in the first groove,
wherein the second group of second channel portions (group of 160 at bottom of Fig. 24B) includes a second side-channel portion in the second groove,
wherein the first select line (top 152/154) extends between the vertical portion of the separation insulting pattern and the first side-second channel portion, and
wherein the second select line (bottom 152/154) extends between the vertical portion of the separation insulting pattern and the second side-second channel portion (see Fig. 24B).
Regarding claim 43, Imai further discloses wherein each of the plurality of first channel portions (601/602/62) comprises:
a channel layer (601/602, see [0172] and [0184]) extending along an inner wall of the memory layer;
a core insulating layer (62, see [0187]) surrounded by the channel layer; and
a semiconductor pattern (e.g. bottom portion of 160 in direct contact with 62, see [0209]) disposed between the core insulating layer and each of the plurality of second channel portions.
Regarding claim 44, Imai further discloses wherein each of the plurality of second channel portions (160) protrudes in the first direction higher than the first select line and the second select line (152/154).
Regarding claim 45, Imai further discloses wherein each of the plurality of second channel portions (160) protrudes in the first direction higher than the gate insulating layer (150).
Regarding claim 46, Imai further discloses wherein the gate insulating layer (e.g. in the interpretation where 150 and 175’ are the gate insulating layer) protrudes in the first direction higher than the first select line and the second select line (152/154).
Regarding claim 47, Imai further discloses a conductive contact (88, see [[0257]) disposed on each of the plurality of second channel portions (160).
Regarding claim 48, Imai further discloses wherein a width of the conductive contact (88) is greater than a width of each of the plurality of second channel portions (160).
Regarding claim 49, Imai further discloses
wherein each of the first select line and the second select line includes a first gate pattern (152) surrounding the gate insulating layer and a second gate pattern (154) surrounding the first gate pattern, and
wherein the first gate pattern includes a same conductive material as the second gate pattern (e.g. Ti or W, see [0196], [0219]-[0220]).
Regarding claim 50, Imai further discloses a top of the conductive contact (88) is wider than a top of the upper channel portion (e.g. top of 160) (see Fig. 31A).
Claim(s) 32-38 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanaka et al. (US 20200051995; herein “Tanaka”).
Regarding claim 32, Tanaka discloses in Figs. 19A-I and 20 (including similar features shown in accordance with Figs. 1-18B) and related text a semiconductor memory device, comprising:
a separation insulating pattern (e.g. 272 and 132, see [0141] and [0160]) including a first surface and a second surface that face in opposite directions (see also Fig. 9B);
a first groove formed in the first surface of the separation insulating pattern (a first groove in 272, see also Fig. 9B);
a second groove formed in the second surface of the separation insulating pattern (a second groove in 272, see also Fig. 9B);
a first line-shaped gate pattern (e.g. first 246, see [0125]; note 246 replaces 242) contacting the first surface of the separation insulating pattern and including a third groove that faces the first groove;
a second line-shaped gate pattern (e.g. second 246, see [0125]) contacting the second surface of the separation insulating pattern and including a fourth groove that faces the second groove;
a first tubular gate pattern (e.g. first 152, see [0145]) extending along a surface of the first groove and a surface of the third groove;
a second tubular gate pattern (e.g. second 152) extending along a surface of the second groove and a surface of the fourth groove;
channel portions (e.g. at least a portion of 153, see [0148]) inserted into central areas of the first and second tubular gate patterns; and
a first gate insulating layer (e.g. 150 around first 153, see [0147]) disposed between the first tubular gate pattern and a first channel portion, of the channel portions, inserted into the central area of the first tubular gate pattern,
a second gate insulating layer (e.g. 150 around second 153) disposed between the second tubular gate pattern and a second channel portion, of the channel portions, inserted into the central area of the second tubular gate pattern,
wherein the separation insulating pattern includes a horizontal portion (132) covering a bottom surface of each of the first line-shaped gate pattern and the second line-shaped gate pattern,
wherein each of the first and second gate insulating layers (150) includes an end portion extending at a lower level than a bottom surface of the horizontal portion of the separation insulating layer (lower than bottom surface of 132, see Fig. 19I).
Regarding claim 33, Tanaka further discloses wherein each of the first and second tubular gate patterns (152) comprises:
a first portion contacting the separation insulating pattern and a second portion extending from the first portion in a direction away from the separation insulating pattern,
wherein the first portion further protrudes higher than the second portion in a longitudinal direction of the channel portions (note that one can choose “portions” such that the claimed limitation is met).
Regarding claim 34, Tanaka further discloses
each of the first and second tubular gate patterns (152) includes a conductive barrier layer (see [0094]), and
each of the first and second line-shaped gate patterns (154) includes a metal layer (see [0124]-[0125]).
Regarding claim 35, Tanaka further discloses wherein each of the first tubular gate pattern, the second tubular gate pattern, the first line- shaped gate pattern, and the second line-shaped gate pattern includes refractory metal (see [0094] and [0124]-[0125]).
Regarding claim 36, Tanaka further discloses
the first tubular gate pattern (152) and the first line-shaped gate pattern (264) contact each other to form a first select line (see [0125]), and
the second tubular gate pattern (152) and the second line-shaped gate pattern (264) contact each other to form a second select line (see [0125]).
Regarding claim 37, Tanaka further discloses
lower channel portions (601/602, see [0064], [0077]) disposed under the channel portions;
a stacked body including interlayer insulating layers (32, see [0043]) and word lines (46, see [0125]) that enclose the lower channel portions and that are alternately disposed in a longitudinal direction of each of the lower channel portions; and
a memory layer (52/54/56, see [0064]) disposed between each of the lower channel portions and the stacked body.
Regarding claim 38, Tanaka further discloses wherein each of the word lines includes a conductive pattern having a planar shape that is overlapping with the first line-shaped gate pattern, the separation insulating pattern, and the second line-shaped gate pattern (see Fig. 20 at least).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imai as applied to claim 28 above, and in view of Kim (US 2015/0243672; herein “Kim”).
Regarding claim 29, Imai does not disclose wherein the conductive contact includes a groove into which the upper channel portion is inserted.
In the same field of endeavor, Kim teaches in Fig. 1 and related text a semiconductor device wherein the conductive contact (CAP, see [0028]) includes a groove into which the upper channel portion (CH, see [0023]) is inserted.
It would have been obvious to one of ordinary skill in the art to modify the device of Imai by having the conductive contact including a groove into which the upper channel portion is inserted, as taught by Kim, in order to increase a contact area between the channel and the conductive contact and resistance of the channel pattern may be reduced (see Kim [0078]).
Response to Arguments
Applicant's arguments filed 12/15/2025 have been fully considered but are not persuasive.
Applicant argues (page 14-15 and 15-16) that Imai does not teach or suggest the claimed invention of claims 21 and 39 because 160L does not fill a core region defined by the gate dielectric 150.
In response, the examiner disagrees. Specifically, the Examiner notes that in accordance with MPEP 2111, USPTO personnel are to give claims their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023, 1027-28 (Fed. Cir. 1997). Therefore the claim limitation “core region” has been given their broadest reasonable interpretation. The “region” is merely required to be at least partially “defined by” the gate insulating layer, and therefore a region can be chosen such that it begins at the gate insulating layer, but does not necessarily occupy the entirety of the space between the sides of the gate insulating layer.
Applicant's remaining arguments have been fully considered but are moot in view of the new grounds of rejection presented above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896 3/24/2026