DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05 March 2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Apparatus claims 11-18 will be discussed first, followed by method claims 1-8, and followed by apparatus claims 19-20.
Claims 1-6, 8, 11-16, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable by US 20200320375 A1 Abuhatzera et al. (hereinafter “Abuhatzera”) in view of Rastegari, Mohammad, et al. "Xnor-net: Imagenet classification using binary convolutional neural networks." European conference on computer vision. Cham: Springer International Publishing, 2016. (hereinafter “Rastegari”) in view of Chandel, Deepali, et al. "Booth multiplier: Ease of multiplication." International Journal of Emerging Technology and Advanced Engineering 3.3 (2013): 118-122. (hereinafter “Chandel”) in view of US 20200097253 A1 Clark et al. (hereinafter “Clark”) in view of Patterson, David A., and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface (5th Edition). Morgan Kaufmann, 2013. (hereinafter “Patterson”) in further view of US 20080270758 A1 Ozer et al. (hereinafter “Ozer”).
Regarding claim 11, Abuhatzera teaches a system comprising:
a processing circuit (Fig. 7, 710 containing 764, 718 [0106]) configured to perform a neural network inference operation ([0106], [0024]), the performing of the neural network inference operation comprising:
calculating (Fig. 5, 530; Fig. 6, 630), by a core (Fig. 7, 718 [0106], [0108-0112]) of the processing circuit, a first plurality of products, each of the first plurality of products (Fig. 2, output of 230) being the product of a weight (Fig. 1B, 182) and an activation (Fig. 1B, 184);
calculating, by the processing circuit, a first partial sum (Fig. 2, 250), the first partial sum being the sum being a sum of the first plurality ([0078], [0084-0089]) of products (Fig. 2, output of 250);
compressing, by the core (Fig. 7, 718 [0106], [0108-0112]) of the processing circuit, the first partial sum (Fig. 2, 155) to form a first compressed partial sum (Fig. 2, output of 155, output activation, [0041]), the first compressed partial sum (Fig. 2, output of 155, output activation, [0041]) having a first size, in bits, ([0059] re-encoder 140 re-encodes a 7-bit signed number into two 4-bit numbers and outputs to compression circuit 155, [0067, 0069-0070, 0076] compression circuit’s compression techniques, [0133]), wherein the first size is associated with an accuracy of a neural network ([0015-0016] quantizing from 32 to 8-bits); and
storing ([0041], [0048]), by the processing circuit, the first compressed partial sum (Fig. 2, output of 155, output activation, [0041]) at a first cache (Fig. 1A, 130, [0034], [0041]; Fig. 7, 762, [0107], [0110]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify with the alternative embodiment of the electronic computing device 700 of Fig. 7 which contains a cache 762. Abuhatzera generally teaches the first compressed partial sum (Fig. 2, output of 155, output activation) as being computed as a function of the Model Executor Processing Element (Fig. 2, 200), of which the Model Executor Processing Element is a component of the computing system (Fig. 1A, 100), as the model executor processing element 200 is the same ([0056]) as the model executor (Fig. 1A, 105) found in the computing system. While the computing system teaches storing the first compressed partial sum in a memory 130, it would have been obvious to modify as using a cache as a storage is a known technique in the art ([0125]). Thus, it would have been obvious to perform simple substitution of a known element in the art to obtain predictable results.
Although Abuhatzera generally teaches the first compressed partial sum (Fig. 2, output of 155, output activation), they are silent to teaching scaling the first plurality of products using a weight scaling factor and an activation scaling factor; and an encoded product of the weight scaling factor and the activation scaling factor. Further, Abuhatzera is silent with disclosing a second partial sum being the sum of a second plurality of products, and compressing the second partial sum to form a second compressed partial sum, the second compressed partial sum having a second size different from the first size, in bits; storing the second compressed partial sum in a second cache separate from the first cache. Further, Abuhatzera appears to be silent with disclosing a return path.
Rastegari teaches scaling using a weight scaling factor (Pg. 8, Binary Convolution section, scaling factor
α
, Pg. 5, 3-3.1, Para. 1) and an activation scaling factor (Pg. 8, Binary Convolution section, scaling factor
β
).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Abuhatzera’s neural network inference operation with Rastegari’s scaling technique because they are in the claimed invention’s same field of endeavor of
performing neural network inference operations (Pg. 11, 4.2, Para. 1). It would have been obvious to one of ordinary skill in the art to implement the scaling technique utilizing a weight scaling factor and an activation scaling factor, as it allows the operation to yield a higher classification accuracy (Pg. 12, Para. 2). Making this modification would be beneficial as Abuhatzera’s operation will yield more accurate classification results.
Rastegari and the combination of Abuhatzera in view of Rastegari are silent with disclosing an encoded product of the weight scaling factor and the activation scaling factor. Further, Rastegari and the combination of Abuhatzera in view of Rastegari are silent with disclosing a second partial sum being the sum of a second plurality of products, and compressing the second partial sum to form a second compressed partial sum, the second compressed partial sum having a second size different from the first size, in bits; storing the second compressed partial sum in a second cache separate from the first cache; a return path.
Chandel teaches an encoded product (Pg. 3, V, Para. 1, modified Booth encoding algorithm; Pg. 4, Col. 1-2, Sec. B. Radix-4, result of operand multiplication).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Abuhatzera in view of Rastegari’s neural network inference operation with Chandel’s encoding product technique because they are in the claimed invention’s same field of endeavor of computer architecture (Pg. 1, II, Para. 1). It would have been obvious to one of ordinary skill in the art to implement the encoding product technique, as multiplying to yield a product is a known technique in the art (Abstract, Pg. 1, I, Para. 2). It would have been obvious to try this known technique and yield predictable results, and further using the modified Booth encoding algorithms provides a more efficient way to compute than the previous approaches by reducing the number of partial products in computation (Pg. 3, V, Para. 1).
Chandel and the combination of Abuhatzera in view of Rastegari in view of Chandel are silent with disclosing a second partial sum being the sum of a second plurality of products, and compressing the second partial sum to form a second compressed partial sum, the second compressed partial sum having a second size different from the first size, in bits; storing the second compressed partial sum in a second cache separate from the first cache; a return path.
Clark teaches a second partial sum (Fig. 6, output of Adder block located in unit using 617 and 627, [0044]) being the sum of a second plurality of products (Fig. 6, S/CC from unit using 611 and 621, propagated to unit using 614 and 624, to finally unit using 617 and 627, [0044]), and compressing the second partial sum to form a second compressed partial sum (Fig. 7, 631 output from compress block, [0043]), the second compressed partial sum having a second size different from the first size, in bits ([0037]); storing the second compressed partial sum ([0044] memory system) in a second cache separate from the first cache.
Clark teaches the number of bits used for the outputs of multipliers with respect to Fig. 3, “307, 308, … 309”. However, although Clark is referring to a separate embodiment in Fig. 3 rather than the embodiment used in the claim mapping above, Fig. 6, functionally the operation of the multipliers is effectively similar. Fig. 6 illustrates the digital multiply-accumulator with carry compression configured to perform dot products ([0041]). Fig. 3 illustrates a digital multiplier circuit with compressed carry, however, the adder “320” outputs the results from multipliers “307, 308, … 309” and decompress “311” and can forward that output to another multiplier circuit cell for another multiply accumulate operation ([0038]). Thus, it would have been obvious to use the number of bits scheme of Fig. 3 in the other exemplary embodiment of Fig. 6.
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Abuhatzera in view of Rastegari in view of Chandel’s neural network inference operation with Clark’s second partial sum compression feature because they are in the claimed invention’s same field of endeavor of machine learning application, such as inferences ([0041], [0045]). It would have been obvious to one of ordinary skill in the art to implement the second partial sum compression feature, as doing so allows matrices to be processed into sections for calculations (Fig. 6, [0043]). Further, by having a second partial sum compression feature, it would allow the modified system to perform more types of computations, such as dot products, on a wide range of inputs ([0044]) such as using complex data structures, like matrices, for communicating data for processing. Thus, it would have been obvious to one of ordinary skill in the art to improve the Abuhatzera in view of Rastegari in view of Chandel’s modified operation by recognizing these advantages and making the modification.
Clark and the combination of Abuhatzera in view of Rastegari in view of Chandel in view of Clark are silent with explicitly disclosing a second cache separate from the first cache; a return path.
Patterson teaches a second cache separate from (Pg. 397, split cache) the first cache.
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Abuhatzera in view of Rastegari in view of Chandel in view of Clark’s neural network inference operation with Patterson’s second cache feature because they are in the claimed invention’s same field of endeavor of computer architecture (Pg. 383, Sec. 5.3, Para. 1). It would have been obvious to one of ordinary skill in the art to implement a separate, second cache, as doing so is a known technique in the art (Pg. 397, Elaboration section). Further, by splitting a basic cache into two split caches yields better hit rates (Pg. 397, Elaboration section), effectively reducing access time (Pg. 401, Para. 2; Pg. 402, Para. 1-2). Thus, it would have been obvious to one of ordinary skill in the art to improve the Abuhatzera in view of Rastegari in view of Chandel in view of Clark’s modified apparatus by recognizing these advantages and making the modification.
Patterson and the combination of Abuhatzera in view of Rastegari in view of Chandel in view of Clark in view of Patterson are silent with explicitly disclosing a return path.
Ozer discloses a return path (Fig. 2 “114” [0032]).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Abuhatzera in view of Rastegari in view of Chandel in view of Clark in view of Patterson’s neural network inference operation with Ozer’s return path feature because they are in the claimed invention’s same field of endeavor of cache-based architecture ([Abstract]). It would have been obvious to one of ordinary skill in the art to implement a return path as doing so would yield predictable results to improve the modified neural network inference operation. Modifying with Ozer’s return path feature would provide the option for omitting levels of the cache hierarchy when performing lookup and returning operations, which would tolerate a multiple cycle direct fetch while maintaining a dedicated whole bandwidth of a cache ([abstract], [0032]) and decrease delays ([0030]). Thus, it would have been obvious to one of ordinary skill in the art to improve the Abuhatzera in view of Rastegari in view of Chandel in view of Clark in view of Patterson’s modified apparatus by recognizing these advantages and making the modification.
Regarding claim 12, in addition to the teachings addressed in the claim 11
analysis, the rejection of claim 11 is incorporated and Abuhatzera teaches a system wherein:
the first size is at most 0.85 ([0059], [0067, 0069-0070, 0076], [0133]) of a size, in bits, of the first partial sum (Fig. 2, output of 250).
Regarding claim 13, in addition to the teachings addressed in the claim 11
analysis, the rejection of claim 11 is incorporated and Abuhatzera teaches a system wherein:
the first size is at most 0.5 ([0059], [0067, 0069-0070, 0076], [0133]) of a size, in bits, of the first partial sum (Fig. 2, output of 250).
Regarding claim 14, in addition to the teachings addressed in the claim 11
analysis, the rejection of claim 11 is incorporated and Abuhatzera teaches a system wherein:
the first compressed partial sum (Fig. 2, output of 155, output activation, [0041]) comprises an exponent (Fig. 3, 4 bit MSB) and a mantissa (Fig. 3, 3 bit LSB).
Regarding claim 15, in addition to the teachings addressed in the claim 14
analysis, the rejection of claim 14 is incorporated and Abuhatzera teaches a system wherein:
the first partial sum is an integer ([0024], [0026]), and the exponent (Fig. 3, 4 bit MSB) is an n-bit integer equal to
2
n
-
1
([0063] “[0,15]”) less an exponent difference, the exponent difference ([0061] branch for negatively signed integers) being a difference between:
a bit position of a leading 1 in a limit number (Fig. 3, “1” input to 322), and
the bit position of the leading 1 in the first partial sum (Fig. 3, 4 bit MSB input to 322).
Regarding claim 16, in addition to the teachings addressed in the claim 15
analysis, the rejection of claim 15 is incorporated and Abuhatzera teaches a system wherein:
n
=
4
(Fig. 3, 4 bit MSB).
Regarding claim 18, in addition to the teachings addressed in the claim 15
analysis, the rejection of claim 15 is incorporated and Abuhatzera teaches a system wherein:
the first partial sum (Fig. 2, 250) is greater than (Pg. 7, Table 1, Example Output, Signed #’s 2-63) the limit number (Fig. 3, “1” input to 322),
the exponent (Fig. 3, 4 bit MSB) equals
2
n
-
1
([0063] “[0,15]”), and
the mantissa (Fig. 3, 3 bit LSB) of the first compressed partial sum (Fig. 2, output of 155, output activation, [0041]) equals a mantissa of the limit number (Fig. 3, “1” input to 322).
Claims 1-6, 8 are directed to a method which recite substantially the same limitations of the device of claims 11-16, 18. All method limitations recited in claims 1-6, 8 are similarly practiced by the device limitations recited in claims 11-16, 18, respectively. The claims 11-16, 18 analysis equally applies to claims 1-6, 8.
Claims 19-20 are directed to a system that would be practiced by the system of claim 11. All steps recited in claims 19-20 are practiced by the system of claims 11 and 15, respectively. The claims 11 and 15 analysis equally applies to claims 19-20.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable by Abuhatzera in view of Rastegari in view of Chandel in view of Clark in view of Patterson in view of Ozer, in further view Ortiz, Marc, et al. "Low-precision floating-point schemes for neural network training." 2018. (hereinafter “Ortiz”).
Regarding claim 17, in addition to the teachings addressed in the claim 16
analysis, the rejection of claim 16 is incorporated and Abuhatzera teaches a system wherein:
the first compressed partial sum (Fig. 2, output of 155, output activation, [0041]) further comprises a sign bit ([0060], [0061-62], [0065]), and the mantissa (Fig. 3, 3 bit LSB) excluding an implicit 1 (Fig. 3, implicit “1” 324 or “0” 332).
Abuhatzera is silent to disclosing the mantissa as a 7-bit number, although
generally disclosing the mantissa as 3 bits (Fig. 3, 3 bit LSB) and capable of operating on
datatypes not limited to a 7-bit signed integer implementation ([0059-0060], Table 1).
Rastegari is similarly silent to disclosing a mantissa as a 7-bit number.
Chandel is similarly silent to disclosing a mantissa as a 7-bit number.
Abuhatzera in view of Rastegari in view of Chandel are silent with disclosing a mantissa as a 7-bit number.
Abuhatzera in view of Rastegari in view of Chandel in view of Clark in view of Patterson in view of Ozer are silent with disclosing a mantissa as a 7-bit number.
Ortiz teaches a mantissa as a 7-bit number (Pg. 7, Paragraph 2, 𝑐𝑜𝑛𝑡𝑒𝑥𝑡 −𝑓𝑙𝑜𝑎𝑡[𝐸, 𝑀] with E exponent and M mantissa bits, 𝑐𝑜𝑛𝑡𝑒𝑥𝑡 − 𝑓𝑙𝑜𝑎𝑡[4,7]).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Abuhatzera in view of Rastegari in view of Chandel in view of Clark in view of Patterson in view of Ozer with Ortiz’s higher mantissa number feature because they are in the claimed invention’s same field of endeavor of implementing lower precisions for more effective multiplication operations in neural networks [abstract]. Abuhatzera discloses using fewer mantissa bits than what is claimed. Modifying the length of the mantissa to include 4 additional bits would lead to additional architecture that would allow Abuhatzera’s system to increase the range of precision and representation (Pg. 8, Paragraph 2), yielding more accurate training results than those of lower mantissa bit numbers (Pg. 8, Table 3, 𝑐𝑜𝑛𝑡𝑒𝑥𝑡 −𝑓𝑖𝑥𝑒𝑑[6,6]).
Claim 7 is directed to a method which recite substantially the same limitations of the device of claim 17. All method limitations recited in claim 7 are similarly practiced by the device limitations recited in claims 17, respectively. The claim 17 analysis equally applies to claim 7.
Response to Arguments
35 USC 103.
Applicant’s arguments, see Remarks, with respect to the amendments of independent claims in Pg. 14, Para. 4-Pg. 15, Para. 1, filed 05 March 2026, with respect to the rejection(s) of claim(s) 1-8, 11-20 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ozer, as necessitated by the amendment.
Applicant asserts that, in rejecting claim 1, pages 13-14 of the Office action cite FIG. 2 of Abuhatzera and allege that "FIG. 2, output of 155, output activation" reads on "the first compressed partial sum" in claim 1. Furthermore, page 14 of the Office action alleges that paras. [0059] and [0133] of Abuhatzera disclose "having a first size, in bits" in claim 1. However, when determining if an invention is obvious, the Examiner must consider the subject matter "as a whole," not just individual components. Abuhatzera appears to not disclose that the output activation (e.g., the alleged first compressed partial sum) has a first size. Therefore, Abuhatzera fails to disclose the feature "the first compressed partial sum having a first size, in bits" in claim 1 (see Remarks Pg. 14, Para. 3).
Examiner respectfully disagrees. Abuhatzera discloses the first compressed partial sum (Fig. 2, output of 155, output activation, [0041]) having a first size, in bits, ([0059], [0067, 0069-0070, 0076], [0133]). Abuhatzera discloses the compression circuit 155 re-encodes and compresses output activations 174 ([0041]), as described in exemplary flow of a first mode (Fig. 1B 170) and in circuit components of Fig. 2, that were previously received from the re-encoder 140. The re-encoder re-encodes a 7-bit signed number into two 4-bit numbers ([0059]). In addition, the compressed data modes of Fig. 1B includes various compression techniques ([0068-0076]) where an 8-bit integer is compressed to 4-bits via masking ([0069]), via probability ratios ([0070]), and via gating ([0076]).
Conclusion
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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