DETAILED ACTION
Claims 1-3, 5, and 7-25 are pending.
Claims 10 and 14-25 have been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
In original paragraph 109, line 11, insert --computing-- after “(throughput)”.
In amended paragraph 114, line 2, replace “one or more scheduler unit(s)” with
--one or more scheduler units--. The parentheses are unnecessary when “one or more” is used.
Appropriate correction is required.
Drawings
Original FIG.3 is objected to for failing to comply with 37 CFR 1.84(i), which requires that words appear in a horizontal, left-to-right fashion when the page is either upright or turned so that the top becomes the right side. Note, from 37 CFR 1.84(f), that the top of the sheet is regarded as one of the shorter sides. Please rotate “Execution Dynamic Input Program”, “Backend Branch Program”, and “Backend Micro-Op IP Program” 180 degrees.
The replacement FIGs are objected to for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(l), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. The drawings are pixelated because applicant did not use black (RGB = 000), despite the drawings appearing black to the naked eye. This has been confirmed by the examiner by analyzing the color content of applicant’s submitted pdf file. In such a case, the dithering used to convert applicant's grayscale image to black and white will add white pixels to try to estimate applicant's "gray" color, and the final drawings may not print properly or may print with reduced quality. Therefore, applicant must be sure to use only black and white. Applicant may try the following process to correct the color content:
1. Open the drawings PDF file with Adobe Acrobat Pro DC (a similar Adobe product may work, but the examiner has only tested this in Adobe Acrobat Pro DC);
2. Click “File” and then click “Print”;
3. Select “Adobe PDF” as the printer. If not available, “Microsoft Print to PDF” may also work, though this has not been tested. If neither option is available, this process may not be applicable, and applicant should try to find an alternate way to print in only black and white.
4. Uncheck “Print in grayscale (black and white)”;
5. Uncheck “Save ink/toner”;
6. Click “Advanced”;
7. Under “Color Management”, for the “Color Profile” field, select “Black & White” near the bottom of the list. The examiner also had “Treat grays as K-only grays” checked, and “Preserve Black” checked.
8. Click “OK” and then click “Print”. The resulting PDF should comprise only black and white drawings. Please review the final drawings for potential unintended consequences of this process.
NOTE: The examiner notes that this particular process is customized to this particular set of drawings. It may not work on other sets of drawings in other applications. If applicant is unable to perform the above conversion, the examiner would be willing to perform the conversion and email the resulting pdf file to applicant for formal filing once all other objections are resolved, provided an Authorization for Internet Communications (PTO/SB/439) is on record (see MPEP 502.03).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) and/or or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Please ensure any replacement is in only black and white to avoid pixelation and further objection. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102/103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 7-9 and 11-13 are rejected under 35 U.S.C. 102(a)(1) as anticipated by Henry et al., U.S. Patent Application Publication No. 2012/0260067 A1, or, in the alternative, under 35 U.S.C. 103 as obvious over Henry in view of the examiner’s taking of Official Notice.
Referring to claim 1, Henry has taught an apparatus comprising:
Data-space Translation Logic (DTL) circuitry (FIG.1, at least 104) to receive a static input (FIG.1, at least 132) and a dynamic input (FIG.1, 124), the DTL circuitry to generate one or more outputs (FIG.1, 126; and/or FIG.2, 252 and/or 254) based at least in part on the static input and the dynamic input (based on a mode (defined by static input) and current instruction (at least part of the dynamic input), appropriate micro-instructions (and other signals) are output), wherein the one or more outputs comprise one or more of: a frontend branch hint, an immediate value, and a micro-operation instruction pointer (see FIG.2, which is an expanded view of translator 104. Within translator 104 is a micro-PC that outputs a micro-operation pointer address 254 to address ROM to access a desired micro-operation); and
a Jump Execution Unit (JEU) to send data from a register file for the dynamic input of the DTL circuitry (configuration register file 122 sends signal 136 as a dynamic input to the DTL circuitry (thus, 124 and 136 may make up the dynamic input). The examiner notes that the entirety of FIG.1 may be deemed a JEU, in part because this system is used to execute branch/jump instructions (e.g. paragraphs 29, 34, 61, and FIG.4, 412))
Regarding the limitation “wherein the DTL circuitry is to generate the one or more outputs prior to commencement of speculation operations in a processor”, this is not patentable for multiple reasons:
First, when a system includes branch prediction/speculation (FIG.1, 114), speculation operations include operations for writing a history update to the branch predictor (paragraph [0053]). As is known, in order to obtain a taken/not taken history outcome for a given branch, which occurs upon execution of the branch, the branch must first be fetched and decoded (to determine a branch is to even be performed). As such, this limitation amounts to claiming decoding/translating a branch prior to writing a result of execution of the branch”. This is necessarily the case in Henry per the flow of FIG.1, where instructions are fetched and decoded prior to execution in pipeline 112. Under this interpretation, the claim is rejected under 35 U.S.C. 102.
Alternatively, where the speculation operations are not interpreted to include a predictor update, but merely anything to do with speculation (including branch prediction), Henry has not explicitly disclosed the aforementioned limitation. However, Official Notice is taken that a given branch instruction could appearing anywhere in a program including after many previous instructions are fetched/decoded was well known in the art before applicant’s invention. With such a program, all of the fetching/decoding of non-branch instructions prior to a speculated/predicted branch would cause DTL 104 to generate outputs based on inputs before the branch in question is even predicted (speculated). This is merely a matter of program design, where a programmer may not require a branch until previous instructions establish a condition on which a branch may be predicted. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Henry to execute a program that includes a number of non-branch instruction prior to speculation of a conditional branch instruction so as to generate the one or more outputs prior to commencement of speculation operations in a processor.
Referring to claim 2, Henry, alone or as modified, has taught the apparatus of claim 1, wherein a frontend of the processor comprises the DTL circuitry (from FIG.1, anything prior to execution 112 is deemed the frontend of the processor. This includes DTL circuitry 104).
Referring to claim 5, Henry, alone or as modified, has taught the apparatus of claim 1, wherein the JEU is to block data associated with a mispredicted path to be sent for the dynamic input of the DTL circuitry (this is the purpose of unit 104 (e.g. see paragraph 53). As is known, a branch can branch either to instructions down a first taken path or a second not-taken path, depending on a condition. The predictor is used to predict which of the two paths the branch will branch to (before it is known which path the branch will actually branch to). This, the JEU only allows data (instruction) to be fetched and passed to the translator if they are part of the predicted path. Contrarily, the JEU blocks data/instructions associated with the incorrect (mispredicted) path from being fetched and translated).
Referring to claim 7, Henry, alone or as modified, has taught the apparatus of claim 1, wherein the DTL circuitry is to atomically program the one or more of a frontend branch hint (when the DTL circuitry is interpreted to include unit 114, a generated prediction for a branch is a frontend branch hint that hints at the branch path that will be executed (a prediction is programmed into the predictor during runtime)), an immediate value (from paragraph 25, an immediate operand may be in an instruction and subtracted from another operand. Thus, the immediate value as part of the instruction, goes through the decoder/translator, and to the execution unit for arithmetic processing (the immediate is programmed as the value to be subtracted)), and a micro-operation instruction pointer (again, see FIG.2, where the pointer is programmed into PC 232 so that it may be supplied to the ROM).
Referring to claim 8, Henry, alone or as modified, has taught the apparatus of claim 1, wherein the static input is to indicate a mode of operation for the DTL circuitry (from FIG.1, static input 132 indicates an instruction mode for the DTL circuitry. The mode may be x86 or ARM mode).
Referring to claim 9, Henry, alone or as modified, has taught the apparatus of claim 1, wherein the dynamic input is to change for each instruction (from FIG.1, the dynamic input is the current instruction 124 fetched from cache 102. Thus, the dynamic input changes for each instruction because the dynamic input is each instruction. A program with the instructions set forth in paragraph 25 would have dynamic inputs of “add”, “subtract”, “shift”, “branch”, and “load”).
Referring to claim 11, Henry, alone or as modified, has taught the apparatus of claim 1, wherein a plurality of processor cores of the processor are to share the DTL circuitry (see FIG.1 and FIG.4, where cores 412, 414, 416, and 418 receive microinstructions 126 from the single (shared) translator).
Referring to claim 12, Henry, alone or as modified, has taught the apparatus of claim 1, further comprising a backend DTL circuitry (FIG.2, 204+237 and/or 212) to generate one or more outputs based at least in part on the static input and the dynamic input (note that these circuits generate the outputs based on the inputs 124, 132, and 136).
Referring to claim 13, Henry, alone or as modified, has taught the apparatus of claim 12, wherein the backend DTL circuitry is to provide the one or more outputs to the JEU (the outputs (microinstructions 126) go to the execution units 112, which include branch/jump execution unit 412 to execute any branch/jump instruction).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Henry in view of the examiner’s taking of Official Notice.
Referring to claim 3, Henry, alone or as modified, has taught the apparatus of claim 1, but has not taught wherein the DTL circuitry comprises a Programmable Logic Array (PLA). However, Official Notice is taken that it was well known in the art, before applicant’s invention, to implement a translator/decoder with a PLA. A PLA is programmable/customizable to allow for different translations to occur. Additionally, a PLA is advantageous over a ROM, for instance, because it is known to use fewer transistors. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Henry such that the DTL circuitry comprises a Programmable Logic Array (PLA).
Claim 11 is alternatively rejected under 35 U.S.C. 103 as being unpatentable over Henry, optionally in view of the examiner’s taking of Official Notice, in view of Ge et al., U.S. Patent Application Publication No. 2016/0224349 A1.
Referring to claim 11, Henry, alone or as modified, has taught the apparatus of claim 1, but, when the claimed plurality of processor cores are not simply interpreted as execution units of Henry, Henry has not taught wherein a plurality of processor cores of the processor are to share the DTL circuitry. However, Ge has taught a multi-core system with a shared front-end including instruction decoder/translator (see FIG.9). Adding multiple cores to Henry would increase parallelism and throughput in Henry. And, by sharing front-end components, less duplicate hardware would need to be implemented, thereby saving chip space. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Henry such that a plurality of processor cores of the processor are to share the DTL circuitry.
Response to Arguments
On page 11 of applicant’s response, applicant states that double-patenting will be addressed upon indication of allowability and a desire by the Office to maintain the rejection.
The examiner notes that the double-patenting rejections have been withdrawn in response to applicant’s amendments.
On page 12 of applicant’s response, applicant argues that DTL 104 in Henry only outputs microinstructions, not hints, etc.
This is not persuasive. The DTP is not required to output hints, etc. From amended claim 1, the one or more outputs may be one or more of a branch hint, an immediate, and a micro-op pointer. Thus, only one of these options needs to be outputted. As explained in the rejection, one of the outputs is a micro-op pointer 254.
On page 12 of applicant’s response, applicant argues that the Official Notice does not make sense as there is a fetch unit and branch predictor that never receive output from the DTL.
This is not persuasive. The examiner does not understand how this argument pertains to the claim language.
On page 12 of applicant’s response, applicant states that they do not understand why one input would by static, while the other is dynamic.
Input 124 is dynamic because it is constantly changing at runtime. The input corresponds to the currently fetched instruction. Thus, input 124 will change each time a new instruction is fetched. Input 132 is deemed static because it is a mode indicator that indicates whether x86 or ARM instructions are currently being processed by the front end of the processor (fetch, decode, translate) (see paragraph [0035]). As such, for as long as the instructions are of the same type, this input is static, i.e., non-changing. If the mode is switched, it will then again be static for as long as the instruction are of the same other type.
On page 12 of applicant’s response, applicant argues that it does not make sense to call the entirety of FIG.1 a JEU, because applicant questions how a JEU sends anything to DTL within the JEU.
The examiner disagrees. If FIG.1 is called a JEU, then the register file 122 and DTL 104 are within the JEU. Thus, if the registers 122 are sending data for the DTL, then it is the JEU sending data (internally) from registers 122 for DTL 104. The examiner also notes that mapping FIG.1 to the JEU is just an example. The JEU could be any subset of components since they can all be tied to jump execution in some way. Names of components are not distinguishing features.
On pages 12-13 of applicant’s response, applicant argues that pipeline 112 appears to align with units 424, which does not feed back to 104, nor does file 106 feed back to 104.
This argument is not persuasive and the examiner is not clear on how this is relevant to the rejection. The claim sends data from a register file to DTL circuitry. As pointed out, register file 122 (not necessarily 106 or 112 or 424) sends data to DTL 104.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183