DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiners Interpretation
Based on the current Application history of the case, the specifications, and the language of the current claims as presented, the attorney and/or applicant has made it clear that they do not consider metal vias and/or metal vertically extending contacts within the grouping of metal interconnects. Although the Examiner still strongly disagrees with this interpretation as presented. For the purpose of compact prosecution, the examiner will use the applicant’s interpretation as the applicant has made it sufficiently clear on the record when interpreting the claims of this application that the grouping of “metal interconnects” exclude “metal vias” and/or “metal vertically extending contacts” under broadest reasonable interpretation [see MPEP 2111].
Response to Arguments
Applicant’s arguments, see Remarks page 8-10, filed 10/13/2025, with respect to Rejections under 35 USC 103 have been fully considered and are persuasive, the amendments sufficiently change the scope of what is claimed to overcome the rejections as written. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of US 10177311 B1 Hsieh et al here after “Hsieh Chao-Ching”
Applicant’s argument in part regarding claims 20, 31 and 11 page -19 regarding Hsieh that metal interconnect layers 128 and 129 can not be interpreted as a metal-1 layer is not persuasive. 128 and 129 are layers comprising metal interconnects and are capable of being labeled the first layer and/or “1” layer, meeting the requirements of MPEP 2111 broadest reasonable interpretation and layers 128 and 129 comprise the same composition and structure (a metal layer) as claimed thus meets the reequipments of MPEP 2112.01. As stated in prior office actions the specification does not sufficiently define the metal-1 in a manner that would explicitly exclude the layers of Hsieh from being considered a metal-1 layer.
The applicant also in part argues that Hsieh teaches away as Hsieh explicitly states “In general, memory cells 103 may be located between any adjacent pair of metal interconnect layers”. The examiner disagrees Disclosed examples and preferred embodiments do not constitute a teaching away from a broader disclosure or nonpreferred embodiments [See MPEP 2123 II]. In addition, this reflects what is illustrated in a preferred embodiment of what is claimed in the instant application [see annotation below] as the memory cell (202) of this instant application is located between adjacent metal layers M0 and M1 wherein paragraph 0046 of the instant application sufficiently discloses the Mx layers (including the metal-0 layer and/or M0) are considered metal interconnect layers and M1 is the first metal interconnect layer in “a first metal interconnect layer (often referred to as Metal-1); in such an example, the silicided active region defines the lower metal layer Mx where x=0 (i.e., Mo) and the first metal interconnect layer (Metal-1) defines the upper metal layer Mx+i (i.e., Mi).”
The applicant also argues in part “It would not have been obvious to somehow form Hsieh’s memory cell 103 between the substrate 202 and the metal interconnect layer 108 shown in fig. 1”, this argument is moot the examiner does not match layer 108 to the metal-1 layer, the examiner matches 139 and/or 138 to the metal-1 and figure 1 exactly illustrates the memory cell between the metal-1 layer and the substrates [see annotation below] in addition per MPEP 2144.04 II. Omission of an element and its function is Obvious if the function of the element is not desired, such as horizontally interconnecting the device to additional elements.
The applicant also argues in part Hsieh does not teach or hint at how a memory cell 103 could be connected to any transistor 206 below the metal-1 layer 108. The examiner respectfully disagrees, once again the argument is moot the examiner does not match and/or considers108 to be the metal-1 layer the examiner matches and/or considers 139/138 to be the metal-1 layer and fig. 1 clearly illustrates the electrode 115 of the memory cell element is electrically connected to the source drain region 214 of the transistor 206. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “the memory cell element directly contacts the transistor”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Note: the examiner has additionally brought in Hsieh Chao-Ching as shown below that explicitly illustrate that such structure is known without metal interconnects [as interpreted in view of the applicants pervious arguments].
PNG
media_image1.png
545
816
media_image1.png
Greyscale
Annotated Fig. 4 of the instant application
PNG
media_image2.png
392
412
media_image2.png
Greyscale
Hsieh Annotated fig. 1: highlighting the metal-1 layer, the memory cell and the substrate
PNG
media_image3.png
308
451
media_image3.png
Greyscale
Hsieh Chao-Ching Annotated fig. 1: highlighting the metal-1 layer, the via layer, and the substrate
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11, 13, 17-19, 23 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over US 11088203 B2 Hsieh et al herein after “Hsieh”, and further in view of US 20110303888 A1 Fukumizu et al herein after “Fukumizu” and WO 2015147801 A1 “Prashant” et al, hereinafter “Prashant”, and US 10177311 B1 Hsieh et al here after “Hsieh Chao-Ching”.
Regarding claim 11 Hsieh teaches an integrated circuit structure, comprising:
a substrate (202 fig. 1);
a via layer [see annotation below] formed over the substrate [sufficiently illustrated fig. 1] and comprising a dielectric region (comprising 135, and 125 fig. 1 and 2) including a tub opening (the opening around elements 103 fig. 1 and 2) and a via opening spaced apart from the tub opening (the opening around via 133 fig. 2);
a resistive memory cell element (103 fig. 1) formed in the tub opening in the via layer and including:
a cup-shaped bottom electrode (115 fig. 1);
a cup-shaped resistive memory layer (113 fig. 1); and
a top electrode (109 fig. 1);
a via (133 fig. 2) formed in the via opening in the dielectric region; and
a metal-1 metal interconnect layer (137/138 fig. 1 and 2) of horizontally-extending metal lines (139 fig. 1 and 2) formed over the via layer and including (a) a top electrode contact (102 fig. 1 and 2) in electrical contact with the top electrode and (b) an interconnect element (metal portion of 139 physically contacting 133 fig. 2) in contact with the via and spaced apart from the top electrode contact;
wherein the cup-shaped bottom electrode and the via comprise respective elements of a same conformal metal layer (metal layer within via layer 135 comprising 133 and 115 fig. 2; an embodiment is sufficiently disclosed in which 115 [column 5 lines 4-5, “copper”, or “gold”, or “tungsten”] and 133 [column 53-55, “copper”, or “gold, or “tungsten”] are the same material, thus this limitation is met as the element is materially and structurally the same as disclosed (see MPEP 2112.01));
Hsieh does not teach a carbon nanotube memory cell and; a carbon nanotube layer.
Fukumizu teaches a carbon nanotube memory cell (80a fig. 1B) and; a carbon nanotube layer (23 fig. 1B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a carbon nanotube layer that Fukumizu teaches as the resistive memory layer in the resistive memory cell that Hsieh teaches thus forming a carbon nanotube memory cell to achieve the known result of a faster switching operation [Fukumizu paragraph 0019] with a reasonable expectation of success.
Hsieh does not teach an upper surface of the via is co-planar with the upper surface of the cup-shaped bottom electrode, the upper surface of the cup-shaped carbon nanotube layer, and the upper surface of the top electrode, nor the via layer but no metal interconnect layer is formed between the substrate and the metal-1 metal interconnect layer.
Hsieh in view of Fukumizu does teach an upper (most) surface of the cup-shaped bottom electrode, an upper surface (most) of the cup-shaped carbon nanotube layer, an upper surface (most) of the top electrode and an upper (most ) surface of top electrode are co-planar.
Prashant teaches an upper (most) surface of the cup-shaped bottom electrode (322 Fig. 3J), an upper (most) surface of the via (M2 Fig. 3J, note M2 interconnect structure meets the limitation of a via as it is material and structurally the same as claimed, see MPEP 2112).
It would have been obvious to one of ordinary skill in the art to change the size and/or shape of the device that Hsieh in view of Fukumizu teaches such that “an upper surface of the cup-shaped bottom electrode, an upper surface of the cup-shaped carbon nanotuhe layer, an upper surface of the top electrode, and an upper surface of the via are co-planar” as Prashant teaches to reduce the size and/or vertical profile of the device and/or changes in size and/or shape are prima facie obviousness (see MPEP 2144.04 IV).
Hsieh, Chao-Ching teaches a 1 transistor, 1 capacitor resistive memory device (1 fig. 1, met under MPEP 2112.01) comprising a via layer (comprising 313 and/or 310 fig. 1) but no metal interconnect layer is formed between a substrate (100 fig. 1) and a metal-1 metal interconnect layer (comprising 512 and/or 520 fig. 1) [in the same sense as argued by the applicant].
It would have been obvious for one of ordinary skill in the art to modify the device Hsieh teaches in view of the device Hsieh, Chao-Ching teaches such that “the via layer but no metal interconnect layer is formed between the substrate and the metal-1 metal interconnect layer” to reduce the number of steps need for manufacturing, and/or to reduces the amount of materials need for manufacturing, and/or to reduce the size and/or vertical profile of the device (see MPEP 2144.04 IV) and/or when the interconnect layers are deemed not necessary for the intended application (i.e. when the device does not need to be electrically connected between the transistor and the capacitor to additional elements in the lateral directions, see MPEP 2144.04 II A).
PNG
media_image4.png
392
412
media_image4.png
Greyscale
Hsieh Annotated fig. 1: High lighting the via layer
PNG
media_image5.png
221
576
media_image5.png
Greyscale
Hsieh Annotated fig. 2: High lighting the via layer
Regarding claim 13 as shown above Hsieh in view of Fukumizu, Prashant and Hsieh Chao-Ching teaches the integrated circuit structure of Claim 11, wherein:
the dielectric region (Hsieh 135 fig. 1) is formed over a transistor (206 fig. 1) including a source region (214 or 216 fig. 1) in the substrate and a drain region (214 or 216 fig. 1) in the substrate;
the cup-shaped bottom electrode of the carbon nanotube memory cell element is conductively coupled to the source region or the drain region of the transistor [Hsieh column 3 lines 4-6 “Bottom electrodes 115 may be coupled to source/drain regions 214 through vias 203”].
Hsieh does not explicitly teach a doped source region, a doped drain region, and a silicide region formed on the source region or on the drain region.
The examiner takes Official Notice that doped source/drain regions and silicides as being well-known and commonly employed structures in semiconductor devices before the effective filing date of the claimed invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a doped source region, a doped drain region and a silicide region formed on the source region drain region such that the silicide is conductively coupled to the carbon nanotube memory cell element in the transistor that Hsieh teaches to facilitate the creation of a channel, improved contact resistance, and improve series resistance.
Regarding claim 16 as shown above Hsieh in view of Fukumizu, Prashant, and Hsieh Chao-Ching teaches the integrated circuit structure of Claim 11, wherein:
the dielectric region (Hsieh comprising 135 fig. 1) is formed over a lower metal interconnect layer (Hsieh 127 fig. 1); and
the upper metal layer (Hsieh 137/138 fig. 1) comprises an upper metal interconnect layer (Hsieh 139 fig. 1).
Regarding claim 17 as shown above Hsieh in view of Fukumizu, Prashant, and Hsieh Chao-Ching teaches the integrated circuit structure of Claim 11.
Hsieh in view of Fukumizu does not explicitly teach wherein the cup- shaped carbon nanotube layer has a thickness in the range of 200A-500A.
Hsieh in view of Fukumizu teaches wherein the cup- shaped carbon nanotube layer (Hsieh 113 fig. 1 in view of Fukumizu) has a thickness in the range of 100A-500A (Fukumizu paragraph 0019).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to pick the thickness of the carbon nanotube within the range of 100A-500A that Fukumizu teaches such that it is within the range of 200A-500A to achieve “faster switching” [Fukumizu paragraph 0019] and/or because “in the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists” (MPEP 2144.05-I).
Regarding claim 18 as shown above Hsieh in view of Fukumizu, Prashant and Hsieh Chao-Ching teaches the integrated circuit structure of Claim 11, wherein:
the cup-shaped bottom electrode comprises tungsten [Hsieh column 5 lines 3-5 an embodiment of 115 comprising of tungsten is sufficiently disclosed]; and
the top electrode comprises titanium, tungsten, or a combination of titanium and tungsten. [Hsieh column 5 lines 43-47].
Regarding claim 19 as shown above Hsieh in view of Fukumizu, Prashant and Hsieh Chao-Ching teaches the integrated circuit structure of Claim 11, wherein a lateral width (Hsieh 105 fig. 2) of the tub opening is larger than a vertical height (Hsieh 107 fig. 2) of the tub opening. (Hsieh teaches the width being larger than the height with sufficient specificity in column 4 line 54-56 “the height is at least one quarter the width” the examiner is relying on the embodiment in which the height is one quarter the width).
Claim(s) 20-22, 30 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh, and further in view of Fukumizu, and US 10177311 B1 Hsieh et al here after “Hsieh Chao-Ching”.
Regarding claim 20 Hsieh teaches an integrated circuit structure, comprising:
a resistive memory cell (101 fig. 1): including
a transistor (Hsieh 206 fig. 1) including a gate (Hsieh 210 fig. 1), a source region (Hsieh 214 or 216 fig. 1) and a drain region (Hsieh 214 or 216 fig. 1) formed in a semiconductor substrate (202 fig. 1); and
a via layer (135 fig. 1) of vertically extending vias [sufficiently illustrated fig. 1 and 2] formed over the semiconductor substrate [illustrated in fig. 1, the via layer is over the substrate in a direction from the bottom to the top of the figure];
a metal-1 metal interconnect layer (138 fig. 1) formed over the via layer; and
a memory cell element (Hsieh 103 fig. 1) formed in the via layer between the semiconductor substrate and the metal-1 interconnect layer, wherein the memory cell element is electrically coupled to the transistor [Hsieh column 3 lines 4-6 “Bottom electrodes 115 may be coupled to source/drain regions 214 through vias 203” the bottom electrodes are part of the memory cell] and including:
a cup-shaped bottom electrode (Hsieh 115 fig. 1) conductively coupled to the source region or to the drain region of the transistor [Hsieh column 3 lines 4-6 “Bottom electrodes 115 may be coupled to source/drain regions 214 through vias 203” the bottom electrodes are part of the memory cell].
Hsieh does not teach a cup-shaped carbon nanotube layer formed in an interior opening defined by the cup-shaped bottom electrode; and a top electrode formed in an interior opening defined by the cup-shaped carbon nanotube layer;
Hsieh does teach a cup-shaped resistive memory layer (Hsieh 113 fig. 1) formed in an interior opening defined by the cup-shaped bottom electrode; and a top electrode (Hsieh 109 fig. 1) formed in an interior opening defined by the resistive memory layer
Fukumizu teaches a carbon nanotube memory cell (Fukumizu 80a fig. 1B) and; a carbon nanotube layer (Fukumizu 23 fig. 1B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a carbon nanotube layer that Fukumizu teaches as the resistive memory layer in the resistive memory cell that Hsieh teaches thus forming a carbon nanotube memory cell to achieve the known result of a faster switching operation [Fukumizu paragraph 0019] with a reasonable expectation of success.
Hsieh does not teach, inter alia, a doped source region and a doped drain region.
The examiner takes Official Notice that doped source and drain regions are well-known and commonly employed structures in semiconductor devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a doped source region, “a doped source comprise respective elements of and a doped drain region formed in the semiconductor substrate” that Hsieh teaches to facilitate the creation of a channel, and improve series resistance.
Hsieh does not teach the via layer but no metal interconnect layer is formed between the substrate and the metal-1 metal interconnect layer.
Hsieh Chao-Ching teaches a 1 transistor, 1 capacitor resistive memory device (1 fig. 1, met under MPEP 2112.01) comprising a via layer (comprising 313 and/or 310 fig. 1) but no metal interconnect layer is formed between a substrate (100 fig. 1) and a metal-1 metal interconnect layer (comprising 512 and/or 520 fig. 1) [in the same sense as argued by the applicant].
It would have been obvious for one of ordinary skill in the art to modify the device Hsieh teaches in view of the device Hsieh, Chao-Ching teaches such that “the via layer but no metal interconnect layer is formed between the substrate and the metal-1 metal interconnect layer” to reduce the number of steps need for manufacturing, and/or to reduces the amount of materials need for manufacturing, and/or to reduce the size and/or vertical profile of the device (see MPEP 2144.04 IV) and/or when the interconnect layers are deemed not necessary for the intended application (i.e. when the device does not need to be electrically connected between the transistor and the capacitor to additional elements in the lateral directions, see MPEP 2144.04 II A).
Regarding claim 21 as shown above Hsieh in view of Fukumizu and Hsieh Chao-Ching teaches the integrated circuit structure of Claim 20, wherein the cup- shaped bottom electrode is electrically coupled to the doped source region or on the doped drain region of the transistor. [Hsieh column 3 lines 4-6 “Bottom electrodes 115 may be coupled to source/drain regions 214 through vias 203”].
Hsieh does not explicitly teach a silicide region formed on the doped source region or on the doped drain region.
The examiner takes Offical notice that silicides are well-known and commonly employed structures in semiconductor devices before the effective filing date of the claimed invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a silicide region formed on the doped source region or on the doped drain region that Hsieh teaches such that it is electrically coupled to the bottom electrode to improve contact resistance.
Regarding claim 22 as shown above Hsieh in view of Fukumizu and Hsieh Chao-Ching teaches the integrated circuit structure of Claim 20, comprising at least one interconnect via or contact via formed in the via layer [Hsieh fig. 2 the memory cell is formed in a common layer with via 133].
Regarding Claim 23 as shown above Hsieh in view of Fukumizu and Hsieh Chao-Ching the integrated circuit structure of Claim 11, wherein:
the via comprises a first portion (133 fig. 2) of the conformal metal layer; and
wherein the cup-shaped bottom electrode comprises a second portion (115 fig. 2) of the conformal metal layer [see claim 1 for how features 133 and 115 meet the limitation of forming a conformal metal layer].
Regarding claim 30 shown above Hsieh in view of Fukumizu teaches The integrated circuit structure of Claim 20, wherein the integrated circuit structure comprises a one transistor, one capacitor (1T1C) memory cell (this limitation is met as Hsieh 206 [one transistor] and 103 [one capacitor or CNT] in fig. 1 and 2 in view of Fukumizu as shown above is material and structurally identical to what is claimed and/or disclosed [see MPEP 2112.01], further paragraph 0046 of the instant applicant states “the CNT memory cell element and transistor may collectively define a CNT memory cell, e.g., a 1T1C CNT memory cell, where the CNT memory cell is considered a capacitor”, thus a CNT memory cell element 103 and transistor 206 constitute a 1T1C CNT memory cell), wherein the carbon nanotube memory cell element comprises a capacitor structure (this limitation is met as Hsieh 103 fig. 1 and 2 in view of Fukumizu as shown above is material and structurally identical to what is claimed and/or disclosed [see MPEP 2112.01], further paragraph 0046 of the instant applicant states “the CNT memory cell element and transistor may collectively define a CNT memory cell, e.g., a 1T1C CNT memory cell, where the CNT memory cell is considered a capacitor”, thus the CNT memory cell 103 constitutes a capacitor).
Claims 25-27, 29, and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in view of Fukumizu and Prashant, and in further view of US 20190348466 A1 Pillarisetty et al herein after “Pillarisetty”.
Regarding claim 25 as shown above Hsieh in view of Fukumizu and Prashant teaches the integrated circuit structure of Claim 11, wherein:
the dielectric region is formed over a transistor (Hsieh 206 fig. 1) including a source region (Hsieh 214 or 216 fig. 1), a drain region (Hsieh 214 or 216 fig. 1), and a gate (Hsieh 210 fig. 1);
the cup-shaped bottom electrode (Hsieh 115 fig. 1) of the carbon nanotube memory cell element (Hsieh 203 fig. 1 in view Fukumizu) is conductively coupled to the source region (Hsieh 114/116 fig. 1) or to the drain region (Hsieh 114/116 fig. 1) of the transistor (Hsieh 206 fig. 1);
Hsieh in view of Fukumizu does not explicitly teach a doped source region, a doped drain region, and the via conductively coupled to the gate of the transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a doped source region, a doped drain region for the source and drain regions of the transistor that Hsieh teaches to facilitate the creation of a channel, and improve series resistance.
Pillarisetty teaches a via (120 fig. 1) conductively coupled to the gate (110 fig. 1) of the transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a via conductively coupled to the gate that Pillarisetty teaches to the transistor that Hsieh teaches to enable a source follower configuration, to enable means for electrically controlling the gate of a transistor.
Regrading claim 26 as shown above Hsieh in view of Fukumizu, Prashant and Pillarisetty teaches the integrated circuit structure of Claim 25.
Hsieh in view of Fukumizu, Prashant and Pillarisetty does not explicitly the cup-shaped bottom electrode of the carbon nanotube memory cell element is conductively coupled to a first silicide region formed on the doped source region or on the doped drain region of the transistor and the via is conductively coupled to a second silicide region formed on the gate of the transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the cup-shaped bottom electrode of the carbon nanotube memory cell element is conductively coupled to a first silicide region formed on the source region or on the drain region of the transistor that Hsieh teaches and to have the via conductively coupled to a second silicide region formed on the gate of the transistor that Hsieh teaches to enable improved contact resistance and improved efficiency.
Regarding claim 27 as shown above Hsieh in view of teaches Fukumiku teaches the integrated circuit structure of Claim 20, comprising:
the via layer including a tub opening (103 fig. 1 and 2) and a via opening (includes 133 fig. 2) laterally spaced apart from the tub opening;
wherein the cup-shaped bottom electrode (115 fig. 1 and 2) of the carbon nanotube memory cell element is formed in the tub opening;
a via formed (133 fig. 2) in the via opening,
wherein the cup-shaped bottom electrode of the carbon nanotube memory cell element and the via are formed from a same conformal metal layer (metal layer within via layer 135 comprising 133 and 115 fig. 2; “formed from a same conformal metal layer” is a product-by-process limitation and/or claim, product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (See MPEP 2113), the structure implied by this limitation is that the claimed elements share the same material, an embodiment is sufficiently disclosed in which 115 [column 5 lines 4-5, “copper”, or “gold”, or “tungsten”] and 133 [column 53-55, “copper”, or “gold, or “tungsten”] are the same material).
Hsieh does not teach the via is conductively coupled to the gate of the transistor;
Pillarisetty teaches a via (120 fig. 1) conductively coupled to the gate (110 fig. 1) of the transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a via conductively coupled to the gate that Pillarisetty teaches to the transistor that Hsieh teaches to enable a source follower configuration, to enable means for electrically controlling the gate of a transistor.
Regarding claim 29 Hsieh in view of Fukumizu, Prashant and Pillarisetty teach the integrated circuit structure of Claim 11.
Hsieh in view of Fukumizu and Pillarisetty does not explicitly teach and the via is conductively coupled to a second silicide region formed on the gate of the transistor.
Pillarisetty teaches a via (120 fig. 1) conductively coupled to the gate (110 fig. 1) of the transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a via conductively coupled to the gate that Pillarisetty teach identical to the Via Hsieh teaches to the transistor that Hsieh teaches to enable a source follower configuration, to enable means for electrically controlling the gate of a transistor.
The examiner takes Official Notice that silicides are well-known and commonly employed structures in semiconductor devices before the effective filing date of the claimed invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the bottom electrode of the carbon nanotube memory cell element is conductively coupled to a first silicide region formed on the source region or on the drain region of the transistor and the via is conductively coupled to a second silicide region formed on the gate of the transistor for the transistor that Hsieh in view of Fukumizu and Pillarisetty teaches to enable improved contact resistance and improved efficiency.
Regarding claim 31 Hsieh teaches one transistor, one capacitor (1T1C) memory cell, comprising:
a transistor (206 fig. 1) including a gate (210 fig. 1), a source region (214 or 216 fig 1) formed in a semiconductor substrate (202 fig. 1) and a drain region (216 or 214 fig. 1); formed in the semiconductor substrate
a capacitor structure (103 fig. 1; the disclosed structure meets the material and structural requirements of being a capacitor, top electrode 109, bottom electrode 115 with a resistive switching layer 113 in between) formed over the transistor [illustrated in fig. 1], wherein the capacitor structure is formed on the transistor [illustrated in fig. 1, Hsieh column 3 lines 4-6 “Bottom electrodes 115 may be coupled to source/drain regions 214 through vias 203”] and includes: a cup-shaped bottom electrode (115 fig. 1) conductively coupled to the source region or to the drain region of the transistor [illustrated in fig. 1, Hsieh column 3 lines 4-6 “Bottom electrodes 115 may be coupled to source/drain regions 214 through vias 203”].
Hsieh further teaches a cup-shaped resistance switching layer (113 fig. 1) formed in an interior opening defined by the cup-shaped bottom electrode;
a top electrode (109 fig. 1) formed in an interior opening defined by the cup-shaped resistance switching layer; and
a vertically-extending contact (133 fig. 2) being spaced apart from the capacitor structure wherein the vertically-extending contact and the cup-shaped bottom electrode of the capacitor structure are formed in a common dielectric region (“interlevel dielectric layer” 135 fig. 2) below a metal-1 metal interconnect layer (138 and/or 139 fig. 1 and fig. 2) of horizontally-extending metal lines [sufficiently illustrated fig. 1 and 2 as extending in and out of fig. 1 and 2, and under broadest reasonable interpretation Paragraph 15 discloses as part of a BEOL (back-end-of-line)].
Hsieh does not teach the resistance switching layer being a carbon nanotube layer.
Hsieh does not explicitly teach a vertically-extending contact formed on the gate of the transistor.
Hsieh does not teach no metal interconnect layer is formed below the metal-1 metal interconnect layer.
Fukumizu teaches a carbon nanotube memory cell (80a fig. 1B) and; a carbon nanotube layer (23 fig. 1B).
Pillarisetty teaches a vertically extending contact (120 fig. 1) formed on the gate (110 fig. 1) of the transistor.
Hsieh, Chao-Ching teaches a 1 transistor, 1 capacitor resistive memory device (1 fig. 1, met under MPEP 2112.01) comprising a via layer (comprising 313 and/or 310 fig. 1) but no metal interconnect layer is formed between a substrate (100 fig. 1) and a metal-1 metal interconnect layer (comprising 512 and/or 520 fig. 1) [in the same sense as argued by the applicant].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a carbon nanotube material such as Fukumizu teaches for the resistance switching layer that Hsieh teaches for the known resistive properties of carbon nanotube and/or to achieve the known result of a faster switching operation [Fukumizu paragraph 0019] with a reasonable expectation of success.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the vertically extending contact Hsieh teach such that it is conductively coupled to the gate as Pillarisetty teaches such that there is “a vertically-extending contact formed on the gate of the transistor, the vertically-extending contact being spaced apart from the capacitor structure” to the transistor that Hsieh teaches to enable a source follower configuration, to enable means for electrically controlling the gate of a transistor.
It would have been obvious for one of ordinary skill in the art to modify the device Hsieh teaches by removing the metal interconnect layers formed between the substrate and the metal-1 interconnect layer such that “no other metal interconnect layer is formed between the substrate and the metal-1 metal interconnect laver” to reduce the number of steps need for manufacturing, and/or to reduces the amount of materials need for manufacturing, and/or to reduce the size and/or vertical profile of the device (see MPEP 2144.04 IV) and/or when the interconnect layers are deemed not necessary for the intended application (i.e. when the device does not need to be electrically connected between the transistor and the capacitor to additional elements in the lateral directions, see MPEP 2144.04 II A).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WCT/ Examiner, Art Unit 2821
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893