DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 04/09/2026 have been fully considered but they are not persuasive. Applicant argues that the examiner’s “interpretation mischaracterizes Applicant’s arguments”, “applicant has never presented any argument about the meaning of metal interconnect” and “explicitly arguing the meaning of the metal interconnect layer and via layer”.
This argument is not persuasive regarding the allowability and interpretation of the claims as there is no patentable distinction between the terms “metal interconnect layer” and “metal interconnect” nor “via layer” and “via” as claimed. The term “layer” in “metal interconnect layer” and “via layer” clarifies the structure that is already necessitated by the terms “metal interconnect” and “via” in the context of a device claim.
“Layer” in general includes the broad meaning “a level of material, such as a type of rock or gas, that is different from the material above or below it, or a thin sheet of a substance” [Cambridge dictionary]. In the context of a device claim “a metal interconnect” and “via” must necessarily be “a level of material” and/or have the structural properties of “material” and “level” [height/thickness/position] within the device.
“Layer” to one of ordinary skill in the field of semiconductor technology includes the field specific meaning “Stratum of a printed board or semiconductor” [IPC-T-50M-2015]. IPC-T-50M-2025 does not further define “Stratum” and the general meaning of Stratum includes “one of the parts or layers into which something is separated” [Cambridge dictionary]. In the context of a semiconductor device a “via” and/or “metal interconnect” must necessarily be ~one of the parts a semiconductor is separated into~ and/or ~a part of the semiconductor~.
In view of the above the term layer is synonymous with the terms “part”, “element”, “portion” and/or “component”. The examiner believes he fully understands the perspective at which the applicant is coming from, However the examiner must interpret the claims under the broadest reasonable interpretation in view of the specification without importing limitations from the specification. If the applicant would like to narrow the meaning of the terms to a specific meaning or definition the examiner recommends amending the claim limitation as supported by the specification to explicitly include such meaning.
The applicant argues pages 9-10 The applicant argues that “the silicide active region M0 cannot itself be a metal interconnect layer” and “the present rejections are based on unfounded interpretations”. The examiner respectfully disagrees “silicide active region M0” is not mutually exclusive with “a metal interconnect layer” as the silicide active region comprises metal as disclosed and at least interconnects 202 fig. 4 to 406 fig. 4 and/or 414 by 426 and/or 416 fig. 4) as illustrated in fig. 4 when 420 (gate) is in the on-state, the term “silicide active region” does not prevent the feature from additionally functioning as a metal silicide region when the silicide active region compresses metal; the examiner notes that channel/active regions necessarily at least interconnect source/drain region when in an “on” state.
The applicant in part argues that the M in M0 and M1 is not discloses as standing for Metal interconnect layer but Metal layer and that the M0 is a silicide active region and the M1 layer is a metal interconnect layer. This is persuasive, “Metal layer” is broader than “metal interconnect layer” however after additional consideration the rejection as written still applies under the broader interpretation, as written in non-final action filed 01/15/2026, “a metal interconnect layer” constitutes “a metal layer” although “a metal layer” is not necessarily “a metal interconnect layer”.
The applicant argues pages 10-11 That the applicant has never presented “the memory cell element directly contacts the transistor”. The examiner agrees the use of double inverted commas was not intended to be direct quotation of the applicant nor was it prefaced with the applicant as the speaker. The intent of the use of double quotations was to highlight the feature as though it was spoken. After further consideration single inverted commas would have been more appropriate. ‘the memory cell element directly contacts the transistor’ is the structural feature the examiner believes provides the functions of ‘connection’ and/or ‘conductive couple’. Hsieh Chao-Ching provides sufficient motivation to configure such a connection regardless of if Hsieh Chao-Ching expressly states how. The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). If the applicant is arguing something different than what has been interpreted the examiner would ask the applicant to clarify the argument.
Pages 11-12 the applicant argues Hsieh does not teach a 1 transistor, 1 capacitor resistive memory device but a 1 transistor, 1 resistor RRAM cell, that Hsieh Chao-Ching does not mention a capacitor. The examiner agrees that Hsieh Chao-Ching does not expressly mention a capacitor. The capacitor structure is sufficiently illustrated within the figures under MPEP 2112 which a distinct from MPEP 2111. MPEP 2112 is not a question of interpretation as MPEP 2111 but of composition and structure, “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established”. The structure of a capacitor comprises a top conductive layer, a middle resistive layer [dielectric layer] and a bottom conductive layer, note this is not limited by orientation. This is illustrated fig. 8 of Hsieh Chao-Ching. With top electrode (330 fig. 8), resistive layer (320), and bottom conductive layer (310a fig. 8), this structure the same if not identical to a capacitor thus capable of performing the function of capacitor regardless of if it is referred to as a capacitor. Thus, under MPEP 2112.01 it is presumed to function as a capacitor and/or to be a capacitor. After additional search and consideration, the terms “Capacitor” and “Resistor” refer to the function and/or use of the same structure under MPEP 2112.01. A capacitor/resistor structure comprising two electrodes and a dielectric material therebetween behaves as a capacitor when an applied voltage across the capacitor/resistor structure is lower than the break down voltage of the dielectric material, and the same capacitor/resistor structure behaves as a resistor when an applied voltage across the capacitor/resistor structure is higher than the breakdown voltage of the dielectric material. As evidence see US 20220285269 A1 Chang discloses one circuit in fig. 1A-B and 7A-C under different operating conditions comprising a same structure behaving as both a capacitor 112 and resistor 116 based on operating conditions. This is sufficiently disclosed paragraph 0021 “As programmed, the fuse element 112 provided in the dielectric antifuse structure 100 (FIG. 1A) has been subjected to a voltage level (VDDQ.sub.P) sufficient to induce a breakdown in the portion of the capacitor dielectric 107 arranged between the overlapping portions of the first plate defined by the first portion of the source/drain conductor structure 108 (MD) and the second plate defined by a first portion of a gate conductor structure 106 (MG), thereby creating a resistive direct electrical connection 116 between the two plates of the original capacitor of fuse element 112”.
In addition both the prior art and the instant application discuss the invention and/or are classified as ‘resistive memory cells’ in view of this the motivation to combine the teaching of Hsieh Chao-Ching still applies as previously shown, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Applicant repeats the argument as presented in prior remarks on Pages 12-13 that the examiners interpretation is inconsistent with specification. The examiner disagrees and maintains the arguments as present in prior office actions. The applicant in parts argues that the examiner interpretation “metal-1 metal interconnect layer” is improper and provides the specific definition “Metal-1 (M1) is the first, lowest, and thinnest conductive layer in the Back-End-of-Line (BEOL) interconnect stack, sitting directly above the transistor contacts”. The examiner respectfully disagrees with the application.
For the sake of compact prosecution in prior non-final office action filed 01/15/2026 the examiner made the interpretation in view of the applicants arguments that the M1 metal interconnect layer does not include Via layers such that the rejection as written aligns meets ~the via layer but no metal interconnect layer is formed between the substrate and the metal-1 metal interconnect layer~ and Modified the prior art in further view of Hsieh Chao-Ching to reduce the number of steps need for manufacturing, and/or to reduces the amount of materials need for manufacturing, and/or to reduce the size and/or vertical profile of the device (see MPEP 2144.04 IV) and/or when the interconnect layers are deemed not necessary for the intended application (i.e. when the device does not need to be electrically connected between the transistor and the capacitor to additional elements in the lateral directions, see MPEP 2144.04 II A), using the traversed meaning “Metal-1 (M1) is the first, lowest, and thinnest conductive layer in the Back-End-of-Line (BEOL) interconnect stack, sitting directly above the transistor contacts” as provide by the application, the limitations as stated still reads in view of the modification made. As such the applicant’s argument regarding interpretation of this feature being is moot. The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). The examiner further notes that it is unclear if a meaning generated using google AI sufficiently meets the requirements of broadest reasonable interpretation to one of ordinary skill in the art in lieu of a more reputable source of one whom works and/or is within the semiconductor field.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11, 13, 17-19, 23, 30, and 34 are rejected under 35 U.S.C. 103 as being unpatentable over US 11088203 B2 Hsieh et al herein after “Hsieh”, and further in view of US 20110303888 A1 Fukumizu et al herein after “Fukumizu” and WO 2015147801 A1 “Prashant” et al, hereinafter “Prashant”, and US 10177311 B1 Hsieh et al here after “Hsieh Chao-Ching”.
Regarding claim 11 Hsieh teaches an integrated circuit structure, comprising:
a substrate (202 fig. 1);
a via layer [see annotation below] formed over the substrate [sufficiently illustrated fig. 1] and comprising a dielectric region (comprising 135, and 125 fig. 1 and 2) including a tub opening (the opening around elements 103 fig. 1 and 2) and a via opening spaced apart from the tub opening (the opening around via 133 fig. 2);
a resistive memory cell element (103 fig. 1) formed in the tub opening in the via layer and including:
a cup-shaped bottom electrode (115 fig. 1);
a cup-shaped resistive memory layer (113 fig. 1); and
a top electrode (109 fig. 1);
a via (133 fig. 2) formed in the via opening in the dielectric region; and
a metal-1 metal interconnect layer (137/138 fig. 1 and 2) of horizontally-extending metal lines (139 fig. 1 and 2) formed over the via layer and including (a) a top electrode contact (102 fig. 1 and 2) in electrical contact with the top electrode and (b) an interconnect element (metal portion of 139 physically contacting 133 fig. 2) in contact with the via and spaced apart from the top electrode contact;
wherein the cup-shaped bottom electrode and the via comprise respective elements of a same conformal metal layer (metal layer within via layer 135 comprising 133 and 115 fig. 2; an embodiment is sufficiently disclosed in which 115 [column 5 lines 4-5, “copper”, or “gold”, or “tungsten”] and 133 [column 53-55, “copper”, or “gold, or “tungsten”] are the same material, thus this limitation is met as the element is materially and structurally the same as disclosed (see MPEP 2112.01));
Hsieh does not teach a carbon nanotube memory cell and; a carbon nanotube layer.
Fukumizu teaches a carbon nanotube memory cell (80a fig. 1B) and; a carbon nanotube layer (23 fig. 1B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a carbon nanotube layer that Fukumizu teaches as the resistive memory layer in the resistive memory cell that Hsieh teaches thus forming a carbon nanotube memory cell to achieve the known result of a faster switching operation [Fukumizu paragraph 0019] with a reasonable expectation of success.
Hsieh does not teach an upper surface of the via is co-planar with the upper surface of the cup-shaped bottom electrode, the upper surface of the cup-shaped carbon nanotube layer, and the upper surface of the top electrode, nor the via layer but no metal interconnect layer is formed between the substrate and the metal-1 metal interconnect layer.
Hsieh in view of Fukumizu does teach an upper (most) surface of the cup-shaped bottom electrode, an upper surface (most) of the cup-shaped carbon nanotube layer, an upper surface (most) of the top electrode and an upper (most ) surface of top electrode are co-planar.
Prashant teaches an upper (most) surface of the cup-shaped bottom electrode (322 Fig. 3J), an upper (most) surface of the via (M2 Fig. 3J, note M2 interconnect structure meets the limitation of a via as it is material and structurally the same as claimed, see MPEP 2112).
It would have been obvious to one of ordinary skill in the art to change the size and/or shape of the device that Hsieh in view of Fukumizu teaches such that “an upper surface of the cup-shaped bottom electrode, an upper surface of the cup-shaped carbon nanotuhe layer, an upper surface of the top electrode, and an upper surface of the via are co-planar” as Prashant teaches to reduce the size and/or vertical profile of the device and/or changes in size and/or shape are prima facie obviousness (see MPEP 2144.04 IV).
Hsieh, Chao-Ching teaches a 1 transistor, 1 capacitor resistive memory device (1 fig. 1, met under MPEP 2112.01) comprising a via layer (comprising 313 and/or 310 fig. 1) but no metal interconnect layer is formed between a substrate (100 fig. 1) and a metal-1 metal interconnect layer (comprising 512 and/or 520 fig. 1) [in the same sense as argued by the applicant].
It would have been obvious for one of ordinary skill in the art to modify the device Hsieh teaches in view of the device Hsieh, Chao-Ching teaches such that “the via layer but no metal interconnect layer is formed between the substrate and the metal-1 metal interconnect layer” to reduce the number of steps need for manufacturing, and/or to reduces the amount of materials need for manufacturing, and/or to reduce the size and/or vertical profile of the device (see MPEP 2144.04 IV) and/or when the interconnect layers are deemed not necessary for the intended application (i.e. when the device does not need to be electrically connected between the transistor and the capacitor to additional elements in the lateral directions, see MPEP 2144.04 II A).
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Hsieh Annotated fig. 1: High lighting the via layer
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Hsieh Annotated fig. 2: High lighting the via layer
Regarding claim 13 as shown above Hsieh in view of Fukumizu, Prashant and Hsieh Chao-Ching teaches the integrated circuit structure of Claim 11, wherein:
the dielectric region (Hsieh 135 fig. 1) is formed over a transistor (206 fig. 1) including a source region (214 or 216 fig. 1) in the substrate and a drain region (214 or 216 fig. 1) in the substrate;
the cup-shaped bottom electrode of the carbon nanotube memory cell element is conductively coupled to the source region or the drain region of the transistor [Hsieh column 3 lines 4-6 “Bottom electrodes 115 may be coupled to source/drain regions 214 through vias 203”].
Hsieh does not explicitly teach a doped source region, a doped drain region, and a silicide region formed on the source region or on the drain region.
The examiner takes Official Notice that doped source/drain regions and silicides as being well-known and commonly employed structures in semiconductor devices before the effective filing date of the claimed invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a doped source region, a doped drain region and a silicide region formed on the source region drain region such that the silicide is conductively coupled to the carbon nanotube memory cell element in the transistor that Hsieh teaches to facilitate the creation of a channel, improved contact resistance, and improve series resistance.
Regarding claim 16 as shown above Hsieh in view of Fukumizu, Prashant, and Hsieh Chao-Ching teaches the integrated circuit structure of Claim 11, wherein:
the dielectric region (Hsieh comprising 135 fig. 1) is formed over a lower metal interconnect layer (Hsieh 127 fig. 1); and
the upper metal layer (Hsieh 137/138 fig. 1) comprises an upper metal interconnect layer (Hsieh 139 fig. 1).
Regarding claim 17 as shown above Hsieh in view of Fukumizu, Prashant, and Hsieh Chao-Ching teaches the integrated circuit structure of Claim 11.
Hsieh in view of Fukumizu does not explicitly teach wherein the cup- shaped carbon nanotube layer has a thickness in the range of 200A-500A.
Hsieh in view of Fukumizu teaches wherein the cup- shaped carbon nanotube layer (Hsieh 113 fig. 1 in view of Fukumizu) has a thickness in the range of 100A-500A (Fukumizu paragraph 0019).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to pick the thickness of the carbon nanotube within the range of 100A-500A that Fukumizu teaches such that it is within the range of 200A-500A to achieve “faster switching” [Fukumizu paragraph 0019] and/or because “in the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists” (MPEP 2144.05-I).
Regarding claim 18 as shown above Hsieh in view of Fukumizu, Prashant and Hsieh Chao-Ching teaches the integrated circuit structure of Claim 11, wherein:
the cup-shaped bottom electrode comprises tungsten [Hsieh column 5 lines 3-5 an embodiment of 115 comprising of tungsten is sufficiently disclosed]; and
the top electrode comprises titanium, tungsten, or a combination of titanium and tungsten. [Hsieh column 5 lines 43-47].
Regarding claim 19 as shown above Hsieh in view of Fukumizu, Prashant and Hsieh Chao-Ching teaches the integrated circuit structure of Claim 11, wherein a lateral width (Hsieh 105 fig. 2) of the tub opening is larger than a vertical height (Hsieh 107 fig. 2) of the tub opening. (Hsieh teaches the width being larger than the height with sufficient specificity in column 4 line 54-56 “the height is at least one quarter the width” the examiner is relying on the embodiment in which the height is one quarter the width).
Claim(s) 20-22, 30 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh, and further in view of Fukumizu, and US 10177311 B1 Hsieh et al here after “Hsieh Chao-Ching”.
Regarding claim 20 Hsieh teaches an integrated circuit structure, comprising:
a resistive memory cell (101 fig. 1): including
a transistor (Hsieh 206 fig. 1) including a gate (Hsieh 210 fig. 1), a source region (Hsieh 214 or 216 fig. 1) and a drain region (Hsieh 214 or 216 fig. 1) formed in a semiconductor substrate (202 fig. 1); and
a via layer (135 fig. 1) of vertically extending vias [sufficiently illustrated fig. 1 and 2] formed over the semiconductor substrate [illustrated in fig. 1, the via layer is over the substrate in a direction from the bottom to the top of the figure];
a metal-1 metal interconnect layer (138 fig. 1) formed over the via layer; and
a memory cell element (Hsieh 103 fig. 1) formed in the via layer between the semiconductor substrate and the metal-1 interconnect layer, wherein the memory cell element is electrically coupled to the transistor [Hsieh column 3 lines 4-6 “Bottom electrodes 115 may be coupled to source/drain regions 214 through vias 203” the bottom electrodes are part of the memory cell] and including:
a cup-shaped bottom electrode (Hsieh 115 fig. 1) conductively coupled to the source region or to the drain region of the transistor [Hsieh column 3 lines 4-6 “Bottom electrodes 115 may be coupled to source/drain regions 214 through vias 203” the bottom electrodes are part of the memory cell].
Hsieh does not teach a cup-shaped carbon nanotube layer formed in an interior opening defined by the cup-shaped bottom electrode; and a top electrode formed in an interior opening defined by the cup-shaped carbon nanotube layer;
Hsieh does teach a cup-shaped resistive memory layer (Hsieh 113 fig. 1) formed in an interior opening defined by the cup-shaped bottom electrode; and a top electrode (Hsieh 109 fig. 1) formed in an interior opening defined by the resistive memory layer
Fukumizu teaches a carbon nanotube memory cell (Fukumizu 80a fig. 1B) and; a carbon nanotube layer (Fukumizu 23 fig. 1B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a carbon nanotube layer that Fukumizu teaches as the resistive memory layer in the resistive memory cell that Hsieh teaches thus forming a carbon nanotube memory cell to achieve the known result of a faster switching operation [Fukumizu paragraph 0019] with a reasonable expectation of success.
Hsieh does not teach, inter alia, a doped source region and a doped drain region.
The examiner takes Official Notice that doped source and drain regions are well-known and commonly employed structures in semiconductor devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a doped source region, “a doped source comprise respective elements of and a doped drain region formed in the semiconductor substrate” that Hsieh teaches to facilitate the creation of a channel, and improve series resistance.
Hsieh does not teach the via layer but no metal interconnect layer is formed between the substrate and the metal-1 metal interconnect layer.
Hsieh Chao-Ching teaches a 1 transistor, 1 capacitor resistive memory device (1 fig. 1, met under MPEP 2112.01) comprising a via layer (comprising 313 and/or 310 fig. 1) but no metal interconnect layer is formed between a substrate (100 fig. 1) and a metal-1 metal interconnect layer (comprising 512 and/or 520 fig. 1) [in the same sense as argued by the applicant].
It would have been obvious for one of ordinary skill in the art to modify the device Hsieh teaches in view of the device Hsieh, Chao-Ching teaches such that “the via layer but no metal interconnect layer is formed between the substrate and the metal-1 metal interconnect layer” to reduce the number of steps need for manufacturing, and/or to reduces the amount of materials need for manufacturing, and/or to reduce the size and/or vertical profile of the device (see MPEP 2144.04 IV) and/or when the interconnect layers are deemed not necessary for the intended application (i.e. when the device does not need to be electrically connected between the transistor and the capacitor to additional elements in the lateral directions, see MPEP 2144.04 II A).
Regarding claim 21 as shown above Hsieh in view of Fukumizu and Hsieh Chao-Ching teaches the integrated circuit structure of Claim 20, wherein the cup- shaped bottom electrode is electrically coupled to the doped source region or on the doped drain region of the transistor. [Hsieh column 3 lines 4-6 “Bottom electrodes 115 may be coupled to source/drain regions 214 through vias 203”].
Hsieh does not explicitly teach a silicide region formed on the doped source region or on the doped drain region.
The examiner takes Offical notice that silicides are well-known and commonly employed structures in semiconductor devices before the effective filing date of the claimed invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a silicide region formed on the doped source region or on the doped drain region that Hsieh teaches such that it is electrically coupled to the bottom electrode to improve contact resistance.
Regarding claim 22 as shown above Hsieh in view of Fukumizu and Hsieh Chao-Ching teaches the integrated circuit structure of Claim 20, comprising at least one interconnect via or contact via formed in the via layer [Hsieh fig. 2 the memory cell is formed in a common layer with via 133].
Regarding Claim 23 as shown above Hsieh in view of Fukumizu and Hsieh Chao-Ching the integrated circuit structure of Claim 11, wherein:
the via comprises a first portion (133 fig. 2) of the conformal metal layer; and
wherein the cup-shaped bottom electrode comprises a second portion (115 fig. 2) of the conformal metal layer [see claim 1 for how features 133 and 115 meet the limitation of forming a conformal metal layer].
Regarding claim 30 shown above Hsieh in view of Fukumizu, and Hsieh-Chao teaches The integrated circuit structure of Claim 20, wherein the integrated circuit structure comprises a one transistor, one capacitor (1T1C) memory cell (this limitation is met as Hsieh 206 [one transistor] and 103 [one capacitor or CNT] in fig. 1 and 2 in view of Fukumizu as shown above is material and structurally identical to what is claimed and/or disclosed [see MPEP 2112.01], further paragraph 0046 of the instant applicant states “the CNT memory cell element and transistor may collectively define a CNT memory cell, e.g., a 1T1C CNT memory cell, where the CNT memory cell is considered a capacitor”, thus a CNT memory cell element 103 and transistor 206 constitute a 1T1C CNT memory cell), wherein the carbon nanotube memory cell element comprises a capacitor structure (this limitation is met as Hsieh 103 fig. 1 and 2 in view of Fukumizu as shown above is material and structurally identical to what is claimed and/or disclosed [see MPEP 2112.01], further paragraph 0046 of the instant applicant states “the CNT memory cell element and transistor may collectively define a CNT memory cell, e.g., a 1T1C CNT memory cell, where the CNT memory cell is considered a capacitor”, thus the CNT memory cell 103 constitutes a capacitor).
Claim 34 Hsieh in view of Fukumizu, Prashant and Hsieh Chao-Ching teach the integrated circuit structure of Claim 11, wherein the integrated circuit structure comprises a one transistor, one capacitor (1T1C) memory cell, wherein the carbon nanotube memory cell element comprises a capacitor structure [sufficiently illustrated by base reference memory cell element 103 is a capacitor under MPEP 2112.01 as the structure is identical to a capacitor, two electrodes and a dielectric layer there-between].
Claims 25-27, 29, 31, and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in view of Fukumizu, Hsieh-Chao and Prashant, and in further view of US 20190348466 A1 Pillarisetty et al herein after “Pillarisetty”.
Regarding claim 25 as shown above Hsieh in view of Fukumizu, Hsieh-Chao and Prashant teaches the integrated circuit structure of Claim 11, wherein:
the dielectric region is formed over a transistor (Hsieh 206 fig. 1) including a source region (Hsieh 214 or 216 fig. 1), a drain region (Hsieh 214 or 216 fig. 1), and a gate (Hsieh 210 fig. 1);
the cup-shaped bottom electrode (Hsieh 115 fig. 1) of the carbon nanotube memory cell element (Hsieh 203 fig. 1 in view Fukumizu) is conductively coupled to the source region (Hsieh 114/116 fig. 1) or to the drain region (Hsieh 114/116 fig. 1) of the transistor (Hsieh 206 fig. 1);
Hsieh in view of Fukumizu does not explicitly teach a doped source region, a doped drain region, and the via conductively coupled to the gate of the transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a doped source region, a doped drain region for the source and drain regions of the transistor that Hsieh teaches to facilitate the creation of a channel, and improve series resistance.
Pillarisetty teaches a via (120 fig. 1) conductively coupled to the gate (110 fig. 1) of the transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a via conductively coupled to the gate that Pillarisetty teaches to the transistor that Hsieh teaches to enable a source follower configuration, to enable means for electrically controlling the gate of a transistor.
Regrading claim 26 as shown above Hsieh in view of Fukumizu, Prashant, Hsieh-Chao and Pillarisetty teaches the integrated circuit structure of Claim 25.
Hsieh in view of Fukumizu, Prashant and Pillarisetty does not explicitly the cup-shaped bottom electrode of the carbon nanotube memory cell element is conductively coupled to a first silicide region formed on the doped source region or on the doped drain region of the transistor and the via is conductively coupled to a second silicide region formed on the gate of the transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the cup-shaped bottom electrode of the carbon nanotube memory cell element is conductively coupled to a first silicide region formed on the source region or on the drain region of the transistor that Hsieh teaches and to have the via conductively coupled to a second silicide region formed on the gate of the transistor that Hsieh teaches to enable improved contact resistance and improved efficiency.
Regarding claim 27 as shown above Hsieh in view of Fukumiku, Hsieh-Chao teaches the integrated circuit structure of Claim 20, comprising:
the via layer including a tub opening (103 fig. 1 and 2) and a via opening (includes 133 fig. 2) laterally spaced apart from the tub opening;
wherein the cup-shaped bottom electrode (115 fig. 1 and 2) of the carbon nanotube memory cell element is formed in the tub opening;
a via formed (133 fig. 2) in the via opening,
wherein the cup-shaped bottom electrode of the carbon nanotube memory cell element and the via are formed from a same conformal metal layer (metal layer within via layer 135 comprising 133 and 115 fig. 2; “formed from a same conformal metal layer” is a product-by-process limitation and/or claim, product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (See MPEP 2113), the structure implied by this limitation is that the claimed elements share the same material, an embodiment is sufficiently disclosed in which 115 [column 5 lines 4-5, “copper”, or “gold”, or “tungsten”] and 133 [column 53-55, “copper”, or “gold, or “tungsten”] are the same material).
Hsieh does not teach the via is conductively coupled to the gate of the transistor;
Pillarisetty teaches a via (120 fig. 1) conductively coupled to the gate (110 fig. 1) of the transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a via conductively coupled to the gate that Pillarisetty teaches to the transistor that Hsieh teaches to enable a source follower configuration, to enable means for electrically controlling the gate of a transistor.
Regarding claim 29 Hsieh in view of Fukumizu, Prashant and Pillarisetty teach the integrated circuit structure of Claim 11.
Hsieh in view of Fukumizu and Pillarisetty does not explicitly teach and the via is conductively coupled to a second silicide region formed on the gate of the transistor.
Pillarisetty teaches a via (120 fig. 1) conductively coupled to the gate (110 fig. 1) of the transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a via conductively coupled to the gate that Pillarisetty teach identical to the Via Hsieh teaches to the transistor that Hsieh teaches to enable a source follower configuration, to enable means for electrically controlling the gate of a transistor.
The examiner takes Official Notice that silicides are well-known and commonly employed structures in semiconductor devices before the effective filing date of the claimed invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the bottom electrode of the carbon nanotube memory cell element is conductively coupled to a first silicide region formed on the source region or on the drain region of the transistor and the via is conductively coupled to a second silicide region formed on the gate of the transistor for the transistor that Hsieh in view of Fukumizu and Pillarisetty teaches to enable improved contact resistance and improved efficiency.
Regarding claim 31 Hsieh teaches one transistor, one capacitor (1T1C) memory cell, comprising:
a transistor (206 fig. 1) including a gate (210 fig. 1), a source region (214 or 216 fig 1) formed in a semiconductor substrate (202 fig. 1) and a drain region (216 or 214 fig. 1); formed in the semiconductor substrate
a capacitor structure (103 fig. 1; the disclosed structure meets the material and structural requirements of being a capacitor, top electrode 109, bottom electrode 115 with a resistive switching layer 113 in between) formed over the transistor [illustrated in fig. 1], wherein the capacitor structure is formed on the transistor [illustrated in fig. 1, Hsieh column 3 lines 4-6 “Bottom electrodes 115 may be coupled to source/drain regions 214 through vias 203”] and includes: a cup-shaped bottom electrode (115 fig. 1) conductively coupled to the source region or to the drain region of the transistor [illustrated in fig. 1, Hsieh column 3 lines 4-6 “Bottom electrodes 115 may be coupled to source/drain regions 214 through vias 203”].
Hsieh further teaches a cup-shaped resistance switching layer (113 fig. 1) formed in an interior opening defined by the cup-shaped bottom electrode;
a top electrode (109 fig. 1) formed in an interior opening defined by the cup-shaped resistance switching layer; and
a vertically-extending contact (133 fig. 2) being spaced apart from the capacitor structure wherein the vertically-extending contact and the cup-shaped bottom electrode of the capacitor structure are formed in a common dielectric region (“interlevel dielectric layer” 135 fig. 2) below a metal-1 metal interconnect layer (138 and/or 139 fig. 1 and fig. 2) of horizontally-extending metal lines [sufficiently illustrated fig. 1 and 2 as extending in and out of fig. 1 and 2, and under broadest reasonable interpretation Paragraph 15 discloses as part of a BEOL (back-end-of-line)].
Hsieh does not teach the resistance switching layer being a carbon nanotube layer.
Hsieh does not explicitly teach a vertically-extending contact formed on the gate of the transistor.
Hsieh does not teach no metal interconnect layer is formed below the metal-1 metal interconnect layer.
Fukumizu teaches a carbon nanotube memory cell (80a fig. 1B) and; a carbon nanotube layer (23 fig. 1B).
Pillarisetty teaches a vertically extending contact (120 fig. 1) formed on the gate (110 fig. 1) of the transistor.
Hsieh, Chao-Ching teaches a 1 transistor, 1 capacitor resistive memory device (1 fig. 1, met under MPEP 2112.01) comprising a via layer (comprising 313 and/or 310 fig. 1) but no metal interconnect layer is formed between a substrate (100 fig. 1) and a metal-1 metal interconnect layer (comprising 512 and/or 520 fig. 1) [in the same sense as argued by the applicant].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a carbon nanotube material such as Fukumizu teaches for the resistance switching layer that Hsieh teaches for the known resistive properties of carbon nanotube and/or to achieve the known result of a faster switching operation [Fukumizu paragraph 0019] with a reasonable expectation of success.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the vertically extending contact Hsieh teach such that it is conductively coupled to the gate as Pillarisetty teaches such that there is “a vertically-extending contact formed on the gate of the transistor, the vertically-extending contact being spaced apart from the capacitor structure” to the transistor that Hsieh teaches to enable a source follower configuration, to enable means for electrically controlling the gate of a transistor.
It would have been obvious for one of ordinary skill in the art to modify the device Hsieh teaches by removing the metal interconnect layers formed between the substrate and the metal-1 interconnect layer such that “no other metal interconnect layer is formed between the substrate and the metal-1 metal interconnect laver” to reduce the number of steps need for manufacturing, and/or to reduces the amount of materials need for manufacturing, and/or to reduce the size and/or vertical profile of the device (see MPEP 2144.04 IV) and/or when the interconnect layers are deemed not necessary for the intended application (i.e. when the device does not need to be electrically connected between the transistor and the capacitor to additional elements in the lateral directions, see MPEP 2144.04 II A).
Claim 37 as shown above Hsieh in view of Fukumizu, Prashant, Pillarisetty and Hsieh Chao-Ching teach the integrated circuit structure of Claim 31, wherein the vertically- extending contact and the cup-shaped bottom electrode of the capacitor structure are formed from the same conformal metal layer (metal layer within via layer 135 comprising 133 and 115 fig. 2; an embodiment is sufficiently disclosed in which 115 [column 5 lines 4-5, “copper”, or “gold”, or “tungsten”] and 133 [column 53-55, “copper”, or “gold, or “tungsten”] are the same material, thus this limitation is met as the element is materially and structurally the same as disclosed (see MPEP 2112.01)).
Claim 33 and 35 is rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in view of Fukumizu, Prashant and Hsieh Chao-Ching as applied to the claims above, and further in view of US 20110291170 A1 Chumakov et al hereafter “Chumakov”.
Claim 33 as shown above Hsieh in view of Fukumizu, Prashant and Hsieh Chao-Ching teach the integrated circuit structure of Claim 11, wherein: the dielectric region is formed over a transistor including a doped source region in the substrate and a doped drain region in the substrate;
Hsieh in view of Fukumizu, Prashant and Hsieh Chao-Ching does not explicitly teach the cup-shaped bottom electrode of the carbon nanotube memory cell element is formed directly on a silicide region formed on the source region or on the drain region of the transistor.
Chumakov teaches a RAM device wherein “the transistors 150 may comprise drain and source regions 151, 152 in which appropriate contact regions 153, for instance in the form of metal silicide, may be provided. In the embodiment shown, the contact region 153 provided in the drain or source region 151 may represent a "shared" transistor region for the transistors 150A, 150B, and may also act as a capacitor electrode” [disclosed Paragraph 0033].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hsieh in view of Fukumizu, Prashant and Hsieh Chao-Ching in further view of Chumakov such that “the cup-shaped bottom electrode of the carbon nanotube memory cell element is formed directly on a silicide region formed on the source region or on the drain region of the transistor”.
A person of ordinary skill in the art would have been motivated to make this modification to achieve “a very space-efficient configuration” [Paragraph 0012 Chumakov].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is combining RAM structures.
Claim 35 as shown above Hsieh in view of Fukumizu, Prashant and Hsieh Chao-Ching the integrated circuit structure of Claim 13,
Hsieh in view of Fukumizu, Prashant and Hsieh Chao-Ching does not explicitly teach wherein the via is conductively coupled to a silicide region formed on the gate of the transistor.
The examiner takes Official Notice that silicides are well-known and commonly employed structures in semiconductor devices before the effective filing date of the claimed invention [as evidence silicides/salicides used as part of a gate electrode structure it taught in “the spacer structure 164 and metal silicide, which may be provided in the gate electrode structures 160 and in portions of the active region 102A exposed by the gate electrode structures 160” paragraph 0052 Chumakov].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention modify the device above such that “the via is conductively coupled to a silicide region formed on the gate of the transistor for the transistor that Hsieh in view of to enable improved contact resistance and improved efficiency and/or to achieve the desire work function across the junction.
Claim 36 is rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in view of Fukumizu, Pillarisetty and Prashant, and in further view of Chumakov.
Claim 36 as shown above Hsieh in view of Fukumizu, Prashant, Pillarisetty and Hsieh Chao-Ching The integrated circuit structure of Claim 31,
Hsieh in view of Fukumizu, Prashant, Pillarisetty and Hsieh Chao-Ching does not teach wherein the cup-shaped bottom electrode of the capacitor structure is formed directly on a silicide region formed on the source region or on the drain region of the transistor.
Chumakov teaches a RAM device wherein “the transistors 150 may comprise drain and source regions 151, 152 in which appropriate contact regions 153, for instance in the form of metal silicide, may be provided. In the embodiment shown, the contact region 153 provided in the drain or source region 151 may represent a "shared" transistor region for the transistors 150A, 150B, and may also act as a capacitor electrode” [disclosed Paragraph 0033].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hsieh in view of Fukumizu, Prashant and Hsieh Chao-Ching in further view of Chumakov such that “the cup-shaped bottom electrode of the carbon nanotube memory cell element is formed directly on a silicide region formed on the source region or on the drain region of the transistor”.
A person of ordinary skill in the art would have been motivated to make this modification to achieve “a very space-efficient configuration” [Paragraph 0012 Chumakov].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is combining RAM structures.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/WCT/ Examiner, Art Unit 2821
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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