DETAILED ACTION
This Office action responds to Applicant’s amendments filed on 06/25/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1, 3-8, 10-13, 15-17, and 21-25. Claims 2, 9, 14, and 18-20 are canceled by the Applicant.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-4, 6-8, 11-13, 17, and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Thakar (US 6803661) in view of Okoroanyanwu (US 6653231) in further view of Mehrad (US 9035399).
Regarding claim 1, Thakar shows (see, e.g., Thakar: figs.1-5b) most aspects of the instant invention including a method of fabricating an integrated circuit, comprising:
Depositing a polysilicon layer 102 on a dielectric layer 101 over a semiconductor substrate 100
Forming an anti-reflective coating (ARC) layer 103/104 on the polysilicon layer 102, the ARC layer 103/104 having a first thickness
Depositing a layer of photoresist pattern 205 on the ARC layer 103/104
Patterning the layer of photoresist material 205 to form a photoresist pattern 205 on the ARC layer 103/104
Removing the photoresist pattern 305
Etching the polysilicon layer 102 exposed by the ARC layer 403/404 to form the polysilicon gates 502
A portion of the ARC layer 503 remaining on the polysilicon gates as a result of etching the polysilicon layer
The portion of the ARC layer 503 having a second thickness less than the first thickness
Performing a wet etch process to remove the portion of the ARC layer 503 on the polysilicon gates (see, e.g., Thakar: col.5/II.35-38 – col.6/II.1-4)
Thakar, however, fails (see, e.g., Thakar: figs.1-5b) to specify the method step of trimming features of the photoresist pattern 205 to reduce the width of the features of the photoresist pattern 205 and to form trimmed features 305 having widths that correspond to critical dimensions of polysilicon gates 502. Okoroanyanwu, in a similar method to Thakar, shows (see, e.g., Okoroanyanwu: figs.3, 4A-4C, and 5) the method step of trimming features of the photoresist pattern 30 to reduce the width of the features of the photoresist pattern 50 and to form trimmed features 64 having widths 66 that correspond to critical dimensions (see, e.g., Okoroanyanwu: abstract, col.1/II.46-57) of polysilicon gates (see, e.g., Okoroanyanwu: col.2/II.7-20). Okoroanyanwu also teaches that the method step trimming features of the photoresist pattern 30 to reduce the width of the features of the photoresist pattern 50 and to form trimmed features 64 having widths 66 that correspond to critical dimensions of polysilicon gates is a method step for achieving a sub-lithographic critical dimension in an integrated circuit device feature (see, e.g., Okoroanyanwu: col.2/II.32-34).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to have a method step of Okoroanyanwu of trimming features of the photoresist pattern to reduce the width of the features of the photoresist pattern in the method of fabrication of Thakar to achieve a sub-lithographic critical dimension in an integrated circuit device feature.
Thakar in view of Okoroanyanwu shows (see, e.g., Thakar: figs.1-5b) the method step of:
Etching the ARC layer 103/104 exposed by the trimmed features of the photoresist pattern 205
Thakar in view of Okoroanyanwu, however, fails (see, e.g., Thakar: figs.1-5b) to specify, prior to the method step of forming sidewall spacers, the method step of performing a first ion implantation using the portion of the ARC on the polysilicon gates as first implant blocking structures to form first implant regions adjacent to sidewalls of the polysilicon gates. Mehrad, in a similar method to Thakar in view of Okoroanyanwu, shows (see, e.g., Mehrad: fig. 8), prior to a sidewall spacer formation 310, the method step of performing a first ion implantation 265 using the portion of the ARC 235C on the polysilicon gates 230C as first implant blocking structures to form first implant regions 285/290 adjacent to sidewalls of the polysilicon gates 230C. Mehrad teaches (see, e.g., fig. 8) that the ion implantation 265 is to perform channel engineering (see, e.g., col.8/II.58-6 – col.9/II.1-22]) through the implantation of dopants into source/drain regions 285/290 following the gate patterning.
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to have a method step of Mehrad of performing a self-aligned ion implantation in the method of fabrication of Thakar in view of Okoroanyanwu to perform channel engineering thorough the implantation of dopants into source/drain regions.
Thakar in view of Okoroanyanwu in view of Mehrad shows (see, e.g., Mehrad: fig. 9) the method steps of:
Forming sidewall spacers 340 on sidewalls of the polysilicon gates 230A
Performing a second ion implantation 295 using the portion of the ARC layer 235C on the polysilicon gates 230C and the sidewall spacers 310 on the sidewalls of the polysilicon gates 230C as second implant blocking structures to form second implant regions 30/305 adjacent to the sidewall spacers 310 on the polysilicon gates 230C
Regarding claim 3, Thakar in view of Okoroanyanwu in view of Mehrad shows (see, e.g., Thakar: figs.1-5b) the first thickness of the ARC layer 103/104 and the second thickness of the portion of the ARC layer 503. Thakar in view of Okoroanyanwu in view of Mehrad shows (see, e.g., Thakar: col.4/II. 3-24, and col.5/II.24-30) that the second thickness (only SixNy layer) is at least 50% of the first thickness (the SixOyNz layer and the SixNy layer).
Thakar in view of Okoroanyanwu in view of Mehrad also shows (see, e.g., Mehrad: fig. 4I) shows the portion of the ARC layer 324 that has a sidewall taper angle at least 80 degrees a relative to a top surface of the polysilicon layer 320.
Furthermore, it is noted that the specification fails to provide teachings about the criticality of having different thicknesses and angles, and differences in thicknesses and angles will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the first and second thicknesses of ARC layer, and of the sidewall taper angles of the ARC layer, and Thakar and Mehrad have identified such thicknesses and angles as result-effective variables subject to optimization, it would have been obvious to one of ordinary skill in the art to have these thicknesses and angles to be different in the method of Thakar in view of Okoroanyanwu in view of Mehrad.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed thickness and angle differences or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 4, Thakar in view of Okoroanyanwu in view of Mehrad shows (see, e.g., Thakar: fig. 1) that the etching of the polysilicon layer comprises a plasma etch configured for etching polysilicon (see, e.g., Thakar: col.5/II.31-34).
Regarding claim 6, Thakar in view of Okoroanyanwu in view of Mehrad shows (see, e.g., Thakar: fig. 1) that the first thickness of the ARC layer 103/104 is in a range from 800 to 2,500 A, and the ARC layer 103/104 comprises silicon nitride (see, e.g., Thakar: col.4/II.3-24).
Regarding claim 7, Thakar in view of Okoroanyanwu in view of Mehrad shows (see, e.g., Thakar: fig. 1) that the forming of the ARC layer 103/104 comprises forming a bottom ARC layer 103 and then forming a top ARC layer 104 on the bottom ARC layer 103 that is a different material compared to the bottom ARC layer 103 (see, e.g., Thakar: col.3/II.28-31).
Regarding claim 8, Thakar in view of Okoroanyanwu in view of Mehrad shows (see, e.g., Thakar: fig. 1) that the bottom ARC layer 103 comprises silicon rich silicon nitride, and the top ARC layer 104 comprises silicon nitride (see, e.g., Thakar: col.3/II.28-31 and col.3/II.43-44).
Regarding claim 11, Thakar shows (see, e.g., Thakar: figs.1-5b) most aspects of the instant invention including a method, comprising:
Depositing a polysilicon layer 102 on a dielectric layer 101 over a semiconductor layer 100
Forming an anti-reflective coating (ARC) layer 103/104 on the polysilicon layer 102
The ARC layer 103/104 having a first thickness
The ARC layer including a bottom ARC layer 103 and a top ARC layer 104 on the bottom ARC layer 103 that is a different material compared to the bottom ARC layer 103 (see, e.g., col.3/II.28-31)
Depositing a layer of photoresist material 105 on the top ARC layer 103/104
Patterning the layer of photoresist material 205 to form a photoresist pattern 205 on the ARC layer 103/104
Removing the photoresist pattern 305
Etching the polysilicon layer 102 exposed by the ARC layer 403/404 to form polysilicon gates 502
wherein:
A portion of the ARC layer 503 remaining on the polysilicon gates 502 as a result of etching the polysilicon layer 102
The portion of the ARC layer 503 having a second thickness less than the first thickness
Performing a wet etch process top remove the portion of the ARC layer 503 gates (see, e.g., Thakar: col.5/II.35-38 – col.6/II.1-4)
Thakar, however, fails (see, e.g., Thakar: figs.1-5b) to specify the method step of trimming features of the photoresist pattern 205 to reduce the width of the features of the photoresist pattern 205 and to form trimmed features 305 having widths that correspond to critical dimensions of polysilicon gates 502. Okoroanyanwu, in a similar method to Thakar, shows (see, e.g., Okoroanyanwu: figs.3, 4A-4C, and 5) the method step of trimming features of the photoresist pattern 30 to reduce the width of the features of the photoresist pattern 50 and to form trimmed features 64 having widths 66 that correspond to critical dimensions (see, e.g., Okoroanyanwu: abstract, col.1/II.46-57) of polysilicon gates (see, e.g., Okoroanyanwu: col.2/II.7-20). Okoroanyanwu also teaches that the method step trimming features of the photoresist pattern 30 to reduce the width of the features of the photoresist pattern 50 and to form trimmed features 64 having widths 66 that correspond to critical dimensions of polysilicon gates is a method step for achieving a sub-lithographic critical dimension in an integrated circuit device feature (see, e.g., Okoroanyanwu: col.2/II.32-34).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to have a method step of Okoroanyanwu of trimming features of the photoresist pattern to reduce the width of the features of the photoresist pattern in the method of fabrication of Thakar to achieve a sub-lithographic critical dimension in an integrated circuit device feature.
Thakar in view of Okoroanyanwu shows (see, e.g., Thakar: figs.1-5b) the method step of:
Etching the ARC layer 103/104 exposed by the trimmed features of the photoresist pattern 205
Thakar in view of Okoroanyanwu, however, fails (see, e.g., Thakar: figs.1-5b) to specify, prior to the method step of forming sidewall spacers, the method step of performing a first ion implantation using the portion of the ARC on the polysilicon gates as first implant blocking structures to form first implant regions adjacent to sidewalls of the polysilicon gates. Mehrad, in a similar method to Thakar in view of Okoroanyanwu, shows (see, e.g., Mehrad: fig. 8), prior to a sidewall spacer formation 310, the method step of performing a first ion implantation 265 using the portion of the ARC 235C on the polysilicon gates 230C as first implant blocking structures to form first implant regions 285/290 adjacent to sidewalls of the polysilicon gates 230C. Mehrad teaches (see, e.g., fig. 8) that the ion implantation 265 is to perform channel engineering (see, e.g., col.8/II.58-6 – col.9/II.1-22]) through the implantation of dopants into source/drain regions 285/290 following the gate patterning.
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to have a method step of Mehrad of performing a self-aligned ion implantation in the method of fabrication of Thakar in view of Okoroanyanwu to perform channel engineering thorough the implantation of dopants into source/drain regions.
Thakar in view of Okoroanyanwu in view of Mehrad shows (see, e.g., Mehrad: fig. 9) the method steps of:
Forming sidewall spacers 340 on sidewalls of the polysilicon gates 230A
Performing a second ion implantation 295 using the portion of the ARC layer 235C on the polysilicon gates 230C and the sidewall spacers 310 on the sidewalls of the polysilicon gates 230C as second implant blocking structures to form second implant regions 30/305 adjacent to the sidewall spacers 310 on the polysilicon gates 230C
Regarding claim 12, Thakar in view of Okoroanyanwu in view of Mehrad shows (see, e.g., Thakar: fig. 1) that the bottom ARC layer 103 comprises silicon rich silicon nitride, and the top ARC layer 104 comprises silicon nitride (see, e.g., Thakar: col.3/II.28-31 and col.3/II.43-44).
Regarding claim 13, Thakar in view of Okoroanyanwu in view of Mehrad shows (see, e.g., Thakar: fig. 1) that the first thickness of the ARC layer 103/104 is in a range from 800 to 2,500 A (see, e.g., Thakar: col.4/II.3-24).
Regarding claim 17, Thakar in view of Okoroanyanwu in view of Mehrad shows (see, e.g., Thakar: fig. 1) that the etching of the polysilicon layer comprises a plasma etch configured for etching polysilicon (see, e.g., Thakar: col.5/II.31-34).
Regarding claim 22, Thakar in view of Okoroanyanwu in view of Mehrad shows (see, e.g., Thakar: figs.1-5b) the first thickness of the ARC layer 103/104 and the second thickness of the portion of the ARC layer 503. Thakar in view of Okoroanyanwu in view of Mehrad shows (see, e.g., Thakar: col.4/II. 3-24, and col.5/II.24-30) that the second thickness (only SixNy layer) is at least 50% of the first thickness (the SixOyNz layer and the SixNy layer).
Furthermore, it is noted that the specification fails to provide teachings about the criticality of having different thicknesses, and differences in thicknesses will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph 19) of the first and second thicknesses of ARC layer, and Thakar has identified such angles as result-effective variables subject to optimization, it would have been obvious to one of ordinary skill in the art to have these thicknesses to be different in the method of Thakar in view of Okoroanyanwu in view of Mehrad.
Regarding claim 23, Thakar in view of Okoroanyanwu in view of Mehrad shows (see, e.g., Mehrad: fig. 10) the portion of the ARC layer 324 that has a sidewall taper angle at least 80 degrees a relative to a top surface of the polysilicon layer 320.
Furthermore, it is noted that the specification fails to provide teachings about the criticality of having different angles, and differences in angles will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph 23) of the sidewall taper angles of the ARC layer, and Mehrad has identified such angles as result-effective variables subject to optimization, it would have been obvious to one of ordinary skill in the art to have these angles to be different in the method of Thakar in view of Okoroanyanwu in view of Mehrad.
Claims 24-25, 10, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Thakar in view of Okoroanyanwu in view of Mehrad in further view of Toprac (US 5926690).
Regarding claims 24 and 25, Thakar in view of Okoroanyanwu in view of Mehrad shows (see, e.g., Thakar: figs.1-5b) a layer of photoresist pattern 205 on the ARC layer 103/104.
However, Thakar in view of Okoroanyanwu in view of Mehrad fails (see, e.g., Thakar: figs.1-5b) to show a method step of trimming the features of the photoresist pattern that includes trimming the features of the photoresist pattern for a duration corresponding an etch trim time as determined based on the gate critical dimension measurement feedback process.
Toprac, in a similar method to Thakar in view of Okoroanyanwu in view of Mehrad, shows (see, e.g., Toprac: figs. 1-3) a method step of trimming the photoresist that that includes trimming the features of the photoresist pattern for a duration corresponding an etch trim time as determined based on a gate critical dimension measurement feedback process (see, e.g., Toprac: abstract). Toprac further shows that the etch trim time is a manipulated variable for the run-to-run control technique applied to drive the critical dimensions in an integrated circuit to a defined specification (see, e.g., Toprac: abstract).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to have a method step of Toprac of trimming the photoresist that that includes trimming the features of the photoresist pattern for a duration corresponding an etch trim time as determined based on a gate critical dimension measurement feedback process in the method of fabrication of Thakar in view of Okoroanyanwu in view of Mehrad in order to manipulate the etch trim time in the run-to-run control technique applied to drive the critical dimensions in an integrated circuit to a defined specification.
Regarding claims 10 and 15, Thakar in view of Okoroanyanwu in view of Mehrad in view of Toprac shows (see, e.g., Toprac: figs. 1-3) a method step of a gate critical dimension measurement feedback process (see, e.g., abstract) that comprises:
Obtaining critical dimensions (CD) of the photoresist pattern (see, Toprac e.g., col.3/II.15-18) for a plurality of wafers in a wafer lot (see, e.g., Toprac: col.6/II.2-4) having a plurality of the IC dies (see, e.g., col.2/II.59-63)
Trimming the photoresist pattern of selected first ones of the plurality of test wafers (see, e.g., Toprac: col.3/II.49-62 and col.4/II/15-23) with trim times (see, e.g., Toprec: col.4/II.33-37) based on the CDs for each of the test wafers
Polysilicon etching the test wafers aster trimming the photoresist pattern (see, e.g., Toprac: col.4/II.38-42)
Measuring a gate CD of the test wafers after the polysilicon etching of the test wafers pattern (see, e.g., Toprac: col.4/II.38-42)
Using the gate CDs of the test wafers to calculate (see, e.g., Toprac: col.6/II.9-21) adjusted trim times for remaining others of the plurality of test wafers in the wafer lot (see, e.g., Toprac: col.5/II.18-21)
Selecting at least one wafer from the remaining others of the plurality of wafers for the polysilicon etching and then measuring a post etch CD (see, Toprac: e.g., col.10/II.8-14)
Using the post etch CD to select a trim time for a trimming of the photoresist pattern for the next lot of wafers (see, e.g., Toprac: col.10/II.8-14 and claim 1)
Claims 5, 21, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Thakar in view of in view of Okoroanyanwu in view of Mehrad view of Smayling (US 5767551).
Regarding claims 5, Thakar in view of Okoroanyanwu in view of Mehrad shows (see, e.g., Thakar: fig. 1) most aspects of the instant invention (see paragraph 6 above), including a silicon substrate 100 and a deposited polysilicon layer 102.
Thakar in view of Okoroanyanwu in view of Mehrad, however, fails to show an IC that includes at least one laterally diffused metal oxide semiconductor (LDMOS) device. Smayling, in a similar method of fabrication to Thakar in view of Okoroanyanwu in view of Mehrad, shows (see, e.g., Smayling: fig. 2k) an IC at includes at least one LDMOS device 146 (see, e.g., col.9/II.12-22). Smayling teaches that the implementation of such substrate facilitates the design of the a LDMOS device that is subjected to voltages and/or current densities much greater than the low-voltage logic transistors (see, e.g., Smayling: col.8/II.53-56).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to provide an IC with at least one LDMOS device of Smayling in the method of fabrication of Thakar in view of Okoroanyanwu in view of Mehrad that is subjected to voltages and/or current densities much greater than the low-voltage logic transistors.
Regarding claim 21, Thakar in view of Okoroanyanwu in view of Mehrad, however, fail to show a substrate that includes a semiconductor layer having a plurality of devices such as bipolar, complementary metal oxide semiconductor (CMOS), and double-diffused MOS (DMOS) transistors. Smayling, in a similar method of fabrication to Thakar in view of Okoroanyanwu in view of Mehrad, shows (see, e.g., fig. Smayling: 2k) an integrated circuit having a substrate with diffusion wells, with a plurality of devices including a bipolar device 147, a CMOS device 142, and a DMOS device 146. Smayling teaches that the implementation of such substrate with diffusion wells facilitates the design of the plurality of devices that are subjected to voltages and/or current densities much greater than the low-voltage logic transistors (see, e.g., Smayling: col.8/II.53-56).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to provide a substrate having well diffusions and with a plurality of devices of Smayling in the method of fabrication of Thakar in view of Okoroanyanwu in view of Mehrad to implement devices that are subjected to voltages and/or current densities much greater than the low-voltage logic transistors.
Regarding claims 16, Thakar in view of Okoroanyanwu in view of Mehrad shows (see, e.g., Thakar: fig. 1) most aspects of the instant invention (see paragraph 6 above), including a silicon substrate 100 and a deposited polysilicon layer 102.
Thakar in view of Okoroanyanwu in view of Mehrad, however, fails to show an IC that includes at least one laterally diffused metal oxide semiconductor (LDMOS) device. Smayling, in a similar method of fabrication to Thakar in view of Okoroanyanwu in view of Mehrad, shows (see, e.g., Smayling: fig. 2k) an IC at includes at least one LDMOS device 146 (see, e.g., col.9/II.12-22). Smayling teaches that the implementation of such substrate facilitates the design of the LDMOS device that is subjected to voltages and/or current densities much greater than the low-voltage logic transistors (see, e.g., Smayling: col.8/II.53-56).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to provide an IC with at least one LDMOS device of Smayling in the method of fabrication of Thakar in view of Okoroanyanwu in view of Mehrad that is subjected to voltages and/or current densities much greater than the low-voltage logic transistors.
Response to Arguments
Applicants’ arguments have been considered but are moot in view of the new grounds of rejection. Examiner has read and considered Applicants’ arguments, and finds them to be unpersuasive. Applicant’s arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitation. Examiner believes that the Thakar in view of Okoroanyanwu in view of Mehrad also discloses the amended limitation. The applicability of Thakar reference, Okoroanyanwu reference, and Mehrad reference to the amended limitation is indicated in the claim rejections above.
The applicants argue:
Thakar fails to anticipate or otherwise render obvious that "… prior to forming sidewall spacers on sidewalls of the polysilicon gates a sidewall spacer formation, performing a first ion implantation using the portion of the ARC layer on the polysilicon gates as first implant blocking structures to form first implant regions adjacent to sidewalls of the polysilicon gates …”, as recited in exemplary claims 1 and 11.
The examiner responds:
In view of the new grounds of rejection, Mehrad, in a similar method to Thakar in view of Okoroanyanwu, shows (see, e.g., Mehrad: fig. 8), prior to a sidewall spacer formation 310, the method step of performing a first ion implantation 265 using the portion of the ARC 235C on the polysilicon gates 230C as first implant blocking structures to form first implant regions 285/290 adjacent to sidewalls of the polysilicon gates 230C. Mehrad teaches (see, e.g., fig. 8) that the ion implantation 265 is to perform channel engineering (see, e.g., col.8/II.58-6 – col.9/II.1-22]) through the implantation of dopants into source/drain regions 285/290 following the gate patterning.
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to have a method step of Mehrad of performing a self-aligned ion implantation in the method of fabrication of Thakar in view of Okoroanyanwu to perform channel engineering thorough the implantation of dopants into source/drain regions.
Conclusion
This action is made final. The Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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