DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/01/2025 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar (U.S. Patent No 10,804,291) (of record) in view of Iwai (U.S. Patent No 10,290,650) (of record), Lue (U.S. PG Pub No US2012/0182808A1) (of record), and Thadjoisworo (U.S. PG Pub No US2014/0004708A1).
Regarding claim 1, Rajashekhar teaches a method for manufacturing a vertical semiconductor device [see title], the method comprising:
forming a gapfill target structure (comprising 79, 109) figs. 11A-11E [col 17, line 44-col 18, line 5] over a semiconductor substrate (9) fig. 11A [col 18, lines 54-57] the gapfill target structure including a horizontal recess (109) fig. 11B [col 17, line 44-col 18, line 5] parallel with the semiconductor substrate (9) and having a first surface (top of 9) and a vertical slit (79) fig. 11B [col 17, line 44-col 18, line 5] extending from the horizontal recess (109) and having a second surface (lateral surface of 116) fig. 11B [col 17, line 44-col 18, line 5] perpendicular to the semiconductor substrate (9);
removing a native oxide (103) figs. 11B-11C [col 6, lines 55-61, col 18, lines 5-39] from the first surface (top of 9) to form a pre-cleaned first surface (exposed top of 9);
forming, in-situ [col 19, lines 4-7], a first semiconductor material (114) fig. 11D [col 19, lines 8-32] over the pre-cleaned first surface (exposed top of 9); and
forming a second semiconductor material (272) fig. 15A [col 19, lines 43-60] on the first semiconductor material (114);
wherein the forming the gapfill target structure (comprising 79, 109) includes
forming a vertical channel layer (60) fig. 15C [col 20, lines 43-65] penetrating the stack structure (comprising 132, 142); and
etching the stack structure [see fig. 10A, 0098-0099] to form the vertical slit (79) fig. 11A [col 17, line 44-col 18, line 5].
However, Rajashekar does not explicitly disclose wherein forming the first semiconductor material (114) includes:
performing a deposition process to selectively form a sacrificial amorphous silicon layer on the second surface while simultaneously growing, selectively, a polysilicon layer as a source contact layer on the pre-cleaned first surface; and
selectively removing the sacrificial amorphous silicon layer,
wherein a contact surface between the vertical channel layer (60) and the polysilicon layer includes an oxide-free surface, and a contact surface between the polysilicon layer and the sacrificial amorphous silicon layer includes an oxidized surface, and
wherein removing the native oxide from the first surface is performed using a fluorine-based chemical including nitrogen trifluoride (NF3) (etchant chemical(s) unspecified [col 6, lines 55-61, col 18, lines 5-39]).
Iwai teaches a method [col 3, lines 48-57] wherein forming the first semiconductor material (10B) fig. 10C [col 22, lines 44-55] includes:
performing a deposition process to selectively form a sacrificial amorphous silicon layer (303) fig. 2 [col 7, lines 22-34] on the second surface (side-surface of 700) fig. 2 [col 5, lines 50-53] while simultaneously growing (shown in single step in fig. 2 [col 6, lines 49-60]), selectively, a polysilicon layer (10A) fig. 2 [col 7, lines 9-17] as a source contact layer [col 7, lines 9-17] on the pre-cleaned first surface (top of 9) fig. 2 [col 5, lines 1-9]; and
selectively removing [see fig. 10A, col 21, lines 59-64] the sacrificial amorphous silicon layer (303),
wherein a contact surface between the polysilicon layer (10A) and the sacrificial amorphous silicon layer (303) includes an oxidized surface (301) fig. 2 [col 7, lines 18-21] (thin silicon oxide layer may optionally adjoin the contact surfaces of 10A and 303).
With respect to whether Iwai discloses the simultaneous deposition of amorphous silicon layer (303) with polysilicon layer (10A) – Iwai is silent as to whether the deposition of the amorphous layer (303) and polysilicon (10A) occurs simultaneously or sequentially between fig. 1 and fig. 2. However, such a distinction reflects a mere change in the sequence of adding layers which does not produce any apparent difference in the finished product. Therefore, unless Applicant can prove unexcepted results in depositing the amorphous silicon and polysilicon layers at the same or different times, the claimed limitations are considered within the scope of the teaching of Iwai. (See MPEP 2144.04, IV, C).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Rajashekhar to include the formation of the amorphous silicon, polysilicon, and silicon oxide layers of Iwai in the concurrent manner [col 6, lines 49-60] shown by Iwai in order to effectively reduce memory cell size using a simplified/less-complex series of processes [col 30, lines 27-36], as taught by Iwai.
However, Rajashekhar in view of Iwai does not explicitly disclose wherein a contact surface between the vertical channel layer and the polysilicon layer (“source semiconductor layer 10A” of Iwai) includes an oxide-free surface,
wherein removing the native oxide from the first surface is performed using a fluorine-based chemical including nitrogen trifluoride (NF3) (etchant chemical(s) unspecified [col 6, lines 55-61, col 18, lines 5-39]).
Lue teaches a method of manufacturing a vertical semiconductor device [see title] wherein a contact surface (top of ‘source’ layer 4) fig. 2 [0020] between the vertical channel layer (20) fig. 3 [0020] and the polysilicon layer (4) fig. 2 [0020] (“source semiconductor layer 10A” is polysilicon in Iwai) includes an oxide-free surface (cleaning process for removing native oxide [0020] applied to surface of source layer [0020]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Rajashekhar in view of Iwai to apply the source structure cleaning process of Lue to the polysilicon source structure of Iwai in order to improve the quality of the channel layer(s) grown thereon [0020] as well as the material quality of the connection between the contact surfaces [0020], as taught by Lue.
However, Rajashekhar in view of Iwai and Lue does not explicitly disclose wherein removing the native oxide from the first surface is performed using a fluorine-based chemical including nitrogen trifluoride (NF3) (etchant chemical(s) unspecified [col 6, lines 55-61, col 18, lines 5-39]).
Thadjoisworo teaches a method [see title] wherein removing the native oxide from the first surface (“native oxide etch”) [0093] is performed using a fluorine-based chemical including nitrogen trifluoride (“to remove the native oxide, the H.sub.2/NF.sub.3 plasma uses a concentration of NF.sub.3 of 4.1% by volume” [0093]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Rajashekhar in view of Iwai and Lue such that the removal of the native oxide from the memory structure involves use of nitrogen trifluoride [0093] in order to ensure sufficient removal of the native oxide [0093], as taught by Thadjoisworo.
Regarding claim 2, Rajashekhar teaches the method [see title] as discussed above in claim 1. Rajashekhar also teaches wherein the first surface (top of 9) fig. 11B [col 18, lines 54-57] includes a surface of a silicon layer (9) fig. 11B [col 6, lines 34-45], and the second surface (lateral surface of 116) fig. 11B [col 7, lines 15-23] includes a surface of an insulation material (such as silicon nitride [col 7, lines 15-23]).
Regarding claim 11, Rajashekhar teaches the method [see title] as discussed above in claim 1. Rajashekhar also teaches wherein the first semiconductor material (silicon layer 114) fig. 15C [col 27, lines 42-49] and the second semiconductor material (silicon pillars collectively comprising 272, 60) fig. 15C [col 27, lines 42-49, col 18, lines 43-60] fill the horizontal recess (109) fig. 11B [col 17, line 44-col 18, line 5], and wherein the second semiconductor material (silicon material(s) 272, 60) extends to fill the vertical slit (79) fig. 11B [col 17, line 44-col 18, line 5].
Regarding claim 12, Rajashekhar teaches the method [see title] as discussed above in claim 1. Rajashekhar also teaches wherein the first semiconductor material (silicon layer 114) fig. 15C [col 27, lines 42-49] fills the horizontal recess (109) fig. 11B [col 17, line 44-col 18, line 5], and the second semiconductor material (silicon pillar(s) comprising 60) fig. 15C [col 27, lines 42-49, col 18, lines 43-60] fills the vertical slit (79) fig. 11B [col 17, line 44-col 18, line 5].
Regarding claim 13, Rajashekhar teaches the method [see title] as discussed above in claim 1. Rajashekhar also teaches wherein forming the gapfill target structure (comprising 79, 109) figs. 11A-11E [col 17, line 44-col 18, line 5] further includes:
forming a stack structure (comprising 132, 142) fig. 2 [col 8, lines 15-30] over the semiconductor substrate (9) fig. 2 [col 6, lines 34-45], the stack structure including a source sacrificial layer (104) fig. 2 [col 6, lines 4 – col 7, line 14], a source layer (116) fig. 2 [col 7, lines 15-22], and insulation layers (132) fig. 2 [col 8, lines 51-61] and sacrificial layers (142) fig. 2 [col 8, lines 51-61] alternately formed on the source layer (116);
forming a sealing layer (122) fig. 11E [col 19, lines 33-38] (silicon oxide) on a side wall of the vertical slit (79) to provide the second surface (effectively extended surface of dielectric 116) of the vertical slits (79);
selectively removing the source sacrificial layer (104) to form the horizontal recess (109) fig. 11B [col 17, line 44-col 18, line 5]; and
exposing a portion (lower sidewalls) of the vertical channel layer (60) from the horizontal recess to provide (effectively extend) the first surface (top of silicon material 9) of the horizontal recess (109).
Regarding claim 14, Rajashekhar teaches the method [see title] as discussed above in claim 13. Rajashekhar also teaches wherein the first surface of the horizontal recess (109) fig. 11B [col 17, line 44-col 18, line 5] further includes (hosts) an exposed surface of the source layer (116) fig. 11C [col 7, lines 15-22].
Claims 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar (U.S. Patent No 10,804,291) (of record) modified by Iwai (U.S. Patent No 10,290,650) (of record), Lue (U.S. PG Pub No US2012/0182808A1) (of record), and Thadjoisworo (U.S. PG Pub No US2014/0004708A1), as applied in claim 1 above, and further in view of Yoo (U.S. PG Pub No US2020/0090996A1) (of record).
Regarding claim 4, Rajashekhar teaches the method [see title] as discussed above in claim 1. However, Rajashekhar does not explicitly disclose wherein the deposition process [see fig. 8B, col 16, lines 16-37] (of amorphous/polysilicon [col 16, lines 16-37]) is performed using a mixture of a chlorine-containing silicon source material and a chlorine-free silicon source material.
Yoo teaches a method [0002] wherein the deposition process [see fig. 6, 0029-0030] (of polysilicon layer 140 [0030]) is performed using a mixture of a chlorine-containing silicon source material (second precursor = dichlorosilane [0028]) and a chlorine-free silicon source material (first precursor = monosilane [0028]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the deposition of the silicon material(s) in Rajashekhar’s method to be performed using a mixture of SiH4 and SiH2Cl2 [0028-0030] with the art-recognized proportion and pressure ranges [0030] specified by Yoo in order to successfully form the polycrystalline silicon material [0030] with a reduced roughness that decreases the presence of voids and seams [0030] in the deposited silicon [0028-0030], as taught by Yoo.
Regarding claim 5, Rajashekhar teaches the method [see title] as discussed above in claim 4. Rajashekhar in view of Yoo (with reference to Yoo) also teaches wherein the chlorine-containing silicon source material includes dichlorosilane (second precursor = dichlorosilane [0028]), and the chlorine-free silicon source material includes monosilane (first precursor = monosilane [0028]).
Regarding claim 6, Rajashekhar teaches the method [see title] as discussed above in claim 4. Rajashekhar in view of Yoo (with reference to Yoo) also teaches wherein the deposition process is performed, with a proportion of the chlorine-free silicon source (first precursor = monosilane [0028]) is material larger than a proportion of the chlorine-containing silicon source material (second precursor = dichlorosilane [0028]) (may be about 3-7:1 ratio of monosilane:dichlorosilane [0030]).
Regarding claim 7, Rajashekhar teaches the method [see title] as discussed above in claim 4. Rajashekhar in view of Yoo (with reference to Yoo) also teaches wherein the deposition process adjusts a deposition ratio of the polysilicon layer to the sacrificial amorphous silicon layer to 1.1:1 to 1.3:1 (precursor ratio may be about 3-7:1 ratio of monosilane:dichlorosilane [0030]).
Although Yoo does not explicitly mention a “deposition ratio” – [0058-0059] of the instant application’s specification teaches that a deposition ratio of 1.1:1 – 1.5:1 can be achieved by varying the monosilane:dichlorosilane ratio from about 8:1 to about 3:1. Therefore, Yoo’s disclosed range of about 3:1-7:1 is taken to imply a deposition ratio of about 1.5:1 to about 1.1:1, which encompasses the claimed range of about 1.1:1 to about 1.3:1 for the “deposition ratio” - in view of the instant application’s specification [0058-0059].
Regarding claim 8, Rajashekhar teaches the method [see title] as discussed above in claim 6. Rajashekhar in view of Yoo (with reference to Yoo) also teaches wherein the deposition process is performed, with a mixing ratio of the chlorine-free silicon source material to the chlorine-containing silicon source material (precursor ratio may be about 3-7:1 ratio of monosilane:dichlorosilane [0030]) adjusted from 7:1 to 9:1 (the 3 to about 7 range disclosed by Yoo is considered to overlap with the scope of the claimed range of 7-9:1 since [0030] and [0049] make it clear that the exemplary range is non-limiting and “indicates a range of values, for example but not limited to” 3-7:1).
Claims 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar (U.S. Patent No 10,804,291) (of record) modified by of Iwai (U.S. Patent No 10,290,650) (of record), Lue (U.S. PG Pub No US2012/0182808A1) (of record), and Thadjoisworo (U.S. PG Pub No US2014/0004708A1), as applied in claim 1 above, and further in view of Yamazaki (U.S. PG Pub No US2014/0027764A1) (of record).
Regarding claim 10, Rajashekhar teaches the method [see title] as discussed above in claim 1. Rajashekhar also teaches wherein the second semiconductor material (272) fig. 15A [col 19, lines 43-60] includes amorphous silicon.
However, Rajashekhar does not explicitly disclose wherein the first semiconductor material (114) fig. 11D [col 19, lines 8-32] includes polysilicon (single-crystalline instead [col 19, lines 8-32] because substrate is single-crystal [col 19, lines 8-32] so 60 and 114 single crystal).
Yamazaki teaches a method [0114] wherein the first semiconductor material (material which matches crystallinity of substrate in Rajashekhar) includes polysilicon (Yamazaki discloses that substrate 115 fig. 1A [0115-0117, 0079] and other layers formed therefrom [0117] may be either single or polycrystalline silicon).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the crystallinity of the silicon substrate and silicon materials epitaxially grown to match the crystallinity of the substrate in Rajashekhar to possibly comprise polycrystalline silicon as an alternative to single-crystalline as both may forms of silicon enable the easy manufacture of high-speed transistors [0079, 0115-0117], as taught by Yamazaki.
Regarding claim 15, Rajashekhar teaches the method [see title] as discussed above in claim 13. However, Rajashekhar does not explicitly disclose wherein the vertical channel layer (60) fig. 15C [col 20, lines 43-65] and the source layer (116 with 122) fig. 11E [col 18, lines 8-38] include polysilicon (single-crystalline instead [col 19, lines 8-32] because substrate is single-crystal [col 19, lines 8-32] so 60 and 114/122 single crystal).
Yamazaki teaches a method [0114] wherein the vertical channel layer and the source layer (materials which match crystallinity of substrate in Rajashekhar) include polysilicon (Yamazaki discloses that substrate 115 fig. 1A [0115-0117, 0079] and other layers formed therefrom [0117] may be either single or polycrystalline silicon)
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the crystallinity of the silicon substrate and silicon materials epitaxially grown to match the crystallinity of the substrate in Rajashekhar to possibly comprise polycrystalline silicon as an alternative to single-crystalline as both may forms of silicon enable the easy manufacture of high-speed transistors [0079, 0115-0117], as taught by Yamazaki.
Claims 17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar (U.S. Patent No 10,804,291) (of record) in view of Yang (U.S. PG Pub No US2016/0027796A1) (of record), Iwai (U.S. Patent No 10,290,650) (of record), Balakrishnan (U.S. PG Pub No US2019/0067280A1) (of record), Thadjoisworo (U.S. PG Pub No US2014/0004708A1), and Lue (U.S. PG Pub No US2012/0182808A1) (of record).
Regarding claim 17, Rajashekhar teaches a method for manufacturing a vertical semiconductor device [see title], the method comprising:
forming a lower level stack (comprising 132, 142) fig. 2 [col 8, lines 15-30] over a semiconductor substrate (9) fig. 11A [col 18, lines 54-57], the lower level stack including a source sacrificial layer (104) fig. 2 [col 6, lines 4 – col 7, line 14] and a source layer (116) fig. 2 [col 17, line 44-col 18, line 5];
forming an alternate stack (comprising 232, 242) fig. 5 [col 12, lines 11-45] on the lower level stack (comprising 132, 142), the alternate stack (232, 242) including insulation layers (232) [col 12, lines 11-45] and sacrificial (242) [col 12, lines 11-45] layers;
forming a vertical channel structure (60) fig. 15C [col 20, lines 43-65] including a channel layer (60) penetrating the alternate stack (232, 242) and the lower level stacks (comprising 132, 142);
forming a slit (79) fig. 10A [col 17, lines 8-66] exposing the source sacrificial layer (104) and penetrating the alternate stack (232, 242);
forming a sealing layer (270) fig. 5 [col 13, lines 25-32] (silicon oxide) on a side wall of the slit (79);
forming a horizontal recess (109) fig. 11B [col 18, lines 20-40] extending from the slit (79) by removing the source sacrificial layer (104);
exposing a portion of the channel layer (60) from the horizontal recess (79) [see fig. 15C];
exposing an exposed surface (surface of 60 in contact with 114) of the channel layer (60) to a pre-cleaning process of halogen gas (HF gas exposure) [see fig. 15C, col 20, lines 43-65].
However, Rajashekhar does not explicitly disclose selectively growing, in-situ, a polysilicon layer on the exposed surface of the channel layer (60) after the pre-cleaning process,
wherein growing the polysilicon layer includes:
performing a deposition process to selectively form a sacrificial amorphous silicon layer on a surface of the sealing layer while simultaneously epitaxial-growing, selectively, the polysilicon layer as a source contact layer on the pre-cleaned exposed surface of the channel layer (60); and
selectively removing the sacrificial amorphous layer,
wherein a contact surface between the vertical channel layer (60) and the polysilicon layer includes an oxide-free surface, and a contact surface between the polysilicon layer and the sacrificial amorphous silicon layer includes an oxidized surface.
Yang teaches a method comprising selectively growing, in-situ [0109], a polysilicon layer (124) fig. 4G [0109] on the exposed surface of the channel layer (122) fig. 4G [0106-0107] after the pre-cleaning process [etching in fig. 4G, 0104-0105],
wherein growing the polysilicon layer (124) includes:
epitaxial-growing (ALD [0109]) the polysilicon layer (124) on the pre-cleaned exposed surface of the channel layer (122).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the channel layer formed in Rajashekhar’s method to be formed of additional silicon channel layers [0052] formed by a selective ALD process with in-situ doping [0109] in order to favorably improve the performance of the channel structure [0052-0056] in ways such as reducing local resistance to boost memory cell current [0053] and increasing surface area to reduce contact resistance [0136], as taught by Yang.
However, Rajashekar in view of Yang does not explicitly disclose wherein growing the polysilicon layer includes:
performing a deposition process to selectively form a sacrificial amorphous silicon layer on a surface of the sealing layer while simultaneously growing, selectively, the polysilicon layer as a source contact layer; and
selectively removing the sacrificial amorphous silicon layer;
exposing to a pre-treatment process to remove a native oxide on the exposed surface of the channel layer before exposing to the pre-cleaning process,
wherein a contact surface between the vertical channel layer (60) and the polysilicon layer includes an oxide-free surface, and a contact surface between the polysilicon layer and the sacrificial amorphous silicon layer includes an oxidized surface,
(and) wherein the pre-treatment process is performed using nitrogen trifluoride (NF3).
Iwai teaches a method [col 3, lines 48-57] wherein growing the polysilicon layer (10A) fig. 2 [col 7, lines 9-17] includes:
performing a deposition process to selectively form a sacrificial amorphous silicon layer (303) fig. 2 [col 7, lines 22-34] on a surface of the sealing layer (410) fig. 2 [col 6, lines 53-57] while simultaneously growing, selectively, the polysilicon layer (10A) fig. 2 [col 7, lines 9-17] as a source contact layer [col 7, lines 9-17]; and
selectively removing [see fig. 10A, col 21, lines 59-64] the sacrificial amorphous silicon layer (303),
wherein a contact surface between the polysilicon layer (10A) and the sacrificial amorphous silicon layer (303) includes an oxidized surface (301) fig. 2 [col 7, lines 18-21] (thin silicon oxide layer may optionally adjoin the contact surfaces of 10A and 303).
With respect to whether Iwai discloses the simultaneous deposition of amorphous silicon layer (303) with polysilicon layer (10A) – Iwai is silent as to whether the deposition of the amorphous layer (303) and polysilicon (10A) occurs simultaneously or sequentially between fig. 1 and fig. 2. However, such a distinction reflects a mere change in the sequence of adding layers which does not produce any apparent difference in the finished product. Therefore, unless Applicant can prove unexcepted results in depositing the amorphous silicon and polysilicon layers at the same or different times, the claimed limitations are considered within the scope of the teaching of Iwai. (See MPEP 2144.04, IV, C).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Rajashekhar in view of Yang to include the formation of the amorphous silicon, polysilicon, and silicon oxide layers of Iwai in the concurrent manner [col 6, lines 49-60] shown by Iwai in order to effectively reduce memory cell size using a simplified/less-complex series of processes [col 30, lines 27-36], as taught by Iwai.
However, Rajashekhar in view of Yang and Iwai does not explicitly disclose
exposing to a pre-treatment process to remove a native oxide on the exposed surface of the channel layer before exposing to the pre-cleaning process,
wherein a contact surface between the vertical channel layer (60) and the polysilicon layer includes an oxide-free surface,
(and) wherein the pre-treatment process is performed using nitrogen trifluoride (NF3).
Balakrishnan teaches a method [0008, 0079] comprising exposing to a pre-treatment process to remove a native oxide (138) figs. 11-12 [0079] on the exposed surface of the channel layer (channel 140) figs. 11-12 [0078-0082] before (simultaneously) exposing to the pre-cleaning process (involving use of H2 plasma).
With respect to Balakrishnan disclosing the claimed ‘pre-treatment’ process (defined as the NF3 plasma exposure) as occurring “before” the claimed ‘pre-cleaning’ process (defined as the H2 plasma exposure), [0079] of Balakrishnan discloses simultaneous cleaning/treatment using a plurality of chemicals. However, the difference in the order of exposure reflects a trivial change of sequence in the steps used to remove the oxide material from the channel, which – in the absence of evidence of unexpected results – does not introduce a patentable difference to the claim language. (See MPEP 2144.04, IV, C).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Rajashekhar in view of Yang and Iwai such that the etchants of the cleaning process(es) are accompanied by plasma byproducts including NF3 [0079] in order to gently remove the oxide at low temperatures [0079], as taught by Balakrishnan.
However, Rajashekhar in view of Yang, Iwai, and Balakrishnan does not explicitly disclose wherein the pre-treatment process is performed using (itself) a fluorine-based chemical including nitrogen trifluoride (NF3) nitrogen trifluoride [0079].
Thadjoisworo teaches a method [see title] wherein the pre-treatment process (removing the native oxide from the first surface (“native oxide etch”) [0093]) is performed using a fluorine-based chemical including nitrogen trifluoride (“to remove the native oxide, the H.sub.2/NF.sub.3 plasma uses a concentration of NF.sub.3 of 4.1% by volume” [0093]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Yang, Iwai, and Balakrishnan such that the removal of the native oxide from the memory structure itself is explicitly performed with the ‘use of’ nitrogen trifluoride [0093] in order to ensure sufficient removal of the native oxide [0093], as taught by Thadjoisworo.
However, Rajashekhar in view of Yang, Iwai, Balakrishnan, and Thadjoisworo does not explicitly disclose wherein a contact surface between the vertical channel layer and the polysilicon layer (“source semiconductor layer 10A” of Iwai) includes an oxide-free surface.
Lue teaches a method of manufacturing a vertical semiconductor device [see title] wherein a contact surface (top of ‘source’ layer 4) fig. 2 [0020] between the vertical channel layer (20) fig. 3 [0020] and the polysilicon layer (4) fig. 2 [0020] (“source semiconductor layer 10A” is polysilicon in Iwai) includes an oxide-free surface (cleaning process for removing native oxide [0020] applied to surface of source layer [0020]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Yang, Iwai, Balakrishnan, and Thadjoisworo to apply the source structure cleaning process of Lue to the polysilicon source structure of Iwai in order to improve the quality of the channel layer(s) grown thereon [0020] as well as the material quality of the connection between the contact surfaces [0020], as taught by Lue.
Regarding claim 19, Rajashekhar teaches the method [see title] as discussed above in claim 17. Rajashekhar in view of Yang (with reference to Yang) also teaches wherein the polysilicon layer (124) fig. 4G [0109] is selectively epitaxial-grown (by ALD) [0109] on the exposed surface of the channel layer (122) fig. 4G [0106].
Regarding claim 20, Rajashekhar teaches the method [see title] as discussed above in claim 17. Rajashekhar in view of Yang (with reference to Yang) also teaches wherein the polysilicon layer (124) fig. 4G [0109] includes a polysilicon layer (124) selectively epitaxial-grown (by ALD) [0109] on the exposed surface of the channel layer (122) fig. 4G [0106].
Claims 22-26 are rejected under 35 U.S.C. 103 as being unpatentable over Rajashekhar (U.S. Patent No 10,804,291) (of record) in view of Yang (U.S. PG Pub No US2016/0027796A1) (of record), Iwai (U.S. Patent No 10,290,650) (of record), Balakrishnan (U.S. PG Pub No US2019/0067280A1) (of record), Thadjoisworo (U.S. PG Pub No US2014/0004708A1), and Lue (U.S. PG Pub No US2012/0182808A1) (of record), as applied in claim 17 above, and further in view of Yoo (U.S. PG Pub No US2020/0090996A1) (of record).
Regarding claim 22, Rajashekhar teaches the method [see title] as discussed above in claim 17. However, Rajashekhar does not explicitly disclose wherein the deposition process [see fig. 8B, col 16, lines 16-37] (of amorphous/polysilicon [see fig. 8B, col 16, lines 16-37]) is performed using a mixture of a chlorine-containing silicon source material and a chlorine-free silicon source material.
Yoo teaches a method [0002] wherein the deposition process [see fig. 6, 0029-0030] (of polysilicon layer 140 [0030]) is performed using a mixture of a chlorine-containing silicon source material (second precursor = dichlorosilane [0028]) and a chlorine-free silicon source material (first precursor = monosilane [0028]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the deposition of the silicon material(s) in Rajashekhar’s method to be performed using a mixture of SiH4 and SiH2Cl2 [0028-0030] with the art-recognized proportion and pressure ranges [0030] specified by Yoo in order to successfully form the polycrystalline silicon material [0030] with a reduced roughness that decreases the presence of voids and seams [0030] in the deposited silicon [0028-0030], as taught by Yoo.
Regarding claim 23, Rajashekhar teaches the method [see title] as discussed above in claim 22. Rajashekhar in view of Yoo (with reference to Yoo) also teaches wherein the chlorine-containing silicon source material includes dichlorosilane (second precursor = dichlorosilane [0028]), and the chlorine-free silicon source material includes monosilane (first precursor = monosilane [0028]).
Regarding claim 24, Rajashekhar teaches the method [see title] as discussed above in claim 22. Rajashekhar in view of Yoo (with reference to Yoo) also teaches wherein the deposition process is performed, with a proportion of the chlorine-free silicon source (first precursor = monosilane [0028]) is material larger than a proportion of the chlorine-containing silicon source material (second precursor = dichlorosilane [0028]) (may be about 3-7:1 ratio of monosilane:dichlorosilane [0030]).
Regarding claim 25, Rajashekhar teaches the method [see title] as discussed above in claim 24. Rajashekhar in view of Yoo (with reference to Yoo) also teaches wherein the deposition process adjusts a deposition ratio of the polysilicon layer to the sacrificial amorphous silicon layer to 1.1:1 to 1.3:1 (precursor ratio may be about 3-7:1 ratio of monosilane:dichlorosilane [0030]).
Although Yoo does not explicitly mention a “deposition ratio” – [0058-0059] of the instant application’s specification teaches that a deposition ratio of 1.1:1 – 1.5:1 can be achieved by varying the monosilane:dichlorosilane ratio from about 8:1 to about 3:1. Therefore, Yoo’s disclosed range of about 3:1-7:1 is taken to imply a deposition ratio of about 1.5:1 to about 1.1:1, which encompasses the claimed range of about 1.1:1 to about 1.3:1 for the “deposition ratio” - in view of the instant application’s specification [0058-0059].
Regarding claim 26, Rajashekhar teaches the method [see title] as discussed above in claim 24. Rajashekhar in view of Yoo (with reference to Yoo) also teaches wherein the deposition process is performed, with a mixing ratio of the chlorine-free silicon source material to the chlorine-containing silicon source material (precursor ratio may be about 3-7:1 ratio of monosilane:dichlorosilane [0030]) adjusted from 7:1 to 9:1 (the 3 to about 7 range disclosed by Yoo is considered to overlap with the scope of the claimed range of 7-9:1 since [0030] and [0049] make it clear that the exemplary range is non-limiting and “indicates a range of values, for example but not limited to” 3-7:1).
Response to Arguments
Applicant’s arguments, see pages 2-3, filed 08/01/2025, with respect to the rejection(s) of claim(s) 1 and 17 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Thadjoisworo (U.S. PG Pub No US2014/0004708A1).
Conclusion
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 08/23/2025
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892