DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claim 1 is amended.
Claims 7-10 are withdrawn.
Election/Restrictions
Claim 7 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: Claim 7 is withdrawn according to Response to Election/Restriction Filed 11/28/2024.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claim 7 is withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/03/2025 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 and 3-6 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “when viewed from the bottom surface parallel to the direction of lamination, positions of the conductive via holes of each of the coil patterns overlap; when viewed from the side surface perpendicular to the direction of lamination, the positions of the conductive via holes of each of the coil patterns do not overlap” contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The term “positions” is not clearly defined in the claim limitations. In addition, the term “overlap” is not clearly defined in the claim limitations. According to www.merriam-webster.com, the term “overlap” is defined as “extend over” or “cover a part of”. Therefore, “when viewed from the bottom surface parallel to the direction of lamination”, “the conductive via holes of each of the coil patterns” have both overlap and non-overlap since any two adjacent conductive via holes are opposing each other. Moreover, “when viewed from the side surface perpendicular to the direction of lamination”, “the positions of the conductive via holes of each of the coil patterns” have both overlap and non-overlap since any two adjacent conductive via holes are opposing each other. The examiner suggests other terms to specifically describe “the conductive via holes of each of the coil patterns”.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 3-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the side surface" in line 15. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites “when viewed from the bottom surface parallel to the direction of lamination, positions of the conductive via holes of each of the coil patterns overlap; when viewed from the side surface perpendicular to the direction of lamination, the positions of the conductive via holes of each of the coil patterns do not overlap” is indefinite and unclear. The term “positions” is not clearly defined in the claim limitations. As shown in Fig. 3, “when viewed from the bottom surface parallel to the direction of lamination”, the position of the middle conductive via does not overlap with the positions of the upper and lower conductive vias. Therefore, the claim limitations “when viewed from the bottom surface parallel to the direction of lamination, positions of the conductive via holes of each of the coil patterns overlap” will need to be more specific since any two adjacent conductive via holes are opposing each other. The examiner suggests other terms to specifically describe “the conductive via holes of each of the coil patterns”.
Claim 1 recites “when viewed from the bottom surface parallel to the direction of lamination, positions of the conductive via holes of each of the coil patterns overlap; when viewed from the side surface perpendicular to the direction of lamination, the positions of the conductive via holes of each of the coil patterns do not overlap” is indefinite and unclear. The term “positions” is not clearly defined in the claim limitations. As shown in Fig. 3, “when viewed from the side surface perpendicular to the direction of lamination, the positions of the conductive via holes of each of the coil patterns do not overlap”, the position of the middle conductive via does not overlap with the positions of the upper and lower conductive vias but the positions of the upper and lower conductive vias are overlapping. Therefore, the claim limitations “when viewed from the side surface perpendicular to the direction of lamination, the positions of the conductive via holes of each of the coil patterns do not overlap” will need to be more specific since any two adjacent conductive via holes are opposing each other. The examiner suggests other terms to specifically describe “the conductive via holes of each of the coil patterns”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lyoo et al. [U.S. Pub. No. 2016/0351321] in view of Miyoshi [U.S. Pub. No. 2017/0287620].
Regarding Claim 1, Lyoo et al. shows a laminated electronic device (see Fig. 2 with teachings from Figs. 5A-10M and see Drawing 1 below), comprising a laminate (see Fig. 2, Paragraphs [0109], [0111]), an internal coil (20), a first external electrode (31’), and a second external electrode (32’), wherein the laminate comprises a plurality of laminated insulator layers (111 or 211, see Fig. 2 and see Figs. 5A-10M), the laminate has a multi-layer coil pattern (21 or 121) provided between the plurality of insulator layers (111 or 211) in a laminated manner (see Fig. 2 and see Figs. 5A-10M), the plurality of insulator layers (111 or 211) are provided with conductive via holes (41, 141, for example first and second elements 41 from the front as shown in Fig. 2), adjacent layers of the coil pattern (21 or 121) are electrically connected through the conductive via holes (41, 141, for example first and second elements 41) to form the internal coil (20, see Fig. 2 and see Figs. 5A-10M), the first external electrode (31’) and the second external electrode (32’) are disposed on a bottom surface (bottom surface BS, see Drawing 1 below) of the laminate which is parallel to a direction (direction D) of lamination (see Fig. 2 and Drawing 1 below), and the first external electrode (31’) and the second external electrode (32’) are connected to two ends of the internal coil (see Fig. 2 and claim 1), respectively, wherein the conductive via holes (41, for example first and second elements 41) do not overlap with either the first external electrode or the second external electrode as viewed from the bottom surface parallel to the direction of lamination (see Fig. 2 and Drawing 1 below, elements 41, for example first and second elements 41, do not overlap with either element 31’ or 32’ as viewed from the bottom surface BS parallel to the direction D); when viewed from the bottom surface parallel to the direction of lamination, positions of the conductive via holes of each of the coil patterns overlap (see Fig. 2 and Drawing 1 below, when viewed from bottom surface BS parallel to direction D, positions of elements 41, for example first and second elements 41, of each elements 21 overlap, see also 112 rejections above); when viewed from the side surface (side surface SS) perpendicular to the direction of lamination, the positions of the conductive via holes of each of the coil patterns do not overlap (see Fig. 2 and Drawing 1 below, when viewed from the side surface SS perpendicular to direction D, the positions of elements 41, for example first and second elements 41, of each elements 21 do not overlap, see also 112 rejections above); the internal coil (20) formed by the multiple layers of the coil pattern (21) electrically connected with each other is a spiral coil (see Fig. 2 and see Figs. 5A-10M, element 20 formed by multiple layers of element 21 electrically connected with each other is a spiral coil).
Lyoo et al. does not explicitly disclose a combination of the coil patterns of two adjacent layers forms no more than one turn of the spiral coil.
Miyoshi shows an electronic component (Fig. 2) teaching and suggesting a laminate (Paragraph [0039]) comprises a plurality of laminated insulator layers (16a-16k), and a combination of the coil patterns of two adjacent layers (18a, 18b or 18j, 18i) forms no more than one turn of the spiral coil (see Fig. 2, Paragraph [0052]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a combination of the coil patterns of two adjacent layers forms no more than one turn of the spiral coil as taught by Miyoshi for the device as disclosed by Lyoo et al. to achieve avoidance of a short circuit and obtaining desirable inductance and improve Q value (Paragraphs [0052], [0080]).
Regarding Claim 4, Miyoshi shows the first external electrode (14a) comprises a plurality of first electrode strips (25a-25j) which are pre-formed on a first side (left portion) of a bottom end of the plurality of insulator layers (see Figs. 1-2), and the plurality of first electrode strips (25a-25j) are laminated together to jointly form the first external electrode (14a, Paragraph [0042]); and the second external electrode (14b) comprises a plurality of second electrode strips (26a-26j) which are pre-formed on a second side (right portion) of the bottom end of the plurality of insulator layers (see Figs. 1-2), and the plurality of second electrode strips (26a-26j) are laminated together to jointly form the second external electrode (14b, Paragraph [0044]).
Regarding Claim 5, Miyoshi shows the first side (left portion) and the second side (right portion) of the bottom end of the plurality of insulator layers (16b-16j) are configured as recesses (cutout, Paragraphs [0042], [0044]), and the plurality of first electrode strip layers (25a-25j) and the plurality of second electrode strip layers (26a-26j) just fill up the recesses so that the bottom surface of the laminate provided with the first external electrode (14a) and the second external electrode (14b) becomes a flat surface (see Fig. 3A).
Regarding Claim 6, Lyoo et al. shows each of the first external electrode (31’) and the second external electrode (32’) is an external electrode integrally formed on the bottom surface (bottom surface BS) of the laminate (see Fig. 2 and Drawing 1 below, Paragraph [0078]).
Miyoshi shows each of the first external electrode (14a) and the second external electrode (14b) is an external electrode integrally formed on the bottom surface of the laminate (see Figs. 1-3A).
Claim(s) 1 and 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee [U.S. Pub. No. 2015/0084730] in view of Lyoo et al. [U.S. Pub. No. 2016/0351321] and Miyoshi [U.S. Pub. No. 2017/0287620].
Regarding Claim 1, Lee shows a laminated electronic device (see Fig. 2-4), comprising a laminate (see Fig. 2), an internal coil (211, 212, 213 combined), a first external electrode (131), and a second external electrode (132), wherein the laminate comprises a plurality of laminated insulator layers (113), the laminate has a multi-layer coil pattern (211, 212, 213) provided between the plurality of insulator layers (113) in a laminated manner (see Fig. 2), the plurality of insulator layers (113) are provided with conductive via holes (270, for example first and second elements 270 from the top as shown in Figs. 2, 4), adjacent layers of the coil pattern (211, 213) are electrically connected through the conductive via holes (270, for example first and second elements 270) to form the internal coil (211, 212, 213 combined, see Fig. 2), the first external electrode (131) and the second external electrode (132) are disposed on a bottom surface (front surface in the W-direction, see Figs. 2, 4) of the laminate which is parallel to a direction (T-direction) of lamination (see Figs. 2, 4), and the first external electrode (131) and the second external electrode (132) are connected to two ends of the internal coil (see Fig. 4, Paragraph [0053]), respectively, wherein the conductive via holes (270, for example first and second elements 270) do not overlap with either the first external electrode or the second external electrode as viewed from the bottom surface parallel to the direction of lamination (see Fig. 2, elements 270, for example first and second elements 270, do not overlap with either element 131 or 132 as viewed from the front surface parallel to the direction in the T-direction); when viewed from the bottom surface parallel to the direction of lamination, positions of the conductive via holes of each of the coil patterns overlap (see Fig. 4 or Fig. 2, when viewed from front surface in the W-direction parallel to direction of lamination, positions of elements 270, for example first and second elements 270 from the top of Fig. 4, of each elements 211, two elements 213 overlap, see also 112 rejections above); when viewed from the side surface perpendicular to the direction of lamination, the positions of the conductive via holes of each of the coil patterns do not overlap (see Fig. 2, when viewed from the side surface in the T-direction perpendicular to direction of lamination, the positions of elements 270, for example first and second elements 270 from the top of Fig. 2, of each elements 211, two elements 213 do not overlap, see also 112 rejections above); the internal coil (211, 212, 213 combined) formed by the multiple layers of the coil pattern (211, 212, 213) electrically connected with each other is a spiral coil (see Figs. 2 and 4).
Lee does not explicitly disclose a combination of the coil patterns of two adjacent layers forms no more than one turn of the spiral coil.
Furthermore, Lyoo et al. clearly shows a laminated electronic device (see Fig. 2 with teachings from Figs. 5A-10M and see Drawing 1 below), comprising a laminate (see Fig. 2, Paragraphs [0109], [0111]), an internal coil (20), a first external electrode (31’), and a second external electrode (32’), wherein the laminate comprises a plurality of laminated insulator layers (111 or 211, see Fig. 2 and see Figs. 5A-10M), the laminate has a multi-layer coil pattern (21 or 121) provided between the plurality of insulator layers (111 or 211) in a laminated manner (see Fig. 2 and see Figs. 5A-10M), the plurality of insulator layers (111 or 211) are provided with conductive via holes (41, 141, for example first and second elements 41 from the front as shown in Fig. 2), adjacent layers of the coil pattern (21 or 121) are electrically connected through the conductive via holes (41, 141, for example first and second elements 41) to form the internal coil (20, see Fig. 2 and see Figs. 5A-10M), the first external electrode (31’) and the second external electrode (32’) are disposed on a bottom surface (bottom surface BS, see Drawing 1 below) of the laminate which is parallel to a direction (direction D) of lamination (see Fig. 2 and Drawing 1 below), and the first external electrode (31’) and the second external electrode (32’) are connected to two ends of the internal coil (see Fig. 2 and claim 1), respectively, wherein the conductive via holes (41, for example first and second elements 41) do not overlap with either the first external electrode or the second external electrode as viewed from the bottom surface parallel to the direction of lamination (see Fig. 2 and Drawing 1 below, elements 41, for example first and second elements 41, do not overlap with either element 31’ or 32’ as viewed from the bottom surface BS parallel to the direction D); when viewed from the bottom surface parallel to the direction of lamination, positions of the conductive via holes of each of the coil patterns overlap (see Fig. 2 and Drawing 1 below, when viewed from bottom surface BS parallel to direction D, positions of elements 41, for example first and second elements 41, of each elements 21 overlap, see also 112 rejections above); when viewed from the side surface (side surface SS) perpendicular to the direction of lamination, the positions of the conductive via holes of each of the coil patterns do not overlap (see Fig. 2 and Drawing 1 below, when viewed from the side surface SS perpendicular to direction D, the positions of elements 41, for example first and second elements 41, of each elements 21 do not overlap, see also 112 rejections above); the internal coil (20) formed by the multiple layers of the coil pattern (21) electrically connected with each other is a spiral coil (see Fig. 2 and see Figs. 5A-10M, element 20 formed by multiple layers of element 21 electrically connected with each other is a spiral coil).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a laminate and the first external electrode and the second external electrode are disposed on a bottom surface of the laminate which is parallel to a direction as taught by Lyoo et al. for the device as disclosed by Lee to significantly decrease the generation of parasitic capacitance (Paragraph [0079]).
Lee in view of Lyoo et al. does not explicitly disclose a combination of the coil patterns of two adjacent layers forms no more than one turn of the spiral coil.
Miyoshi shows an electronic component (Fig. 2) teaching and suggesting a laminate (Paragraph [0039]) comprises a plurality of laminated insulator layers (16a-16k), and a combination of the coil patterns of two adjacent layers (18a, 18b or 18j, 18i) forms no more than one turn of the spiral coil (see Fig. 2, Paragraph [0052]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a combination of the coil patterns of two adjacent layers forms no more than one turn of the spiral coil as taught by Miyoshi for the device as disclosed by Lee in view of Lyoo et al. to achieve avoidance of a short circuit and obtaining desirable inductance and improve Q value (Paragraphs [0052], [0080]).
Regarding Claim 4, Miyoshi shows the first external electrode (14a) comprises a plurality of first electrode strips (25a-25j) which are pre-formed on a first side (left portion) of a bottom end of the plurality of insulator layers (see Figs. 1-2), and the plurality of first electrode strips (25a-25j) are laminated together to jointly form the first external electrode (14a, Paragraph [0042]); and the second external electrode (14b) comprises a plurality of second electrode strips (26a-26j) which are pre-formed on a second side (right portion) of the bottom end of the plurality of insulator layers (see Figs. 1-2), and the plurality of second electrode strips (26a-26j) are laminated together to jointly form the second external electrode (14b, Paragraph [0044]).
Regarding Claim 5, Miyoshi shows the first side (left portion) and the second side (right portion) of the bottom end of the plurality of insulator layers (16b-16j) are configured as recesses (cutout, Paragraphs [0042], [0044]), and the plurality of first electrode strip layers (25a-25j) and the plurality of second electrode strip layers (26a-26j) just fill up the recesses so that the bottom surface of the laminate provided with the first external electrode (14a) and the second external electrode (14b) becomes a flat surface (see Fig. 3A).
Regarding Claim 6, Lyoo et al. shows each of the first external electrode (31’) and the second external electrode (32’) is an external electrode integrally formed on the bottom surface (bottom surface BS) of the laminate (see Fig. 2 and Drawing 1 below, Paragraph [0078]).
Miyoshi shows each of the first external electrode (14a) and the second external electrode (14b) is an external electrode integrally formed on the bottom surface of the laminate (see Figs. 1-3A).
Claim(s) 1 and 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lyoo et al. [U.S. Pub. No. 2016/0351321] in view of Lee [U.S. Pub. No. 2015/0084730] and Miyoshi [U.S. Pub. No. 2017/0287620].
Regarding Claim 1, Lyoo et al. shows a laminated electronic device (see Fig. 2 with teachings from Figs. 5A-10M and see Drawing 1 below), comprising a laminate (see Fig. 2, Paragraphs [0109], [0111]), an internal coil (20), a first external electrode (31’), and a second external electrode (32’), wherein the laminate comprises a plurality of laminated insulator layers (111 or 211, see Fig. 2 and see Figs. 5A-10M), the laminate has a multi-layer coil pattern (21 or 121) provided between the plurality of insulator layers (111 or 211) in a laminated manner (see Fig. 2 and see Figs. 5A-10M), the plurality of insulator layers (111 or 211) are provided with conductive via holes (41, 141, for example first and second elements 41 from the front as shown in Fig. 2), adjacent layers of the coil pattern (21 or 121) are electrically connected through the conductive via holes (41, 141, for example first and second elements 41) to form the internal coil (20, see Fig. 2 and see Figs. 5A-10M), the first external electrode (31’) and the second external electrode (32’) are disposed on a bottom surface (bottom surface BS, see Drawing 1 below) of the laminate which is parallel to a direction (direction D) of lamination (see Fig. 2 and Drawing 1 below), and the first external electrode (31’) and the second external electrode (32’) are connected to two ends of the internal coil (see Fig. 2 and claim 1), respectively, wherein the conductive via holes (41, for example first and second elements 41) do not overlap with either the first external electrode or the second external electrode as viewed from the bottom surface parallel to the direction of lamination (see Fig. 2 and Drawing 1 below, elements 41, for example first and second elements 41, do not overlap with either element 31’ or 32’ as viewed from the bottom surface BS parallel to the direction D); when viewed from the bottom surface parallel to the direction of lamination, positions of the conductive via holes of each of the coil patterns overlap (see Fig. 2 and Drawing 1 below, when viewed from bottom surface BS parallel to direction D, positions of elements 41, for example first and second elements 41, of each elements 21 overlap, see also 112 rejections above); when viewed from the side surface (side surface SS) perpendicular to the direction of lamination, the positions of the conductive via holes of each of the coil patterns do not overlap (see Fig. 2 and Drawing 1 below, when viewed from the side surface SS perpendicular to direction D, the positions of elements 41, for example first and second elements 41, of each elements 21 do not overlap, see also 112 rejections above); the internal coil (20) formed by the multiple layers of the coil pattern (21) electrically connected with each other is a spiral coil (see Fig. 2 and see Figs. 5A-10M, element 20 formed by multiple layers of element 21 electrically connected with each other is a spiral coil).
Lyoo et al. does not explicitly disclose a combination of the coil patterns of two adjacent layers forms no more than one turn of the spiral coil.
Furthermore, Lee clearly shows (Figs. 2-4) when viewed from the bottom surface parallel to the direction of lamination, positions of the conductive via holes of each of the coil patterns overlap (see Fig. 4 or Fig. 2, when viewed from front surface in the W-direction parallel to direction of lamination, positions of elements 270, for example first and second elements 270 from the top of Fig. 4, of each elements 211, two elements 213 overlap, see also 112 rejections above); when viewed from the side surface perpendicular to the direction of lamination, the positions of the conductive via holes of each of the coil patterns do not overlap (see Fig. 2, when viewed from the side surface in the T-direction perpendicular to direction of lamination, the positions of elements 270, for example first and second elements 270 from the top of Fig. 2, of each elements 211, two elements 213 do not overlap, see also 112 rejections above); the internal coil (211, 212, 213 combined) formed by the multiple layers of the coil pattern (211, 212, 213) electrically connected with each other is a spiral coil (see Figs. 2 and 4).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have when viewed from the bottom surface parallel to the direction of lamination, positions of the conductive via holes of each of the coil patterns overlap and when viewed from the side surface perpendicular to the direction of lamination, the positions of the conductive via holes of each of the coil patterns do not overlap as taught by Lee for the device as disclosed by Lyoo et al. in view of Lee to simplify design to achieve desirable coupling characteristics with optimizing vertical distance while maintaining connectivity of via electrodes and decreasing an open defect (Paragraph [0014]).
Lyoo et al. in view of Lee does not explicitly disclose a combination of the coil patterns of two adjacent layers forms no more than one turn of the spiral coil.
Miyoshi shows an electronic component (Fig. 2) teaching and suggesting a laminate (Paragraph [0039]) comprises a plurality of laminated insulator layers (16a-16k), and a combination of the coil patterns of two adjacent layers (18a, 18b or 18j, 18i) forms no more than one turn of the spiral coil (see Fig. 2, Paragraph [0052]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a combination of the coil patterns of two adjacent layers forms no more than one turn of the spiral coil as taught by Miyoshi for the device as disclosed by Lyoo et al. in view of Lee to achieve avoidance of a short circuit and obtaining desirable inductance and improve Q value (Paragraphs [0052], [0080]).
Regarding Claim 4, Miyoshi shows the first external electrode (14a) comprises a plurality of first electrode strips (25a-25j) which are pre-formed on a first side (left portion) of a bottom end of the plurality of insulator layers (see Figs. 1-2), and the plurality of first electrode strips (25a-25j) are laminated together to jointly form the first external electrode (14a, Paragraph [0042]); and the second external electrode (14b) comprises a plurality of second electrode strips (26a-26j) which are pre-formed on a second side (right portion) of the bottom end of the plurality of insulator layers (see Figs. 1-2), and the plurality of second electrode strips (26a-26j) are laminated together to jointly form the second external electrode (14b, Paragraph [0044]).
Regarding Claim 5, Miyoshi shows the first side (left portion) and the second side (right portion) of the bottom end of the plurality of insulator layers (16b-16j) are configured as recesses (cutout, Paragraphs [0042], [0044]), and the plurality of first electrode strip layers (25a-25j) and the plurality of second electrode strip layers (26a-26j) just fill up the recesses so that the bottom surface of the laminate provided with the first external electrode (14a) and the second external electrode (14b) becomes a flat surface (see Fig. 3A).
Regarding Claim 6, Lyoo et al. shows each of the first external electrode (31’) and the second external electrode (32’) is an external electrode integrally formed on the bottom surface (bottom surface BS) of the laminate (see Fig. 2 and Drawing 1 below, Paragraph [0078]).
Miyoshi shows each of the first external electrode (14a) and the second external electrode (14b) is an external electrode integrally formed on the bottom surface of the laminate (see Figs. 1-3A).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lyoo et al. in view of Miyoshi OR Lee in view of Lyoo et al. and Miyoshi OR Lyoo et al. in view of Lee and Miyoshi as applied to claim 1 above, and further in view of Bong [KR 2013-0104035].
Regarding Claim 3, Lyoo et al. in view of Miyoshi OR Lee in view of Lyoo et al. and Miyoshi OR Lyoo et al. in view of Lee and Miyoshi shows the claimed invention as applied above but does not show the insulator layer comprises a plurality of first insulating layers and a plurality of second insulating layers, the first insulating layers are provided with the coil pattern and the conductive via holes, the second insulating layers are only provided with the conductive via holes without the coil pattern, the second insulating layers and the first insulating layers are in alternate arrangement, and adjacent layers of the coil pattern are electrically connected through the conductive via holes in the first insulating layers and the second insulating layers.
Bong shows an inductor (Fig. 3) teaching and suggesting the insulator layer comprises a plurality of first insulating layers (420, 440) and a plurality of second insulating layers (430, 453), the first insulating layers (420, 440) are provided with the coil pattern (441, 421) and the conductive via holes (441b, 421b, 441a, 421a), the second insulating layers (430, 453) are only provided with the conductive via holes (433, 453a) without the coil pattern (see Fig. 3), the second insulating layers and the first insulating layers are in alternate arrangement (see Fig. 3, elements 420, 440 and elements 430, 453 are in alternate arrangement), and adjacent layers of the coil pattern are electrically connected through the conductive via holes in the first insulating layers and the second insulating layers (see Fig. 3, adjacent layers of elements 441, 421 are electrically connected through elements 441b, 421b, 441a, 421a, 433, 453a in elements 420, 440 and elements 430, 453).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the first insulating layers are provided with the coil pattern and the conductive via holes, the second insulating layers are only provided with the conductive via holes without the coil pattern, and adjacent layers of the coil pattern are electrically connected through the conductive via holes in the first insulating layers and the second insulating layers as taught by Bong for the device as disclosed by Lyoo et al. in view of Miyoshi OR Lee in view of Lyoo et al. and Miyoshi OR Lyoo et al. in view of Lee and Miyoshi to facilitate conductivity to increase inductance (Abstract, Purpose).
Claim(s) 3-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lyoo et al. in view of Miyoshi OR Lee in view of Lyoo et al. and Miyoshi OR Lyoo et al. in view of Lee and Miyoshi as applied to claim 1, and further in view of Kido [U.S. Pub. No. 2018/0197675].
Regarding Claim 3, Lyoo et al. in view of Miyoshi OR Lee in view of Lyoo et al. and Miyoshi OR Lyoo et al. in view of Lee and Miyoshi shows the claimed invention as applied above but does not show the insulator layer comprises a plurality of first insulating layers and a plurality of second insulating layers, the first insulating layers are provided with the coil pattern and the conductive via holes, the second insulating layers are only provided with the conductive via holes without the coil pattern, the second insulating layers and the first insulating layers are in alternate arrangement, and adjacent layers of the coil pattern are electrically connected through the conductive via holes in the first insulating layers and the second insulating layers.
Kido shows the insulator layer comprises a plurality of first insulating layers (elements 11 with elements 25) and a plurality of second insulating layers (elements 11 with elements 26), the first insulating layers are provided with the coil pattern (25) and the conductive via holes (ends of elements 25), the second insulating layers are only provided with the conductive via holes (26) without the coil pattern (see Figs. 1-6), the second insulating layers and the first insulating layers are in alternate arrangement (see Figs. 1-6, elements 11 with elements 25 and elements 11 with elements 26 are in alternate arrangement), and adjacent layers of the coil pattern are electrically connected through the conductive via holes in the first insulating layers and the second insulating layers (see Figs. 1-6, adjacent layers of element 25 are electrically connected through element 26 and end of element 25 in elements 11 with elements 25 and elements 11 with elements 26).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the first insulating layers are provided with the coil pattern and the conductive via holes, the second insulating layers are only provided with the conductive via holes without the coil pattern, and adjacent layers of the coil pattern are electrically connected through the conductive via holes in the first insulating layers and the second insulating layers as taught by Kido for the device as disclosed by Lyoo et al. in view of Miyoshi OR Lee in view of Lyoo et al. and Miyoshi OR Lyoo et al. in view of Lee and Miyoshi to facilitate insulation to prevent unwanted connection and conductivity to increase inductance in order to suppress loss and improve Q value (Paragraphs [0021, [0040]).
Regarding Claim 4, Lyoo et al. in view of Miyoshi OR Lee in view of Lyoo et al. and Miyoshi OR Lyoo et al. in view of Lee and Miyoshi shows the claimed invention as applied above.
Kido shows the first external electrode (30) comprises a plurality of first electrode strips (33) which are pre-formed on a first side (left side) of a bottom end (bottom end) of the plurality of insulator layers (11), and the plurality of first electrode strips (33) are laminated together to jointly form the first external electrode (see Figs. 1-3, elements 33 are laminated together to jointly form element 30); and the second external electrode (40) comprises a plurality of second electrode strips (43) which are pre-formed on a second side (right side) of the bottom end (bottom end) of the plurality of insulator layers (11), and the plurality of second electrode strips (43) are laminated together to jointly form the second external electrode (see Figs. 1-3, elements 43 are laminated together to jointly form element 40).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the first external electrode comprises a plurality of first electrode strips which are pre-formed on a first side of a bottom end of the plurality of insulator layers, and the plurality of first electrode strips are laminated together to jointly form the first external electrode; and the second external electrode comprises a plurality of second electrode strips which are pre-formed on a second side of the bottom end of the plurality of insulator layers, and the plurality of second electrode strips are laminated together to jointly form the second external electrode as taught by Kido for the device as disclosed by Lyoo et al. in view of Miyoshi OR Lee in view of Lyoo et al. and Miyoshi OR Lyoo et al. in view of Lee and Miyoshi to form external electrodes to facilitate electrical connection to an external circuit to achieve desirable operating characteristics to improve Q value (Paragraph [0040]).
Regarding Claim 5, Kido shows the first side (left side) and the second side (right side) of the bottom end (bottom end, see Figs. 1-3) of the plurality of insulator layers (11) are configured as recesses (see Figs. 1-3, recesses are formed so elements 30, 40 can be embedded, Paragraphs [0060]-[0062]), and the plurality of first electrode strip layers (33) and the plurality of second electrode strip layers (43) just fill up the recesses (see Figs. 1-3, Paragraphs [0060]-[0062]) so that the bottom surface of the laminate provided with the first external electrode and the second external electrode becomes a flat surface (see Figs. 1-3, elements 33, 43 fill up the recesses by embedding so that the bottom surface element 17 of the laminate provided with elements 30, 40 becomes a flat surface, Paragraphs [0060]-[0062]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the bottom surface of the laminate provided with the first external electrode and the second external electrode becomes a flat surface as taught by Kido for the device as disclosed by Lyoo et al. in view of Miyoshi OR Lee in view of Lyoo et al. and Miyoshi OR Lyoo et al. in view of Lee and Miyoshi to simplified design to reduce manufacture size to reduce to decrease variations in electrical characteristics (Paragraph [0062]) in order to suppress loss and improve Q value (Paragraphs [0021, [0040]).
Regarding Claim 6, Lyoo et al. in view of Miyoshi OR Lee in view of Lyoo et al. and Miyoshi OR Lyoo et al. in view of Lee and Miyoshi shows the claimed invention as applied above.
Kido shows each of the first external electrode (30) and the second external electrode (40) is an external electrode integrally formed on the bottom surface (17) of the laminate (see Fig. 10 or Figs. 1-3, elements 30, 40 is an external electrode integrally formed on element 17 of the laminate, Paragraph [0089]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have each of the first external electrode and the second external electrode is an external electrode integrally formed on the bottom surface of the laminate as taught by Kido for the device as disclosed by Lyoo et al. in view of Miyoshi OR Lee in view of Lyoo et al. and Miyoshi OR Lyoo et al. in view of Lee and Miyoshi to have the external electrodes externally be attached and formed onto the element body which simplified design and easily be manufactured (Paragraph [0089]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lyoo et al. in view of Miyoshi OR Lee in view of Lyoo et al. and Miyoshi OR Lyoo et al. in view of Lee and Miyoshi as applied to claim 1, and further in view of Sekiguchi et al. [U.S. Pub. No. 2017/0345558].
Regarding Claim 6, Lyoo et al. in view of Miyoshi OR Lee in view of Lyoo et al. and Miyoshi OR Lyoo et al. in view of Lee and Miyoshi shows the claimed invention as applied above.
Sekiguchi et al. shows a coil component (Figs. 1-2) teaching and suggesting each of the first external electrode (302) and the second external electrode (301) is an external electrode integrally formed on the bottom surface (102) of the laminate (see Figs. 1-2, elements 302, 301 is an external electrode integrally formed on element 102 of the laminate, Paragraph [0090]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have each of the first external electrode and the second external electrode is an external electrode integrally formed on the bottom surface of the laminate as taught by Sekiguchi et al. for the device as disclosed by Lyoo et al. in view of Miyoshi OR Lee in view of Lyoo et al. and Miyoshi OR Lyoo et al. in view of Lee and Miyoshi to facilitate electrical connection to an external circuit to achieve desirable operating characteristics (Paragraph [0066]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lyoo et al. in view of Miyoshi OR Lee in view of Lyoo et al. and Miyoshi OR Lyoo et al. in view of Lee and Miyoshi as applied to claim 1, and further in view of Choi [CN 104916390].
Regarding Claim 6, Lyoo et al. in view of Miyoshi OR Lee in view of Lyoo et al. and Miyoshi OR Lyoo et al. in view of Lee and Miyoshi shows the claimed invention as applied above.
Choi shows a coil component (Figs. 1-5) teaching and suggesting each of the first external electrode (41) and the second external electrode (42) is an external electrode integrally formed on the bottom surface of the laminate (see Figs. 1-5, elements 41, 42 is an external electrode integrally formed on the bottom surface of the laminate, see English translation).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have each of the first external electrode and the second external electrode is an external electrode integrally formed on the bottom surface of the laminate as taught by Choi for the device as disclosed by Lyoo et al. in view of Miyoshi OR Lee in view of Lyoo et al. and Miyoshi OR Lyoo et al. in view of Lee and Miyoshi to prevent short by contact of metal in order to improve property about volume of the body so that degradation of an inductor capacity can be prevented (see English translation).
PNG
media_image1.png
402
612
media_image1.png
Greyscale
Drawing 1
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 3-6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZFUNG J CHAN whose telephone number is (571)270-7981. The examiner can normally be reached M-TH 8:00AM-6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shawki Ismail can be reached at (571)272-3985. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TSZFUNG J CHAN/Primary Examiner, Art Unit 2837