DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/9/25 has been entered.
Election/Restrictions
Applicant’s election without traverse to the restriction requirement mailed on 12/8/23 of Group I (claims 1-14), in the reply filed on 1/25/24 was acknowledged in a previous office action. Claims 15-20 are withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1, 3-5, and 10-14 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant) regards as the invention.
Claims 1 and 14 recite the limitations:
… an organic light-emitting diode (OLED) panel, comprising:
a substrate, and a light-emitting structure disposed on the substrate;
wherein
a plurality of film layers and a planarization layer disposed on the plurality of film layers are disposed between the substrate and the light-emitting structure,
the plurality of film layers comprising a switch transistor and a drive transistor;
wherein the OLED panel comprises a first region and a second region,
wherein
the first region is a region where a level difference of the plurality of film layers is greater than a predetermined level difference,
the second region is a region where the level difference of the plurality of film layers is less than or equal to the predetermined level difference,
the level difference of the plurality of film layers refers to a difference between a thickness of the plurality of film layers in a region and a thickness of a thinnest part of the plurality of film layers,
sources and drains of the switch transistor and the drive transistor are disposed in the first region,
a portion of a bottom gate of the drive transistor is disposed in the second region, and
the drain of the switch transistor is connected to the bottom gate of the drive transistor by a conductive plug and an interconnection layer; and
wherein the plurality of film layers comprise an interlayer dielectric layer and/or a passivation layer,
wherein:
part of a thickness of the interlayer dielectric layer in the first region is removed;
a thickness of the passivation layer in the first region is 0,
in the first region, the planarization layer is formed on a surface, away from the substrate, of the sources and drains of the switch transistor and the drive transistor,
a highest point of the passivation layer in the first region does not exceed a highest point of the sources and drains, and
the passivation layer in the second region covers the sources and drains.
The metes and bounds of the claim can not be determined for the following reasons:
The claims each require that in the first region the “level difference of the plurality of film layers is greater than a predetermined level difference” and in the second region “the level difference of the plurality of film layers is less than or equal to the predetermined level difference.” The claim does not set forth any criteria for determining what the “predetermined level difference” is, or who makes it, or when the person makes it. The claim is directed to a device, so if a device is manufactured having any specific values of the level difference of the plurality of film layers in the first and second regions, it is subjective to determine if they are higher or lower than the required “predetermined level difference.”
For example, consider a situation wherein company A holds a patent with said language therein and company B builds a device meeting all of structural limitations of the claim, wherein the device of company B has a level difference of e.g. 20 nm in the first region and a level difference of e.g. 10 nm in the second region. In this situation, there is no objective way to say that the claim language regarding the “predetermined level difference” has been met or has not been met. Company A could say that their “predetermined level difference” is 15 nm, so company B’s device infringes, whereas company B could say their “predetermined level difference” is 30 nm, so they have not infringed.
If the language of the claim is such that a person of ordinary skill in the art could not interpret the metes and bounds of the claim so as to understand how to avoid infringement, a rejection of the claim under 35 U.S.C. 112(b) should be made. MPEP 2173.02(II-III).
Claims 1 and 14 require “the level difference of the plurality of film layers refers to a difference between a thickness of the plurality of film layers in a region and a thickness of a thinnest part of the plurality of film layers”. The claim is unclear as to how to determine the level difference, in light of the specification. If one looks at Fig. 2, the plurality of film layers comprises at least ILD, PVX, gate 121, 122, channel 123, source/drain regions 124a and 124b, and the “thinnest part” of said layers could be the smallest thickness of any one of them, e.g. the thickness of PVX. However, the level difference D is shown in Fig. 2 as the distance from the top of 125b to the top of PVX, not, as the claim would require, as the thickness of ILD+PVX+125a+125b minus the thickness of the smallest part thereof, e.g. of the PVX. For these reasons, because the claim language differs from the examples shown in the specification, it is unclear how to determine the level difference.
Furthermore, because the claim allows for layers (and thus “smallest parts of the plurality of film layer” to have thicknesses of 0 (see the limitation “a thickness of the passivation layer in the first region is 0”) it is unclear if the “thickness of the smallest part” should be determined as a thickness of an existing piece of material or should be interpreted as 0.
Claims 1 and 14 are unclear because they have contradictory requirements therein. Specifically, they first require “a thickness of the passivation layer (PVX) in the first region (12a) is 0” (see e.g. Fig. 3, wherein PVX does not exist above 123 in left region 12a, so it has “a thickness… of 0”) but they also require “a highest point of the passivation layer (PVX) in the first region (12a) does not exceed a highest point of the sources (124a) and drains (124b)” (which is problematic, because PVX does not exist in region 12a, so it cannot have a “highest point”).
Claims 1 and 14 are unclear because they have contradictory requirements therein. Specifically, they first require “sources and drains of the switch transistor and the drive transistor are disposed in the first region” but they also then require “the passivation layer in the second region covers the sources and drains”, requiring the sources and regions to be in the second region.
Claims 1 and 14, overall, are unclear whether the plurality of film layers comprises an interlayer dielectric layer (ILD) and whether it comprises a passivation layer (PVX). First, the claim recites “wherein the plurality of film layers comprise an interlayer dielectric layer ILD and/or a passivation layer PVX”. The claims subsequently refer to “a thickness of the ILD layer”, and “a highest point of the passivation layer”, which would imply the existence of both the ILD and PVX. However, the claim also recites the limitation “a thickness of the passivation layer in the first region is 0”, thus allowing for the existence of a “layer” where no such layer actually exists.
Claims 3-5 and 10-13 depend from claim 1 and inherit its deficiencies.
Claim Interpretation
The applicant is hereby notified that the examiner is treating claims 1, 3-5, and 10-14 as "product-by-process” claims. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” (See In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), and also see MPEP 2113).
The structure implied by the process steps should be considered when assessing the patentability of product-by-process claims over the prior art, especially where the product can only be defined by the process steps by which the product is made, or where the manufacturing process steps would be expected to impart distinctive structural characteristics to the final product. (See, e.g., In re Garnero, 412 F.2d 276, 279, 162 USPQ 221, 223 (CCPA 1979) and also see MPEP 2113).
Claims 1 and 14 are directed to devices. They each claim a limitation “wherein part of a thickness of the interlayer dielectric layer in the first region is removed”. The limitation is the result of a process of manufacturing (“removing”). It is first noted that the claims do not require the interlayer dielectric to be in the device, because the claims require a limitation “the plurality of film layers comprise an interlayer dielectric layer and/or a passivation layer”, making the interlayer dielectric layer optional. In the event that the interlayer dielectric layer must be in the device, because the plurality of film layers do not include a passivation layer, the limitation results in no distinctive characteristics of the device, because the claim does not otherwise describe what geometry or dimensions the interlayer dielectric must have. A process of “removal” results in a interlayer dielectric film of some thickness, having some geometry, but it may be of any desired thickness or geometry (e.g. it could result in a uniform thickness, or it could result in non-uniform thicknesses). The initial layer (i.e. the layer before it is subject to “removal”) could be formed in any shape, as it has not been limited, and the final layer (i.e. after the “removing”) could be any shape or dimensions, as it has not been limited.
Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. (See In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)).
Also note the use of 102/103 rejections for product-by-process claims has been approved by the courts. (See In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972), and also see MPEP 2113).
Response to Arguments
Applicant's arguments with respect to the pending claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896