DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse to the restriction requirement mailed on 12/8/23 of Group I (claim 1-14), in the reply filed on 1/25/24 was acknowledged in a previous office action. Claims 15-20 are withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), first paragraph:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 1, 3-5, and 10-14 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter (i.e. “new matter") which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
In the following, the Office has added some formatting herein to make the discussion easier. Specifically:
letter A was added to denote the limitation “the OLED panel comprises a first region and a second region”,
numbers 1-5 were added to denote further limitations regarding limitation A,
letter B was added to denote the limitation “wherein the plurality of film layers comprise an interlayer dielectric layer and/or a passivation layer”, and
lower case roman numerals i-iv were added to denote further limitations regarding limitation B.
Claim 1 recites:
an organic light-emitting diode (OLED) panel, comprising:
a substrate, and a light-emitting structure disposed on the substrate;
wherein a plurality of film layers and a planarization layer disposed on the plurality of film layers are disposed between the substrate and the light-emitting structure, the plurality of film layers comprising a switch transistor and a drive transistor;
A. wherein the OLED panel comprises a first region and a second region,
wherein
a level difference of the plurality of film layers in the first region is greater than a level difference of the plurality of film layers in the second region,
the level difference of the plurality of film layers refers to a difference between a maximum total thickness and a minimum total thickness of the plurality of film layers in a region,
portions of sources and drains of the switch transistor and the drive transistor are disposed in the first region,
a portion of a bottom gate of the drive transistor is disposed in the second region, and
the drain of the switch transistor is connected to the bottom gate of the drive transistor by a conductive plug and an interconnection layer; and
B. wherein the plurality of film layers comprise an interlayer dielectric layer and/or a passivation layer, wherein:
part of a thickness of the interlayer dielectric layer in the first region is removed;
a thickness of the passivation layer in the first region is 0,
in the first region, the planarization layer is formed on a surface, away from the substrate, of the sources and drains of the switch transistor and the drive transistor, and
the passivation layer in the second region covers other portions of the sources and drains.
Claim 14 recites the same as claim 1, except limitation B recites “wherein the plurality of film layers comprise an interlayer dielectric layer a passivation layer”.
Claims 1 and 14 have been expanded significantly by amendment since the first form thereof, filed on 6/20/21. The originally-filed claims do not contain support for the entirety of the current version of claims 1 or 14, as they are much broader than the current version. The originally-filed specification also does not contain support for the entirety of the current version of claims 1 or 14.
The reasons for this conclusion are myriad. Some examples follow:
First, limitation 2 (“the level difference of the plurality of film layers refers to a difference between a maximum total thickness and a minimum total thickness of the plurality of film layers in a region”) differs significantly from what was described in the specification: see e.g. para [0071]: “The level difference of a certain film layer structure in a certain region may refer to a thickness difference between the region and the thinnest part of the film layer structure. For example, the level difference of a certain film structure in region A may refer to a difference between the thickness of the film structure in region A and the thickness of the thinnest part of the film.” Limitation 2 defines the level difference by using, in part, a minimum thickness only in the region, whereas para 0071 defines it by using, in part, a thinnest part of the film layer structure (i.e. anywhere; i.e. without referring only to thinnest part only in the region).
Due to this change, limitations 1 and 2 are not supported by the originally filed specification.
Second, limitation A requires “the OLED panel comprises a first region and a second region”, thus requiring a single first region and a single second region, limited by at least limitations 1-5 and limitations i-iv. However, the specification as originally filed does not support a single first region and a single second region meeting all of the requirements of limitation 1-5 and limitation i-iv. Rather, it uses a symbol 12a to denote “a first region” and symbol 12b to denote “a second region”, but as is clear from Figs. 2-3 there are parts of 12b both to the right and left of 12a in cross-section A-A, and there are parts of 12b both to the right and left of 12a in cross-section B-B, and in Fig. 1 we can see that cross-sections A-A and B-B are parallel to each other in a top view of the device. Thus, it is not possible that 12a in cross-section AA is coupled to 12a in cross-section B-B. Thus, there are at least two different “first regions” in the disclosure. Limitation 3 requires “portions of sources and drains of the switch transistor and the drive transistor are disposed in the first region”. The claim thus requires portions of both the source and drain regions of both the switch and drive transistor to be in a single “first region”, which is not supported by the originally-filed specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1, 3-5, and 10-14 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant) regards as the invention.
Claims 1 and 14 were both repeated above. The metes and bounds of the claims can not be determined for the following reasons:
First, claims 1 and 14, overall, are unclear as to the number (and possibly geometry, such as interconnectedness between various regions) of the first region(s) and of the second region(s). In Figs. 1-3, it is logical to conclude that the region 12a of each transistor is surrounded by 12b, and thus at a minimum, there are many “first regions” 12a, corresponding with the number of transistors in the array on the chip. However, the claims recite a single first region and a single second region, and make many requirements of the claim in these regions. In a real OLED panel, having millions of pixels and thus millions of transistors therein, there are variations in parameters such as thicknesses of layers. It thus becomes unclear if limitation 1, limitation i, limitation ii, and limitation iii need to be evaluated against only a single one of the various first regions in the OLED panel, or if they need to be evalutated against the totality of the first regions. For example, if the layers of one transistor have a variation that makes its upper surface 0.5 nm higher than the upper surface in another transistor, which of those should be evaluated in limitation 1? If a part of the thickness of the interlayer dielectric layer in one of these transistor’s first regions is “removed” but in another of the transistor’s first regions is not “removed”, it is unclear if limitation i has been met.
Second, limitation 2 (“the level difference of the plurality of film layers refers to a difference between a maximum total thickness and a minimum total thickness of the plurality of film layers in a region”) in claims 1 and 14 is unclear because it is grammatically unclear if “in a region” refers to A) the “maximum total thickness”, or to B) the “minimum total thickness”, or to C) both the “maximum total thickness” and to the “minimum total thickness”, and furthermore, as noted above, limitation 2 differs from the teachings of the specification (see e.g. para 71).
Third, in claim 14, limitation B (“wherein the plurality of film layers comprise an interlayer dielectric layer a passivation layer”) is unclear because it is not clear if the plurality of thin film layers is required to comprise A) an interlayer dielectric layer and a passivation layer or B) an interlayer dielectric layer or a passivation layer. Because limitations i-iv further limit B) while sometimes referring to the interlayer dielectric layer and other times referring to the passivation layer, it is unclear overall which of limitations i-iv need not be met in devices having an ILD layer but not having a passivation layer; and in devices having a passivation layer but not having an ILD layer.
Fourth, claims 1 and 14, overall, are unclear whether the plurality of film layers comprises an interlayer dielectric layer (ILD) and whether it comprises a passivation layer (PVX). On one hand, the claim recites “wherein the plurality of film layers comprise an interlayer dielectric layer ILD and/or a passivation layer PVX”. The claims subsequently refer to “a thickness of the ILD layer” and to “a thickness of the passivation layer” which would imply the existence of both the ILD and PVX. However, the claim also recites the limitation “a thickness of the passivation layer in the first region is 0”, thus allowing for the existence of a “layer” where no such layer actually exists. The limitation allowing for a thickness of a layer to be zero makes it unclear whether the interlayer dielectric layer or the passivation layer need to even be present in a device to read on the claims, since the claims allow for the layer to exist with zero thickness.
Claims 3-5 and 10-13 depend from claim 1 and inherit its deficiencies.
Claim Interpretation
The applicant is hereby notified that the examiner is treating claims 1, 3-5, and 10-14 as "product-by-process” claims. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” (See In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), and also see MPEP 2113).
The structure implied by the process steps should be considered when assessing the patentability of product-by-process claims over the prior art, especially where the product can only be defined by the process steps by which the product is made, or where the manufacturing process steps would be expected to impart distinctive structural characteristics to the final product. (See, e.g., In re Garnero, 412 F.2d 276, 279, 162 USPQ 221, 223 (CCPA 1979) and also see MPEP 2113).
Claims 1 and 14 are directed to devices. They each claim a limitation “wherein part of a thickness of the interlayer dielectric layer in the first region is removed”. The limitation is the result of a process of manufacturing (“removing”). It is first noted that the claims do not require the interlayer dielectric to be in the device, because the claims require a limitation “the plurality of film layers comprise an interlayer dielectric layer and/or a passivation layer”, making the interlayer dielectric layer optional. In the event that the interlayer dielectric layer must be in the device, because the plurality of film layers do not include a passivation layer, the limitation results in no distinctive characteristics of the device, because the claim does not otherwise describe what geometry or dimensions the interlayer dielectric must have. A process of “removal” results in a interlayer dielectric film of some thickness, having some geometry, but it may be of any desired thickness or geometry (e.g. it could result in a uniform thickness, or it could result in non-uniform thicknesses). The initial layer (i.e. the layer before it is subject to “removal”) could be formed in any shape, as it has not been limited, and the final layer (i.e. after the “removing”) could be any shape or dimensions, as it has not been limited.
Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. (See In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)).
Also note the use of 102/103 rejections for product-by-process claims has been approved by the courts. (See In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972), and also see MPEP 2113).
Response to Arguments
Applicant's arguments with respect to the pending claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Conclusion / Finality
Applicant's amendment changed the scope of the claims and necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896
Prosecution Insights