Prosecution Insights
Last updated: July 17, 2026
Application No. 17/419,689

METHOD FOR METROLOGY OPTIMIZATION FOR LITHOGRAPHIC SYSTEMS

Non-Final OA §103§112
Filed
Jun 29, 2021
Priority
Dec 31, 2018 — provisional 62/787,204 +1 more
Examiner
KIM, EUNHEE
Art Unit
2188
Tech Center
2100 — Computer Architecture & Software
Assignee
ASML Holding N.V.
OA Round
7 (Non-Final)
78%
Grant Probability
Favorable
7-8
OA Rounds
0m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
578 granted / 742 resolved
+22.9% vs TC avg
Moderate +11% lift
Without
With
+10.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
34 currently pending
Career history
776
Total Applications
across all art units

Statute-Specific Performance

§101
12.5%
-27.5% vs TC avg
§103
67.6%
+27.6% vs TC avg
§102
8.7%
-31.3% vs TC avg
§112
8.3%
-31.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 742 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION 1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/29/2026 has been entered. 2. The amendment filed 04/29/2026 has been received and considered. Claims 6, 9-10, 13-14, and 16-17 are presented for examination. Claim Objections 3. Claims 6, 9 and 13 are objected to because of the following informalities: As per Claim 6, it recites the limitation “by a sensor in a metrology apparatus,” in line 3 which would be better as “by a sensor in the metrology apparatus,”. As per Claim 9, it recites the limitation “determining a distance” between a single parameter value (“the parameter of the semiconductor process”) and a “statistical representation” of a set does not, on its face, identify the metric or the quantities compared. It is recommended applicants confirm a definite metric is conveyed, or amend to recite it. As per Claim 13, it recites the limitation “measuring a structure on a substrate using the metrology recipe.” Claim 6 already recites “a substrate” (collecting step) and “another substrate” (generating step). The limitation “a substrate” in claim 13 is ambiguous as to which substrate is intended; thus, it would be better as “the other substrate” or “a further substrate”. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 4. Claims 6, 9-10, 13-14, and 16-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As per Claim 6, it recites the model is “specific to different regions of the substrate based on target clusters distributed at different wafer location,”; and, claim 17 recites “the different wafer locations include edge regions and center regions”. The metes and bounds are unclear because the claim uses three overlapping spatial concepts which are “regions of the substrate,” “wafer locations,” and “edge regions and center regions” without making clear whether “edge/center regions” define the regions of the substrate, the wafer locations, or the target clusters. It is indefinite what the model is “specific to”. Further Claim 6 recites the limitation: collecting, by a sensor in a metrology apparatus, optical measurements from light diffracted from a plurality of targets positioned on a substrate, wherein at least two targets in the plurality of targets are designed with predetermined different duty cycles; augmenting, by one or more computer systems, a set of measurements used to create a lithography system metrology process model with the optical measurements from light reflected or diffracted from the plurality of targets to create an updated dataset”. The collecting step recites “optical measurements from light diffracted from a plurality of targets”, but the augmenting step augments the dataset “with the optical measurements from light reflected or diffracted from the plurality of targets”. The “reflected” alternative has no antecedent in the collected measurements, leaving it unclear whether the augmenting step uses the previously collected (diffracted) measurements or a broader (reflected-or-diffracted) set. Claim 6 recites “a plurality of targets,” then later “target clusters distributed at different wafer location.” The claim does not establish whether the “target clusters” are groupings of the previously recited “plurality of targets” or separately introduced structures, leaving the antecedent relationship unclear. Also Claim 6 recites targets “positioned on a substrate” and a model “specific to different regions of the substrate,” then immediately switches to “target clusters distributed at different wafer location”; claim 17 likewise recites “the different wafer location”. The claim thus uses two different terms which are “substrate” and “wafer” without stating whether they denote the same element, leaving the metes and bounds unclear As per Claim 9, it recites “a statistical representation of the set of optical measurements.” Claim 6 introduces several optical-measurement sets for example the “optical measurements from light diffracted” (collecting step), the augmenting “optical measurements,” and “a set of corresponding optical measurements measured on the set of devices and/or targets.” It is therefore unclear which set “the set of optical measurements” refers. Notably, the specification describes a distance against “a statistical representation of the set of measurements used to create a model of a metrology process” (paragraph [0009] of PG PUB), not “the set of optical measurements,” underscoring the ambiguity. As per Claim 14, it introduces “a set of optical measurements” and “a set of SEM measurements,” then recites the limitation “the set of SEM measurements and the set of optical measurements are measured on the same devices and/or targets.” Parent independent claim 6 already recites “a set of … (SEM) measurements” and “a set of corresponding optical measurements.” It is unclear whether claim 14’s sets are the same as, or different from, the parent’s sets. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 5. Claims 6, 9, 10, 13, 14, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over David (US 10734293 B2), further in view of Pandev et al. (US 20180252514 A1) and further in view of Pandev '055 (US 9721055 B2). As per Claim 6, David teaches a method for calibrating a metrology apparatus in a lithography system (Fig. 11), comprising: collecting, by a sensor in a metrology apparatus (Fig. 11 element 1102 -> 1106; Col. 7 lines 38-49, “sensor arrangement”, Col. 11 lines 19-36), optical measurements from light diffracted from a target positioned on a substrate (Col. 6 lines 5-7, “metrology data can be collected during etch processes. Optical emissions spectra or spectral data from photoluminescence can be utilized as input data.” Col. 7 lines 64-67, Col. 8 lines 1-5, “For DBO, a first diffraction grating pattern is located on the pattern layer, and a second diffraction grating pattern with identical pitch is located in the resist layer. The second grating should be nominally on top of the first grating, and by measuring the intensity of the diffraction patterns, an overlay measurement may be obtained. If there is an overlay error between the two gratings, it will be detectable in the diffraction pattern”; Col. 9 lines 54-67 “In step 604, the parameters that are useful in evaluating the target are identified, and in step 606, input data relevant to the parameters is collected. Every set of input data is associated with a specific output or target. For example, a set of measured and observed values can be associated with an overlay offset. Those values would be an input vector to the model, and would be associated with the target, e.g., the measured offset. If there are n input variables, then the input vector size for each target would be 1×n. Therefore, if there are m targets, there will be an input data matrix of size m×n, with each row of the input data matrix associated with a target.”; Col. 10 lines 21-40 “overlay measurement (e.g., IBO measurement, DBO measurement, CD-SEM, TEM, etc.)”; Col. 11 lines 40-50, Col. 22 lines 10-34, “These input parameters can include metrology measurements from process steps or metrology measurements collected during the wafer fabrication process. These measurements can include optical reflectomety or ellipsometry data, and the intensity of each measurement at a given wavelength. The metrology data can be incorporated from a reflectometry measurement taken after a certain processing step (for example, CMP or Etch, or Gap Fill processes).”, Fig. 3B & 5B),…; augmenting, by one or more computer systems (Col. 28 lines 24-28), a set of measurements used to create a lithography system metrology process model with the optical measurements from light reflected or diffracted from the plurality of targets to create an updated dataset (Fig. 11 element 1108 -> 1114; Col. 18 lines 1-15 and lines 43-67, Col. 19 lines 1-8, “From the original input data, a set of virtual metrology models may be constructed.”, “The model will continue to be re-trained at user-defined intervals (for example, once a week) as new data is made available. To retrain the model, the entire dataset available may be used.”; col. 26 lines 8-27, “a second set of the real-time inputs”; Col. 26 lines 29-35, “additional real-time inputs from processes”), wherein the set of measurements used to create the lithography system metrology process model contains a set of scanning electron microscopy (SEM) measurements measured on a set of devices and/or targets and a set of corresponding optical measurements measured on the set of devices and/or targets (Col. 10 lines 21-40 “overlay measurement (e.g., IBO measurement, DBO measurement, CD-SEM, TEM, etc.)”, Col. 15 lines 50-67, Col. 16 lines 1- 6 “ CD measurements… parameters of other overlay measurements such as DBO and IBO… are used as inputs to the training model”; col. 26 lines 8-27, “a first set of the real-time inputs”); retraining, by the one or more computer systems (Col. 28 lines 24-28), a lithography system metrology process model configured to map optical measurements to SEM measurements using the updated dataset to create an updated lithography system metrology process model (Fig. 8 element 802-> 804; Col. 13 lines 19-20 “As new input data and corresponding target data is generated, the algorithm can be retrained ”; Col. 10 lines 1- 60 “Every set of input data is associated with a specific output or target.”; Col. 13 lines 19-20 “As new input data and corresponding target data is generated, the algorithm can be retrained ”; Col. 14 lines 48-50 “as new input data and corresponding target data is generated, the algorithm can be retrained”; Col. 18 lines 43-67, Col. 19 lines 1-8, “The model will continue to be re-trained at user-defined intervals (for example, once a week) as new data is made available. To retrain the model, the entire dataset available may be used.” Table I & II; Col. 22 lines 18-67, Col. 23 lines 1-3. “In step 1108, the input data undergoes filtering, normalization and/or cleansing steps. In step 1110, dimensionality reduction or feature selection is performed to reduce the number of input parameters for processing the algorithm. In step 1112, the data is then fed into one or more algorithms for training. Given the training input data and training targets, the algorithm(s) will produce a model in step 1114, which can be deployed in step 1116 to act on real time data”),.... David fails to teach explicitly a plurality of targets positioned on a substrate, wherein at least two targets in the plurality of targets are designed with predetermined different duty cycles; wherein the updated lithography system metrology process model is specific to different regions of the substrate based on target clusters distributed at different wafer locations; generating, by the one or more computer systems, a metrology recipe for measuring a property of another target on another substrate during a lithography manufacturing processing by inputting optical measurements into the updated lithography system metrology process model. Pandev et al. teaches a plurality of targets positioned on a substrate, wherein at least two targets in the plurality of targets are designed with predetermined different duty cycles ([0064] "each of a plurality of overlay metrology targets are illuminated"; [0072]-[0073] " the DOE wafer set includes a large range of programmed values of critical dimension (CD) of a bottom grating structure. The bottom grating structure is repeatedly fabricated with different lithography dosage values ": Pandev et al. teaches a plurality of metrology targets fabricated with a programmed range of critical dimension values at a common pitch (corresponding to the limitation "predetermined different duty cycles" as claimed), such that the line-to-pitch ratio differs from target to target because duty cycle is the ratio of critical dimension to pitch), and generating, by the one or more computer systems, a metrology recipe for measuring a property of another target on another substrate during a lithography manufacturing processing by inputting optical measurements into the updated lithography system metrology process model ([0029] “In another aspect, a trained measurement model is employed as the measurement model for measurement of other targets having unknown overlay values.”, [0030] “the scatterometry-based measurement techniques described herein may be applied to the measurement of other process, structure, dispersion parameters, or any combination of these parameters. By way of non-limiting example, profile geometry parameters (e.g., critical dimension), process parameters (e.g., focus, and dose), dispersion parameters, pitch walk, or any combination of parameters may be measured. A set of training targets with programmed variations for each parameter of interest must be provided. The measurement model is then trained based on scatterometry data collected over measurement sites that include the range of programmed variations of each parameter of interest.”, [0033] “measurements performed at multiple illumination wavelengths, polarizations, etc., are employed to train a measurement model and perform measurements using the trained measurement model”, [0035] “In another aspect, the measurement model results described herein can be used to provide active feedback to a process tool (e.g., lithography tool, etch tool, deposition tool, etc.). For example, values of overlay error determined using the methods described herein can be communicated to a lithography tool to adjust the lithography system to achieve a desired output. In a similar way etch parameters (e.g., etch time, diffusivity, etc.) or deposition parameters (e.g., time, concentration, etc.) may be included in a measurement model to provide active feedback to etch tools or deposition tools, respectively.”, [0064] “In block 201, each of a plurality of overlay metrology targets are illuminated with illumination light generated by an optical illumination source (e.g., illuminator 101) of a scatterometry based overlay metrology system.”, [0076] “trained measurement model is robust to measurement system variations (e.g., optical system variations).” [0112] “In another aspect, the trained model is employed as the measurement model for measurement of other targets having unknown overlay values.”, [0121] “a measurement model trained in the manner described herein is usable to estimate values of overlay and additional parameters such as critical dimension, edge placement errors, lithography focus, lithography dosage, and other shape and film parameters of interest.” [0139] “the measurement model results described herein can be used to provide active feedback to a process tool (e.g., lithography tool, etch tool, deposition tool, etc.) …values of overlay error determined using the methods described herein can be communicated to a lithography tool to adjust the lithography system to achieve a desired output. In a similar way etch parameters (e.g., etch time, diffusivity, etc.) or deposition parameters (e.g., time, concentration, etc.) may be included in a measurement model to provide active feedback to etch tools or deposition tools, respectively.”; [0134] “the metrology system employed to perform overlay measurements as described herein (e.g., metrology system 300) includes an infrared optical measurement system.”; [0140] “a measurement model for off-line or on-tool measurement. In addition, both measurement models and any reparameterized measurement model may describe one or more target structures and measurement sites.”.). Further Pandev '055 teaches wherein the updated lithography system metrology process model is specific to different regions of the substrate based on target clusters distributed at different wafer locations (Col. 2 lines 33-49 “The cross-wafer model characterizes a specimen parameter value as a function of location on the wafer”; Col. 7 lines 62-67, Col. 8 lines 1-14). In particular, Pandev '055 teaches a cross-wafer model that characterizes the modeled parameter as a function of location on the wafer (corresponding to the limitation "specific to different regions of the substrate" as claimed) and links groups of measurement sites at common wafer locations (corresponding to the limitation "target clusters distributed at different wafer locations" as claimed). David, Pandev et al. and Pandev '055 are analogous art because they are all related to a method for calibrating a metrology apparatus in a lithography system, It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. Thus, one of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate Pandev et al. and Pandev '055 into David’s invention to provide an improved measurement system which achieves accurate measurements and sufficiently accurate tool matching (Pandev et al.: Abstract, [0002], [0020]) and to improve the accuracy of the model (Pandev '055: col 2 lines 54-30 ) As per Claim 9, David teaches further comprising: measuring a parameter of a semiconductor process (Col. 18 lines 27-55 “Once a model or multi-step model and associated parameters are chosen…”. “the predicted error”); and determining a distance between the parameter of the semiconductor process and a statistical representation of the set of optical measurements (Col. 7 lines 39-48 “overlay measurement using an optical inspection system”; Col. 18 lines 27-55 “the defined limits”, “the specified error limit (predicted—actual overlay) for a user-specified period of time (for example, 8 weeks of production), then the model is allowed to replace some of the actual overlay measurements used in actual production.”). As per Claim 10, David teaches wherein the retraining preserves the set of measurements used to create the lithography system metrology process model (Col.18 lines 43-67, Col. 19 lines 1-23. “If instead the model is not predicting within the defined limits as compared to actual measured overlay error, then all data collected up to that point is used to retrain the model as outlined in the above steps…To retrain the model, the entire dataset available may be used.”, “The model will continue to be re-trained at user-defined intervals (for example, once a week) as new data is made available. To retrain the model, the entire dataset available may be used.”). As per Claim 13, David teaches further comprising measuring a structure on a substrate using the metrology recipe (Col. 7 lines 38-48, “overlay measurement module typically performs the overlay measurement using an optical inspection system. The position of the mask pattern in the resist layer relative to the position of the pattern on the substrate is determined by measuring an optical response from an optical marker on the substrate which is illuminated by an optical source.”; Col. 25 lines 9-30, “process equipment using process equipment data and in-situ metrology,”; Col. 26 lines 24-27, “adjusting the lithography process or the upstream process such that the prediction of the targeted overlay measurement correlates with an actual targeted overlay measurement.”). As per Claim 14, David teaches, further comprising: mapping, by the one or more computer systems, a set of optical measurements to a set of SEM measurements using a regression algorithm to create the lithography system metrology process model (Col. 10 lines 1- 60 “Every set of input data is associated with a specific output or target.”; Col. 14 lines 1-6 “ regression algorithms”; Col. 18 lines 43-67, Col. 19 lines 1-8, “The model will continue to be re-trained at user-defined intervals (for example, once a week) as new data is made available. To retrain the model, the entire dataset available may be used.” Table I & II; Col. 22 lines 18-67, Col. 23 lines 1-3. “In step 1108, the input data undergoes filtering, normalization and/or cleansing steps. In step 1110, dimensionality reduction or feature selection is performed to reduce the number of input parameters for processing the algorithm. In step 1112, the data is then fed into one or more algorithms for training. Given the training input data and training targets, the algorithm(s) will produce a model in step 1114, which can be deployed in step 1116 to act on real time data”), wherein the set of SEM measurements and the set of optical measurements are measured on the same devices and/or targets (Col. 15 lines 50-67, Col. 15 lines 1-30, “the target as the delta between the DBO measurement and CD-SEM measurement. The error associated between DBO and CD- SEM or TEM can be attributed to an input dataset and corrected in production.”; Col. 22 lines 18-32, “the input data to the algorithm can be input data from any or all processes performed during wafer fabrication…. These input parameters can include metrology measurements from process steps or metrology measurements collected during the wafer fabrication process.”). As per claim 16, David fails to teach explicitly wherein the metrology recipe includes selection of at least one of: polarization, wavelength, apertures, and wafer rotation. Pandev et al. teaches wherein the metrology recipe includes selection of at least one of: polarization, wavelength, apertures, and wafer rotation ([0014], [0055]- [0056] “wavelength selection device 102 is controlled by computing system 130. In these embodiments, computing system 130 is configured to communicate control commands indicative of a desired wavelength or range of wavelengths to wavelength selection device 102. In response, wavelength selection device 102 selectively passes the desired wavelengths or ranges of wavelengths… polarization control device 104 is controlled by computing system 130. In these embodiments, computing system 130 is configured to communicate control commands indicative of a desired polarization to polarization control device 104. In response, polarization control device 104 selectively polarizes the illumination light to achieve the desired polarization state”, “system 100 may include one or more computing systems 130 employed to perform overlay measurements based on trained measurement models”; [0060] “a measurement model or an overlay parameter 121 determined by computer system 130 may be communicated and stored in an external memory. In this regard, measurement results may be exported to another system.”). As per Claim 17, David fails to teach explicitly wherein the different wafer location include edge regions and center regions. Pandev '055 teaches wherein the different wafer location include edge regions and center regions (Col. 2 lines 33-39 "radially symmetric thin film thickness patterns with a U or W shape"; Col. 8 lines 53-62 "for measurements of any combination of sites located at the same distance from the center of the wafer"). Response to Arguments 6. Applicant's arguments filed 04/29/2026 have been fully considered but they are not persuasive. As per the applicant’s argument regarding “A. David in view of Pandev fails to teach or suggest "a plurality of targets positioned on a substrate" as claimed”: The argument conflates cells-per-target with number-of-targets. Pandev et al.'s single-cell discussion concerns the number of cells within an individual target (“metrology target 140 is a single cell target having sensitivity in two orthogonal directions. By collecting signals from one cell instead of four, a significant reduction in move-acquire-measure (MAM) time is achieved.” paragraph [0108]: one cell instead of four to reduce MAM time), not the number of targets on the substrate. The claim recites “a plurality of targets positioned on a substrate,” which is a separate concept from how many cells each target contains. Pandev et al. (US 20180252514 A1) expressly discloses a plurality of targets. In particular, Pandev et al. recites that “each of a plurality of overlay metrology targets are illuminated” ([0064]), and fabricates and measures a DOE set of many targets across the wafer with programmed variations ([0073]). As per the applicant’s argument regarding “B. David in view of Pandev fails to teach or suggest "wherein at least two targets in the plurality of targets are designed with predetermined different duty cycles" as claimed”: The argument is directed to a basis the rejection does not use. The rejection relies on Pandev et al. of paragraph [0073] where it states: “the DOE wafer set includes a large range of programmed values of critical dimension (CD) of a bottom grating structure” the structure being “repeatedly fabricated with different lithography dosage values” (see Office Action, claim 6, element [6.a] teaching paragraph). Furthermore, applicant defines duty cycle as “the ratio of line width to pitch” (Remarks p. 7, citing Spec. paragraph [0082]). Line width is the critical dimension (CD), as the Office noted in the Advisory Action (“duty cycle is the ratio of line width (CD) to pitch,”. Under that definition, targets fabricated with a programmed range of CD values have different line-width-to-pitch ratios that is different duty cycles. At least two such targets are therefore “designed with predetermined different duty cycles” as claimed, and the CD values are programmed (i.e., designed in advance) into the DOE targets ([0073] “programmed values of critical dimension”). As per the applicant’s argument regarding “C. David in view of Pandev fails to teach or suggest "wherein the updated lithography system metrology process model is specific to different regions of the substrate based on target clusters distributed at different wafer locations" as claimed”: Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument – in view of Pandev '055 (US 9721055 B2). In particular, Pandev '055 teaches a cross-wafer model that characterizes the modeled parameter as a function of location on the wafer (corresponding to the limitation "specific to different regions of the substrate" as claimed) and links groups of measurement sites at common wafer locations (corresponding to the limitation "target clusters distributed at different wafer locations" as claimed). See Col. 2 lines 33-49 where it states “The cross-wafer model characterizes a specimen parameter value as a function of location on the wafer” and Col. 7 lines 62-67, Col. 8 lines 1-14). For the foregoing reasons, Arguments are not persuasive, and the rejection under 35 U.S.C. 103 is maintained as set forth in the Office Action. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUNHEE KIM whose telephone number is (571)272-2164. The examiner can normally be reached Monday-Friday 9am-5pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ryan Pitaro can be reached at (571)272-4071. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. EUNHEE KIM Primary Examiner Art Unit 2188 /EUNHEE KIM/Primary Examiner, Art Unit 2188
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Prosecution Timeline

Show 14 earlier events
Oct 03, 2025
Response after Non-Final Action
Oct 27, 2025
Non-Final Rejection mailed — §103, §112
Dec 17, 2025
Response Filed
Feb 11, 2026
Final Rejection mailed — §103, §112
Apr 01, 2026
Response after Non-Final Action
Apr 29, 2026
Request for Continued Examination
May 01, 2026
Response after Non-Final Action
Jun 05, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

7-8
Expected OA Rounds
78%
Grant Probability
89%
With Interview (+10.7%)
3y 4m (~0m remaining)
Median Time to Grant
High
PTA Risk
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