Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Govindarajan (US 20060151822 A1) in view of Tran et al. (US 20130161792 A1).
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CLAIM 1. Govindarajan discloses a semiconductor structure, comprising:
a substrate 14 comprising a trench (Fig. 3) extending along a direction of the substrate;
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wherein the substrate further comprises a first -type doped region (N-type – 14 & fig. 8) and a second-type doped region (P-type Figs. 1,2)located above the first-type doped region (Figs. 1 & 2 – Note: Fig. 8 only depicts the trench structure, it is understood to be used accordingly with the transistors/substrate as shown in Figs. 1&2.);
a capacitor fabricated in the trench (Fig. 8), wherein the capacitor comprises a lower electrode 40 provided on an inner wall of the trench, a dielectric combination layer 20 (¶32)1 provided on the lower electrode 40, and an upper electrode 44/46 provided on the dielectric combination layer 20: wherein the dielectric combination layer comprises a stacked structure composed of a nitride layer and an oxide layer, the lower electrode is a conductive material, and the first-type doped region is a silicon substrate doped with N-type ions. (Fig. 1, 2, 5 & 8 & ¶32).
While Govendarahan may not explicitly list N-type polysilicon for conductive layer 40, such omission does not teach away from its use, as N-type polysilicon was a well-known functional alternative for trench capacitor electrodes at the time of the invention. Tran et al. confirm this conventional understanding by disclosing that trench electrodes can be formed from 'a conductive material (e.g., a TiN material, doped polysilicon, or the like)' [¶0021]. Given this, selecting doped polysilicon—a standard material—in place of the materials listed in Govendarahan (e.g., Ti, TiN) would have been obvious to a Person Having Ordinary Skill in the Art (PHOSITA). It is well-established that selecting a known material based on its suitability for an intended use is within the general skill of a worker in the art. In re Leshin, 125 USPQ 416 (CCPA 1960).
CLAIM 2. Govindarajan discloses a semiconductor structure of claim 1, wherein the trench passes through the second-type doping region (Fig. 2 – p-type region – upper/surface region of substrate) and extends to the first-type doped region (Fig. 2 – n-type region – lower region), and wherein the lower electrode is disposed on the inner wall of the trench in the first-type doped region (Fig. 2 – ¶21).
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CLAIM 3. Govindarajan discloses a semiconductor structure of claim 2, wherein the dielectric combination layer is disposed in the trench in the first-type doped region (Figs. 2, 3 & 5).
CLAIM 4. Govindarajan discloses a semiconductor structure of claim 1, further comprising a capacitor contact structure 30/48 formed above the upper electrode and electrically connected to the upper electrode (Figs. 2 & 8 - ¶70)2.
CLAIM 5. Govindarajan discloses a semiconductor structure of claim 4, further comprising an isolation structure 32 formed above the lower electrode, wherein the isolation structure is disposed on a top surface of a side wall of the lower electrode, for isolating the lower electrode from the capacitor contact structure (Figs. 2 & 8 - ¶22& 70)3.
CLAIM 6. Govindarajan discloses a semiconductor structure of claim 1, wherein the oxide layer comprises one or more of ZrO2, Ta2O5, Al2O3, TiO2, and HfO2 (¶33-39)4.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
2/24/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 [0032] “Referring now to FIG. 5, dielectric 20 is deposited over the layer 40. A wide variety of dielectrics can be used. For example, dielectric 20 can be an oxide (e.g., silicon dioxide) or a nitride (such as silicon nitride, e.g., Si.sub.3N.sub.4). Combinations of oxides and nitrides can also be used. For example, dielectric 20 can be silicon oxynitride (SiON) or a composite layer such as an oxide-nitride-oxide (ONO) layer. With silicon oxide, silicon nitride, and combinations thereof, the preferred physical thickness of dielectric 20 is between about 1 nm and 10 nm, preferably about 3 nm, depending on the dielectric constant of the layer.”
2 “[0070] After collar 32 is etched back, the buried strap 30 is completed by deposition of a conductive material, such as doped polysilicon. In the preferred embodiment, the polysilicon regions 30,48 and 46 are all doped with arsenic, although it is understood that other dopants (e.g., phosphorus) could be used. Further, any or all of the materials for regions 30, 48 and 46 can be a conductive material other than polysilicon (e.g., a metal).”
3 “[0022] As shown in the schematic diagram as well as the cross-section, the storage plate 18 is electrically coupled to the source/drain region 22 of access transistor 28. In this embodiment, a conductive strap 30 formed in an upper portion of the trench electrically couples the storage plate 18 to the doped region 22. Isolation collar 32 is provided to electrically isolate the capacitor electrode 16 from the doped region 22. Shallow trench isolation region 36 electrically isolates the trench capacitor 12 from adjacent any devices (e.g., the storage cell of an adjacent memory)”
4 “[0038] In a first embodiment, the dielectric layer 20 comprises a nanolaminate formed by sequential layers of a first material that has a high dielectric constant and subsequent layers that have a high band offset relative to silicon (e.g., greater than about 1.5 to 2 eV). This combination of materials is preferred since a high dielectric constant material will retain charge and a high band offset will avoid leakage. For example, as discussed above, TiO.sub.2 has an excellent dielectric constant of around 80, but the conduction band offset is quite low. Hence TiO.sub.2 is not preferred by itself. Rather, this material is preferably combined with some material, which helps to increase the band offset. Alternatively, the first layer can be a material with a high conduction band offset to silicon (e.g., Al.sub.2O.sub.3, HfO.sub.2, and others). The subsequent layer could be the material with high dielectric constant (for example, TiO.sub.2). This sequence can be repeated with or without the addition of additional binary films, as discussed below, until the required film thickness is attained.
[0039] For a nanolaminate dielectric layer 20, the individual layers (e.g., SrO, Al.sub.2O.sub.3, TiO.sub.2, Hf.sub.3N.sub.4, AlN, HfO.sub.2) are a few nm thick. In a preferred embodiment, the thickness is preferably about 0.5 nm to about 4 nm, typically about 1 nm. The layers are ideally intact as deposited. However, some intermixing/reactions can occur at the interfaces between each layer during a high temperature anneal
“.