Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 8, 23, 24, 26 and 27 rejected under 35 U.S.C. 103 as being unpatentable over Palacios (WO 2008128160) of record, in view of Suh (U.S. Patent Pub. No. 2009/0072272) of record.
Regarding Claim 1
FIG. 5 of Palacios discloses a semiconductor device, comprising: a first nitride semiconductor layer (GaN) made entirely of an undoped nitride semiconductor and having a lower surface in which a trench is formed such that a thickness of the first nitride semiconductor layer over the trench is less than a thickness of the first nitride semiconductor layer in a region of the first nitride semiconductor layer that is not over the trench; a second nitride semiconductor layer (AlGaN) on an upper surface of the first nitride semiconductor layer; a source electrode (S) on part of an upper surface of the second nitride semiconductor layer; a drain electrode (D) on part of an upper surface of the second nitride semiconductor layer; a buffer layer (GaN Si) on a portion of the lower surface of the first nitride semiconductor layer where a trench is not formed, the trench passing through the buffer layer; a semiconductor substrate (Wafer) is formed on a lower surface of the buffer layer, the trench passing through the semiconductor substrate; and a gate electrode (G2) located between the source electrode and the drain electrode, wherein the second nitride semiconductor layer (AlGaN) has a larger bandgap than the first nitride semiconductor layer (GaN), the drain electrode is separated from the source electrode, the gate electrode is provided on a bottom part of the trench, and the gate electrode is not provided in a side part of the trench.
Palacios is silent with respect to “a gate electrode located on the lower surface of the first nitride semiconductor layer” and “the gate electrode is provided on a bottom part of the trench in direct contact with the lower surface of the first nitride semiconductor layer where the trench is formed, and an entirety of the buffer layer is lower than an entiretyof the Gate electrode”.
FIG. 1 (annotated below) of Suh discloses a similar semiconductor device, comprising a first nitride semiconductor layer (14 and upper portion of 15) having a lower surface in which a trench is formed such that a thickness of the first nitride semiconductor layer over the trench is less than a thickness of the first nitride semiconductor layer in a region of the first nitride semiconductor layer that is not over the trench; a buffer layer (lower portion of 15) on a portion of the lower surface of the first nitride semiconductor layer where a trench is not formed, the trench passing through the buffer layer; and a gate electrode (17) located on the lower surface of the first nitride semiconductor layer, and the gate electrode is provided on a bottom part of the trench in direct contact with the lower surface of the first nitride semiconductor layer where the trench is formed; the gate electrode is not provided in a side part of the trench, and an entirety of the buffer layer is lower than an entirety of the Gate electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Palacios, as taught by Suh. The ordinary artisan would have been motivated to modify Palacios in the above manner, because, as shown by the various embodiments of Suh, the claimed configuration was a matter of choice, which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant. In re Dailey 149 USPQ 47, 50 (CCPA 1966). See also Glue Co. v. Upton 97 US 3,24 (USSC 1878). MPEP 2144.04.
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Regarding Claim 2
FIG. 5 of Palacios discloses the lower surface of the first nitride semiconductor layer is an N plane.
Regarding Claim 3
FIG. 5 of Palacios discloses the first nitride semiconductor layer is made of GaN.
Regarding Claim 4
FIG. 5 of Palacios discloses the upper surface of the second nitride semiconductor layer is a Ga plane.
Regarding Claim 8
FIG. 5 of Palacios discloses a third nitride semiconductor layer (60) on the upper surface of the second nitride semiconductor layer, wherein the source electrode (S) is provided on part of an upper surface of the third nitride semiconductor layer, and the drain electrode (D) is provided on part of the upper surface of the third nitride semiconductor layer.
Regarding Claim 23
FIG. 1 of Suh discloses a lowest surface of the gate electrode (17’) is arranged above a lowest surface of the first nitride semiconductor layer.
Regarding Claim 24
FIG. 5 of Palacios discloses an entirety of the gate electrode (G2) is arranged within the trench.
Regarding Claim 26
FIG. 5 of Palacios discloses the buffer layer is configured to reduce a lattice mismatch between the semiconductor substrate and the first nitride semiconductor layer.
Regarding Claim 27
FIG. 5 of Palacios discloses the semiconductor substrate is made of silicon, silicon carbide, or sapphire.
Claims 7 and 18-20 rejected under 35 U.S.C. 103 as being unpatentable over Palacios, in view of Suh, in view of Zhang (CN 107919394) of record.
Regarding Claim 7
FIG. 5 of Palacios discloses a semiconductor device, comprising: a first nitride semiconductor layer (GaN) made entirely of an undoped nitride semiconductor and having a lower surface in which a trench is formed such that a thickness of the first nitride semiconductor layer over the trench is less than a thickness of the first nitride semiconductor layer in a region of the first nitride semiconductor layer that is not over the trench; a second nitride semiconductor layer (AlGaN) on an upper surface of the first nitride semiconductor layer; a source electrode (S) on part of an upper surface of the second nitride semiconductor layer; a drain electrode (D) on part of an upper surface of the second nitride semiconductor layer; a buffer layer (GaN Si) on a portion of the lower surface of the first nitride semiconductor layer where a trench is not formed, the trench passing through the buffer layer; a semiconductor substrate (Wafer) is formed on a lower surface of the buffer layer, the trench passing through the semiconductor substrate; and a gate electrode (G2) located between the source electrode and the drain electrode, wherein the second nitride semiconductor layer (AlGaN) has a larger bandgap than the first nitride semiconductor layer (GaN), the drain electrode is separated from the source electrode, and the gate electrode is not provided in a side part of the trench.
Palacios is silent with respect to “a gate electrode located on the lower surface of the first nitride semiconductor layer”; “the gate electrode is provided on a bottom part of the trench in direct contact with the lower surface of the first nitride semiconductor layer where the trench is formed” and “a dielectric layer covering the source electrode and the drain electrode on the upper surface of the second nitride semiconductor layer; and a support substrate on an upper surface of the dielectric layer, wherein the support substrate is made of diamond”.
FIG. 1 (annotated above) of Suh discloses a similar semiconductor device, comprising a first nitride semiconductor layer (14 and upper portion of 15) having a lower surface in which a trench is formed such that a thickness of the first nitride semiconductor layer over the trench is less than a thickness of the first nitride semiconductor layer in a region of the first nitride semiconductor layer that is not over the trench; a buffer layer (lower portion of 15) on a portion of the lower surface of the first nitride semiconductor layer where a trench is not formed, the trench passing through the buffer layer; and a gate electrode (17) located on the lower surface of the first nitride semiconductor layer, and the gate electrode is provided on a bottom part of the trench in direct contact with the lower surface of the first nitride semiconductor layer where the trench is formed; the gate electrode is not provided in a side part of the trench, and an entirety of the buffer layer is lower than an entirety of the Gate electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Palacios, as taught by Suh. The ordinary artisan would have been motivated to modify Palacios in the above manner, because, as shown by the various embodiments of Suh, the claimed configuration was a matter of choice, which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant. In re Dailey 149 USPQ 47, 50 (CCPA 1966). See also Glue Co. v. Upton 97 US 3,24 (USSC 1878). MPEP 2144.04.
Palacios as modified by Suh is silent with respect to “a dielectric layer covering the source electrode and the drain electrode on the upper surface of the second nitride semiconductor layer; and a support substrate on an upper surface of the dielectric layer, wherein the support substrate is made of diamond”.
FIG. 1 of Zhang discloses a similar semiconductor device, comprising a dielectric layer (2) covering the source electrode and the drain electrode on the upper surface of the second nitride semiconductor layer; and a support substrate (1) on an upper surface of the dielectric layer, wherein the support substrate is made of diamond.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Palacios, as taught by Zhang. The ordinary artisan would have been motivated to modify Palacios in the above manner for purpose of small on-resistance, high saturation current and transconductance, and good breakdown characteristics (Abstract of Zhang).
Regarding Claim 18
FIG. 5 of Palacios discloses the lower surface of the first nitride semiconductor layer is an N plane.
Regarding Claim 19
FIG. 5 of Palacios discloses the first nitride semiconductor layer is made of GaN.
Regarding Claim 20
FIG. 5 of Palacios discloses the upper surface of the second nitride semiconductor layer is a Ga plane.
Claim 9 rejected under 35 U.S.C. 103 as being unpatentable over Palacios and Suh, in view of Pan (U.S. Patent Pub. No. 2015/0371982) of record.
Regarding Claim 9
Palacios as modified by Suh discloses Claim 1, wherein the gate electrode is provided on the lower surface of the first nitride semiconductor layer.
Palacios as modified by Suh is silent with respect to “a fourth nitride semiconductor layer on the lower surface of the first nitride semiconductor layer; and a fifth nitride semiconductor layer on a lower surface of the fourth nitride semiconductor layer; wherein the fourth nitride semiconductor layer has a larger bandgap than the first nitride semiconductor layer and the fifth nitride semiconductor layer, and the gate electrode is provided on the lower surface of the first nitride semiconductor layer not covered by the fourth semiconductor layer and the fifth semiconductor layer but exposed outside”.
FIG. 1 of Pan discloses a similar semiconductor device, comprising a fourth nitride semiconductor layer (104) on the lower surface of the first nitride semiconductor layer (106); and a fifth nitride semiconductor layer (101) on a lower surface of the fourth nitride semiconductor layer; wherein the fourth nitride semiconductor layer (AIN [0031]) has a larger bandgap (6.42eV) than the first nitride semiconductor layer (GaN [0031] 3.4eV) and the fifth nitride semiconductor layer (AlGaN [0032] 3.4-6.2eV), and the gate electrode is not covered by the fourth semiconductor layer and the fifth semiconductor layer but exposed outside.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Palacios, as taught by Pan. The ordinary artisan would have been motivated to modify Palacios in the above manner for purpose of having a switched substrate (Para. 9 of Pan).
Claim 21 rejected under 35 U.S.C. 103 as being unpatentable over Palacios, Suh and Zhang, in view of Pan (U.S. Patent Pub. No. 2015/0371982) of record.
Regarding Claim 21
Palacios as modified by Suh and Zhang discloses Claim 7.
Palacios as modified by Suh and Zhang is silent with respect to “a third nitride semiconductor layer on the upper surface of the second nitride semiconductor layer, wherein the source electrode is provided on part of an upper surface of the third nitride semiconductor layer, and the drain electrode is provided on part of the upper surface of the third nitride semiconductor layer”.
FIG. 1 of Pan discloses a similar semiconductor device, comprising a third nitride semiconductor layer (104) on the upper surface of the second nitride semiconductor layer (101), wherein the source electrode (114) is provided on part of an upper surface of the third nitride semiconductor layer, and the drain electrode (112) is provided on part of the upper surface of the third nitride semiconductor layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Palacios, as taught by Pan. The ordinary artisan would have been motivated to modify Palacios in the above manner for purpose of having a switched substrate (Para. 9 of Pan).
Claim 22 rejected under 35 U.S.C. 103 as being unpatentable over Palacios, Suh and Zhang, in view of Pan.
Regarding Claim 22
Palacios as modified by Suh and Zhang discloses Claim 7, wherein the gate electrode is provided on the lower surface of the first nitride semiconductor layer.
Palacios as modified by Suh and Zhang is silent with respect to “a fourth nitride semiconductor layer on the lower surface of the first nitride semiconductor layer; and a fifth nitride semiconductor layer on a lower surface of the fourth nitride semiconductor layer; wherein the fourth nitride semiconductor layer has a larger bandgap than the first nitride semiconductor layer and the fifth nitride semiconductor layer, and the gate electrode is provided on the lower surface of the first nitride semiconductor layer not covered by the fourth semiconductor layer and the fifth semiconductor layer but exposed outside”.
FIG. 1 of Pan discloses a similar semiconductor device, comprising a fourth nitride semiconductor layer (104) on the lower surface of the first nitride semiconductor layer (106); and a fifth nitride semiconductor layer (101) on a lower surface of the fourth nitride semiconductor layer; wherein the fourth nitride semiconductor layer (AIN) has a larger bandgap than the first nitride semiconductor layer (GaN) and the fifth nitride semiconductor layer (AlGaN), and the gate electrode is not covered by the fourth semiconductor layer and the fifth semiconductor layer but exposed outside.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Palacios, as taught by Pan. The ordinary artisan would have been motivated to modify Palacios in the above manner for purpose of having a switched substrate (Para. 9 of Pan).
Pertinent Art
FIG. 3 of Charles (U.S. Patent Pub. No. 2010/0065923) discloses a semiconductor device, comprising: a first nitride semiconductor layer (12) made entirely of an undoped nitride semiconductor and having a lower surface; a second nitride semiconductor layer (13) on an upper surface of the first nitride semiconductor layer; a source electrode (20) on part of an upper surface of the second nitride semiconductor layer; a drain electrode (21) on part of an upper surface of the second nitride semiconductor layer; a buffer layer (11) on a portion of the lower surface of the first nitride semiconductor layer where a trench is not formed, the trench passing through the buffer layer; a semiconductor substrate (10) is formed on a lower surface of the buffer layer, the trench passing through the semiconductor substrate; and a gate electrode (42) located on the lower surface of the first nitride semiconductor layer between the source electrode and the drain electrode, wherein the second nitride semiconductor layer (AlGaN) has a larger bandgap than the first nitride semiconductor layer (GaN), the drain electrode is separated from the source electrode, and the gate electrode is not provided in a side part of the trench. U.S. Patent Pub. No. 2019/0115459 by Kim discloses bands of GaN, AlGaN and InAlN. US 20170092752, US 6144048, and JP H09260404 disclose the gate electrode is provided on a bottom part of the trench in direct contact with the lower surface of the first nitride semiconductor layer, and the gate electrode is not provided in a side part of the trench. U.S. Patent Pub. No. 2006/0220060 discloses a lowest surface of the gate electrode is located closer to a lower surface of the second nitride semiconductor layer in relation to the lower surface of the first nitride semiconductor layer. Pertinent art also includes Fan (CN 109037066), Du (CN 106298911) and Chavarkar (U.S. Patent Pub. No. 2002/0167023).
Response to Arguments
Applicant’s arguments with respect to Claims 1 and 7 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897