DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 13 May 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10, 12, 14, 16, 18, 20, 22-23, 25-26, and 28-29 are rejected under 35 U.S.C. 103 as being unpatentable over Wang, Q., Tamukoh, H., & Morie, T. (2018). "A time-domain analog weighted-sum calculation model for extremely low power VLSI implementation of multi-layer neural networks." Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology. (hereinafter “Wang”) in view of US 20190138881 A1 Lin et al. (hereinafter “Lin”) in view of Morie, Takashi, et al. "An Analog-Digital Merged Neural Circuit Using Pulse Width Modulation Technique." Analog Integrated Circuits and Signal Processing 25 (2000): 319-328. (hereinafter “Morie”) further in view of Jeong, H. and Shi, L. "Memristor devices for neural networks". Topical Review. Journal of Physics D: Applied Physics. IOP Publishing. J. Phys. D.: Appl. Phys. 52 (2019) 023003 (28pp) 30 October 2018. (hereinafter “Jeong”) in view of US 20170323677 A1 Ge et al. (hereinafter “Ge”).
Regarding claim 10, Wang teaches a product-sum operation device (Fig. 6(b)) comprising:
a plurality of product operation circuits (Fig. 5(b), synapse, Fig. 6, individual synapses; Pg. 13, Para. 3) configured to generate output signals (Fig. 6(b), output dendrite line from synapse array to post-neurons; Pg. 13, Para. 3) by multiplying (Pg. 5, Equation 16; Pg. 4, Para. 1; Pg. 9, Equation 34) input signals (Pg. 5, Equation 16,
x
i
; Pg. 9, Equation 34,
x
i
; Fig. 1, input spikes; Fig. 6(b) inputs from pre-neurons; Pg. 13, Para. 3) corresponding to input values (Pg. 13, Para. 3) by weighting factors (Pg. 5, Equation 16,
a
i
; Pg. 4, Para. 1; Pg. 9, Equation 34,
w
i
j
(
n
)
; Pg. 13, Para. 3) and output (Pg. 14, Para. 3) the output signals (Fig. 5(b), Fig. 6, synapse; Pg. 13, Para. 3);
a current sensor configured to execute a current detecting process (Pg. 13, Para. 3; Pg. 14, Para. 2) in which a current output (Fig. 6(b), output dendrite line from synapse array to post-neurons; Pg. 13, Para. 3) from the plurality of product operation circuits (Fig. 5(b), synapse, Fig. 6, individual synapses; Pg. 13, Para. 3) with a predetermined time delay (Pg. 4, Equation 8 and 9,
θ
λ
β
) from input (Pg. 3, Para. 2,
t
i
) of an input signal (Pg. 5, Equation 16,
x
i
; Pg. 9, Equation 34,
x
i
; Fig. 1, input spikes; Fig. 6(b) inputs from pre-neurons; Pg. 13, Para. 3) of the input signals (Pg. 5, Equation 16,
x
i
; Pg. 9, Equation 34,
x
i
; Fig. 1, input spikes; Fig. 6(b) inputs from pre-neurons; Pg. 13, Para. 3) and a current output (Fig. 5(b), Fig. 6, synapse; Pg. 13, Para. 3) from the plurality of product operation circuits (Fig. 5(b), synapse, Fig. 6, individual synapses; Pg. 13, Para. 3) at a predetermined time interval (Pg. 5, Para. 1,
T
i
n
) thereafter are detected in a time span (Pg. 4, Para. 7,
t
v
m
a
x
,
t
v
m
i
n
) from a first transient response (Fig. 1,
V
n
t
; Pg. 3, Para. 1) being converged to a steady state (Pg. 3, Para. 2) to before occurrence of a second transient response (Fig. 1,
i
n
(
t
)
; Pg. 3, Para. 1), the first transient response (Fig. 1,
V
n
t
; Pg. 3, Para. 1) being due to charging (Abstract; Pg. 12, Para. 2; Pg. 13, Para. 1, 3; Pg. 14, Para. 2) to a parasitic capacitance (Fig. 6(b),
C
a
l
,
C
d
l
; Pg. 14, Para. 2; Pg. 13, Para. 3) of the product operation circuits (Fig. 5(b), synapse, Fig. 6, individual synapses; Pg. 13, Para. 3) by input (Pg. 3, Para. 2,
t
i
) of the input signal (Pg. 5, Equation 16,
x
i
; Pg. 9, Equation 34,
x
i
; Fig. 1, input spikes; Fig. 6(b) inputs from pre-neurons; Pg. 13, Para. 3) and the second transient (Fig. 1,
i
n
(
t
)
; Pg. 3, Para. 1) response being due to discharging (Abstract; Pg. 14, Para. 2) from the parasitic capacitance (Fig. 6(b),
C
a
l
,
C
d
l
; Pg. 14, Para. 2; Pg. 13, Para. 3) of the product operation circuits (Fig. 5(b), synapse, Fig. 6, individual synapses; Pg. 13, Para. 3) by input (Pg. 3, Para. 2,
t
i
) of the input signal (Pg. 5, Equation 16,
x
i
; Pg. 9, Equation 34,
x
i
; Fig. 1, input spikes; Fig. 6(b) inputs from pre-neurons; Pg. 13, Para. 3); and
an adder (Fig. 6(b) and 6(c), comparator; Pg. 14, Para. 3; Note: the “comparator” of Wang performs the same functionality as the “adder” as claimed) configured to calculate a value (Fig. 6(b) and 6(c),
V
o
u
t
i
) relating to a total sum (Pg. 13, Para. 3; Pg. 14, Para. 1) of the output signals (Fig. 5(b), Fig. 6, synapse; Pg. 13, Para. 3) based on currents detected (Fig. 6(b), output dendrite line from synapse array to post-neurons; Pg. 13, Para. 3) at the predetermined time intervals (Pg. 5, Para. 1,
T
i
n
) by the current sensor, and
the current sensor ends the current detecting process (Pg. 13, Para. 3; Pg. 14, Para. 2) in a case in which a current detected (Fig. 6(b), output dendrite line from synapse array to post-neurons; Pg. 13, Para. 3) in the current detecting process (Pg. 13, Para. 3; Pg. 14, Para. 2) is the same (Pg. 4, Para. 5, both equal to 0) as a current (Fig. 6(b), output dendrite line from synapse array to post-neurons; Pg. 13, Para. 3) of a case in which no input signal (Pg. 4, Para. 5;
∀
i
x
i
=
0
) is input to the plurality of product operation circuits (Fig. 5(b), synapse, Fig. 6, individual synapses; Pg. 13, Para. 3), or at a time point (Fig. 1,
t
v
in
T
i
n
) at which a time is equal to a longest length (Pg. 4, Equation 9,
t
v
m
a
x
) that can be taken by the input signals (Pg. 5, Equation 16,
x
i
; Pg. 9, Equation 34,
x
i
; Fig. 1, input spikes; Fig. 6(b) inputs from pre-neurons; Pg. 13, Para. 3) elapses after the current detecting process (Pg. 13, Para. 3; Pg. 14, Para. 2) is executed for the first time (Fig. 1, beginning of time axis), and
wherein the product-sum operation device (Fig. 6(b)) does not include a capacitor that stores electric charge for calculating the value (Fig. 6(b) and 6(c),
V
o
u
t
i
) relating to the total sum (Pg. 13, Para. 3; Pg. 14, Para. 1) of the output signals (Fig. 5(b), Fig. 6, synapse; Pg. 13, Para. 3).
Although Wang teaches a capacitor (Fig. 6(b),
C
i
; Pg. 13, Para. 3; Pg. 14, Para. 2) which is capable of charging and executing a current detecting process, it appears they are silent to also teaching that it is configured to end the current detecting process on the basis of certain cases, and by nature, make that determination. While a capacitor is a component that is capable of sensing current, “a current sensor” as it appears in the claims is configured to perform more functionalities that a capacitor alone would not be capable of performing, such as making the determination to end current detection in several cases. Although Wang teaches the functionalities of the current sensor claimed, they appear to be silent to teaching a current sensor configured to end the current detecting process and perform the determination (the logical OR) on the basis of the process’s cases and does not include a capacitor that stores electric charge.
Although Wang teaches the product-sum operation device, input spikes as its input signals (Fig. 1, input spikes; Fig. 6(b) inputs from pre-neurons; Pg. 13, Para. 3) are voltage signals (Fig. 6(b), V-in2 , V-in1 , Vin0, Pg. 13, Para. 3), and the input value (Pg. 13, Para. 3), they teach that the spike pulses only indicate input timing, its pulse width and amplitude do not affect the processing (Pg. 3, Sec. 2, Sub. 2.1, Para. 1).
Although Wang generally teaches synapses (Fig. 6, individual synapses), they are silent with disclosing the specific materials or types that compose a synapse, specifically a magnetoresistive effect element exhibiting a magnetoresistive effect.
Thus, Wang is silent with disclosing:
a current sensor configured to end the current detecting process and perform the determination, the logical OR, on the basis of the process’s cases;
all input signals are voltage signals for which pulse width modulation (PWM) corresponding to the input value is performed;
a magnetoresistive effect element exhibiting a magnetoresistive effect;
does not include a capacitor that stores electric charge.
Lin teaches a current sensor (Fig. 1, coupling of 106, 104, 108, wherein 106 performs current sensing, [0012], [0014]) configured to end (Fig. 2, 104 which is coupled to 106 and 108, ends current sensing by switching to a floating mode, [0030]) the current detecting process and perform the determination, the logical OR, on the basis of (Fig. 1, 108 which is coupled to 106 and 104, controls the switching circuit 104 [0013], [0023] for current sensing or not during sum-of-product calculations [0026], [0030], [0035]) the process’s cases.
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Wang’s product-sum operation device with Lin’s current sensor feature, because they are in the claimed invention’s same field of endeavor of neuromorphic computing with a synapses array ([Abstract]). Lin teaches that as the number of synapses increases, the sum-of-product sensing currents yielded from the output may become large enough to result in high energy dissipation ([0003-0004]). Thus, it would have been obvious to one of ordinary skill in the art to implement Lin’s current sensor in place of Wang’s capacitor as Lin’s component possesses two terminals accesses in a switchable manner of which can only conduct a limited current, or even no current, which can effectively reduce the energy dissipation ([0005], [0043]). It would have been obvious to one of ordinary skill in the art to modify with Lin’s current sensor to achieve these benefits in an effort to potentially expand the number of synapses utilized, for purposes of calculating in parallel or computing larger sets of data at a time.
Although Lin discloses a current sensor that performs determinations for estimating a sum-of-product value in which the sensing circuit may include a sensing amplifier ([0014]), the processing circuit may be a micro-processor ([0014]), and the switching circuit may be switching elements ([0019]) without use of a capacitor, they appear to disclose an embodiment which does utilize a capacitor to solve the problem that the voltage difference between the first and second values may be too small to be read ([0042]).
Lin and the combination of Wang in view of Lin are silent with disclosing: all input signals are voltage signals for which pulse width modulation (PWM) corresponding to the input value is performed; a magnetoresistive effect element exhibiting a magnetoresistive effect; does not include a capacitor that stores electric charge.
Morie teaches all input signals are voltage signals for which pulse width modulation (PWM) corresponding to the input value is performed (Pg. 357, Sec. 2, Sub. 2.1, Para 1; Sec. 2, Sub. 2.2).
It would have been obvious to one of ordinary skill in the art before the effective
filing date to modify Wang in view of Lin’s modified product-sum operation device with Morie’s PWM feature, because they are in the claimed invention’s same field of endeavor of analog-digital merged circuitry architecture (summary). Although Wang generally discloses the input signals, as described above, they are silent with explicitly disclosing for which pulse width modulation (PWM) is performed. It would have been obvious to one of ordinary skill in the art to try applying the PWM feature as doing so in neural circuits is a known technique in the art (Pg. 1, Col. 2, Para. 1-2). Further, Morie teaches that implementing a PWM approach leads to low voltage operation and power consumption (Pg. 1, Col. 1, Para. 3, Col. 2, Para. 1), of which was an objective of Wang’s reference when implementing the TACT approach in Wang in view of Lin’s device (Wang, Pg. 2, Para. 3). Thus, it would have been obvious to try a known technique in the art, and would have yielded beneficial results when implemented.
Morie and the combination of Wang in view of Lin in view of Morie are silent with disclosing: a magnetoresistive effect element exhibiting a magnetoresistive effect; does not include a capacitor that stores electric charge.
Jeong teaches:
a magnetoresistive effect element (Fig. 1(b), MRAM; Pg. 1, Col. 2) exhibiting a magnetoresistive effect (Pg. 4, Col. 1, Para. 3; Fig. 2(a), field and STT switching; Pg. 4, Col. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the synapses in Wang in view of Lin in view of Morie’s product-sum operation system with Jeong’s MRAM synapse because they are in the claimed invention’s same field of endeavor of a cross-bar array implementation of weighted multiply-accumulate operations in neural networks (Pg. 10, Col. 1, Para. 1). Wang teaches the basic structures of the synapses, however, they do not specifically detail what type they are using or any alternatives. Jeong teaches MRAM synapses and others as being suitable alternatives for conventional synapse approaches (Pg. 4, Col. 1, Para. 2). It would be beneficial to make this modification as doing so would achieve a higher density of synapses (Pg. 11, Col. 2), not readily lose results of trained weights as MRAM synapses are non-volatile (Pg. 11, Col. 1, Para. 2), and experience similar latency and endurance results as conventional approaches (Pg. 11, Col. 2). Modifying with Jeong’s MRAM synapses implementation would have been obvious to one of ordinary skill in the art, since one of ordinary skill in the art would recognize that Wang in view of Lin in view of Morie’s system was ready for improvement to incorporate the magnetoresitve effect elements, as taught by Jeong.
Jeong and the combination of Wang in view of Lin in view of Morie in view of Jeong are silent with disclosing does not include a capacitor that stores electric charge.
Ge discloses does not include a capacitor that stores electric charge (Fig. 3 “306” [0034-0037], [0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Wang’s post-neurons in view of Lin in view of Morie in view of Jeong’s product-sum operation system with Ge’s non-capacitor implementation feature because they are in the claimed invention’s same field of endeavor of a crossbar array implementation of weighted multiply-accumulate operations ([0008]). Wang teaches the basic structures of the post-neurons, however, they do not specifically detail non-capacitor implementations for computing the output sums. Ge discloses evaluation gates which are transistors that open and close to collect the output charges via a control signal ([0045]) providing the circuit a flexible output measurement resolution ([0037]). It would have been beneficial to modify with the non-capacitor implementation as the output measurement resolution is tunable through different integration periods ([0009], [0050]), providing designers greater circuit configurability based on output resolution requirements. Modifying with Ge’s non-capacitor implementation would have been obvious to one of ordinary skill in the art before the effective filing date, since one of ordinary skill in the art would recognize that Wang in view of Lin in view of Morie in view of Jeong’s system was ready for improvement to incorporate the non-capacitor features and would yield predictable results of storing electric charge, as taught by Ge.
Regarding claim 12, in addition to the teachings addressed in the claim 10 analysis, the rejection of claim 10 is incorporated and Wang teaches a product-sum operation device wherein:
the adder (Fig. 6(b) and 6(c), comparator; Pg. 14, Para. 3; Note: the “comparator” of Wang performs the same functionality as the “adder” as claimed) calculates (Pg. 6(b), S1, S2, S_rst, inverters; Pg. 14, Para. 3) a product of a total current (Fig. 6(b), all charges of
C
d
l
per column; Pg. 13, Para. 3) that is a sum of currents (Fig. 6(b), output dendrite line from synapse array to post-neurons; Pg. 13, Para. 3) detected at the predetermined time intervals (Pg. 5, Para. 1,
T
i
n
) by the current sensor and a coefficient time (Pg. 3, Equation 8,
t
v
m
i
n
), as the value (Fig. 6(b) and 6(c),
V
o
u
t
i
) relating to the total sum (Pg. 13, Para. 3; Pg. 14, Para. 1) of the output signals (Fig. 5(b), Fig. 6, synapse; Pg. 13, Para. 3).
Although Wang teaches a capacitor (Fig. 6(b),
C
i
; Pg. 13, Para. 3; Pg. 14, Para. 2) which is capable of charging and executing a current detecting process, it appears they are silent to also teaching that it is configured to end the current detecting process on the basis of certain cases, and by nature, make that determination. Although Wang teaches the functionalities of the current sensor claimed, they appear to be silent to teaching a current sensor.
Lin teaches a current sensor (Fig. 1, coupling of 106, 104, 108, wherein 106 performs current sensing, [0012], [0014]).
The motivation to combine provided with respect to claim 10 equally applies.
Regarding claim 14, in addition to the teachings addressed in the claim 12 analysis, the rejection of claim 12 is incorporated and Wang teaches a product-sum operation device wherein:
the coefficient time (Pg. 3, Equation 8,
t
v
m
i
n
) is a shortest length that can be taken by the input signals (Pg. 5, Equation 16,
x
i
; Pg. 9, Equation 34,
x
i
; Fig. 1, input spikes; Fig. 6(b) inputs from pre-neurons; Pg. 13, Para. 3),
wherein the input signals (Pg. 5, Equation 16,
x
i
; Pg. 9, Equation 34,
x
i
; Fig. 1, input spikes; Fig. 6(b) inputs from pre-neurons; Pg. 13, Para. 3) have a length of an integer multiple (Pg. 4, Equation 8, λβ when in terms of
θ
is
θ
=
λ
β
t
v
m
i
n
-
T
m
i
n
; Pg. 4, Para. 3,
λ
is a positive constant; Pg. 6, Para. 2,
λ
=
1
) of the coefficient time (Pg. 3, Equation 8,
t
v
m
i
n
) and are simultaneously input (Fig. 1, input spikes; Fig. 3, input layer; Pg. 9, Para. 1; Pg. 4, Para. 1) to the plurality of product operation circuits (Fig. 5(b), synapse, Fig. 6, individual synapses; Pg. 13, Para. 3), and
wherein the current sensor executes the current detecting process (Pg. 13, Para. 3; Pg. 14, Para. 2) in a period equal (Fig. 1,
T
i
n
) to the coefficient time (Pg. 3, Equation 8,
t
v
m
i
n
).
Although Wang teaches a capacitor (Fig. 6(b),
C
i
; Pg. 13, Para. 3; Pg. 14, Para. 2) which is capable of charging and executing a current detecting process, it appears they are silent to also teaching that it is configured to end the current detecting process on the basis of certain cases, and by nature, make that determination. Although Wang teaches the functionalities of the current sensor claimed, they appear to be silent to teaching a current sensor.
Lin teaches a current sensor (Fig. 1, coupling of 106, 104, 108, wherein 106 performs current sensing, [0012], [0014]).
The motivation to combine provided with respect to claim 10 equally applies.
Regarding claim 16, in addition to the teachings addressed in the claim 10 analysis, the rejection of claim 10 is incorporated and Wang teaches a product-sum operation device wherein:
the current sensor ends the current detecting process (Pg. 13, Para. 3; Pg. 14, Para. 2) at a time point (Fig. 1,
t
v
in
T
i
n
) at which a time equal to a longest length (Pg. 4, Equation 9,
t
v
m
a
x
) that can be taken by the input signals (Pg. 5, Equation 16,
x
i
; Pg. 9, Equation 34,
x
i
; Fig. 1, input spikes; Fig. 6(b) inputs from pre-neurons; Pg. 13, Para. 3) elapses after the current detecting process (Pg. 13, Para. 3; Pg. 14, Para. 2) is executed for the first time (Fig. 1, beginning of time axis).
Although Wang teaches a capacitor (Fig. 6(b),
C
i
; Pg. 13, Para. 3; Pg. 14, Para. 2) which is capable of charging and executing a current detecting process, it appears they are silent to also teaching that it is configured to end the current detecting process on the basis of certain cases, and by nature, make that determination. Although Wang teaches the functionalities of the current sensor claimed, they appear to be silent to teaching a current sensor configured to end the current detecting process.
Lin teaches a current sensor (Fig. 1, coupling of 106, 104, 108, wherein 106 performs current sensing, [0012], [0014]) configured to end (Fig. 2, 104 which is coupled to 106 and 108, ends current sensing by switching to a floating mode, [0030]) the current detecting process.
The motivation to combine provided with respect to claim 10 equally applies.
Regarding claim 18, in addition to the teachings addressed in the claim 12 analysis, the rejection of claim 12 is incorporated and Wang teaches a product-sum operation device wherein:
the current sensor ends the current detecting process (Pg. 13, Para. 3; Pg. 14, Para. 2) at a time point (Fig. 1,
t
v
in
T
i
n
) at which a time equal to a longest length (Pg. 4, Equation 9,
t
v
m
a
x
) that can be taken by the input signals (Pg. 5, Equation 16,
x
i
; Pg. 9, Equation 34,
x
i
; Fig. 1, input spikes; Fig. 6(b) inputs from pre-neurons; Pg. 13, Para. 3) elapses after the current detecting process (Pg. 13, Para. 3; Pg. 14, Para. 2) is executed for the first time (Fig. 1, beginning of time axis).
Although Wang teaches a capacitor (Fig. 6(b),
C
i
; Pg. 13, Para. 3; Pg. 14, Para. 2) which is capable of charging and executing a current detecting process, it appears they are silent to also teaching that it is configured to end the current detecting process on the basis of certain cases, and by nature, make that determination. Although Wang teaches the functionalities of the current sensor claimed, they appear to be silent to teaching a current sensor configured to end the current detecting process.
Lin teaches a current sensor (Fig. 1, coupling of 106, 104, 108, wherein 106 performs current sensing, [0012], [0014]) configured to end (Fig. 2, 104 which is coupled to 106 and 108, ends current sensing by switching to a floating mode, [0030]) the current detecting process.
The motivation to combine provided with respect to claim 10 equally applies.
Regarding claim 20, in addition to the teachings addressed in the claim 10 analysis, the rejection of claim 10 is incorporated and Wang teaches a product-sum operation device wherein:
the current sensor ends the current detecting process (Pg. 13, Para. 3; Pg. 14, Para. 2) in a case in which a current detected (Fig. 6(b), output dendrite line from synapse array to post-neurons; Pg. 13, Para. 3) in the current detecting process (Pg. 13, Para. 3; Pg. 14, Para. 2) is equal (Pg. 4, Para. 5, both equal to 0) to a current acquired (Fig. 6(b), output dendrite line from synapse array to post-neurons; Pg. 13, Para. 3) in a case in which no input signal (Pg. 4, Para. 5;
∀
i
x
i
=
0
) is input to the plurality of product operation circuits (Fig. 5(b), synapse, Fig. 6, individual synapses; Pg. 13, Para. 3).
Although Wang teaches a capacitor (Fig. 6(b),
C
i
; Pg. 13, Para. 3; Pg. 14, Para. 2) which is capable of charging and executing a current detecting process, it appears they are silent to also teaching that it is configured to end the current detecting process on the basis of certain cases, and by nature, make that determination. Although Wang teaches the functionalities of the current sensor claimed, they appear to be silent to teaching a current sensor configured to end the current detecting process.
Lin teaches a current sensor (Fig. 1, coupling of 106, 104, 108, wherein 106 performs current sensing, [0012], [0014]) configured to end (Fig. 2, 104 which is coupled to 106 and 108, ends current sensing by switching to a floating mode, [0030]) the current detecting process.
The motivation to combine provided with respect to claim 10 equally applies.
Regarding claim 22, in addition to the teachings addressed in the claim 12 analysis, the rejection of claim 12 is incorporated and Wang teaches a product-sum operation device wherein:
the current sensor ends the current detecting process (Pg. 13, Para. 3; Pg. 14, Para. 2) in a case in which a current detected (Fig. 6(b), output dendrite line from synapse array to post-neurons; Pg. 13, Para. 3) in the current detecting process (Pg. 13, Para. 3; Pg. 14, Para. 2) is equal (Pg. 4, Para. 5, both equal to 0) to a current acquired (Fig. 6(b), output dendrite line from synapse array to post-neurons; Pg. 13, Para. 3) in a case in which no input signal (Pg. 4, Para. 5;
∀
i
x
i
=
0
) is input to the plurality of product operation circuits (Fig. 5(b), synapse, Fig. 6, individual synapses; Pg. 13, Para. 3).
Although Wang teaches a capacitor (Fig. 6(b),
C
i
; Pg. 13, Para. 3; Pg. 14, Para. 2) which is capable of charging and executing a current detecting process, it appears they are silent to also teaching that it is configured to end the current detecting process on the basis of certain cases, and by nature, make that determination. Although Wang teaches the functionalities of the current sensor claimed, they appear to be silent to teaching a current sensor configured to end the current detecting process.
Lin teaches a current sensor (Fig. 1, coupling of 106, 104, 108, wherein 106 performs current sensing, [0012], [0014]) configured to end (Fig. 2, 104 which is coupled to 106 and 108, ends current sensing by switching to a floating mode, [0030]) the current detecting process.
The motivation to combine provided with respect to claim 10 equally applies.
Regarding claim 23, in addition to the teachings addressed in the claim 10 analysis, the rejection of claim 10 is incorporated and Wang teaches a logical operation device comprising:
the product-sum operation device (Fig. 6(b)).
The preamble in claim 10 has been given patentable weight as claim 23 depends on the preamble for completeness, and gives life, meaning, and vitality into this claim by the reference to “the product-sum operation device”. A skilled person in the art reading the claims would consider the claim in view of the body and the preamble, and identify them limited to device as described by claim 10.
Regarding claim 25, in addition to the teachings addressed in the claim 12 analysis, the rejection of claim 12 is incorporated and Wang teaches a logical operation device comprising:
the product-sum operation device (Fig. 6(b)).
The preamble in claim 10 has been given patentable weight as claim 25 depends on the preamble for completeness, and gives life, meaning, and vitality into this claim by the reference to “the product-sum operation device”. A skilled person in the art reading the claims would consider the claim in view of the body and the preamble, and identify them limited to device as described by claim 10.
Regarding claim 26, in addition to the teachings addressed in the claim 10 analysis, the rejection of claim 10 is incorporated and Wang teaches a neuromorphic device comprising:
the product-sum operation device (Fig. 6(b)).
The preamble in claim 10 has been given patentable weight as claim 26 depends on the preamble for completeness, and gives life, meaning, and vitality into this claim by the reference to “the product-sum operation device”. A skilled person in the art reading the claims would consider the claim in view of the body and the preamble, and identify them limited to device as described by claim 10.
Regarding claim 28, in addition to the teachings addressed in the claim 12 analysis, the rejection of claim 12 is incorporated and Wang teaches a neuromorphic device comprising:
the product-sum operation device (Fig. 6(b)).
The preamble in claim 10 has been given patentable weight as claim 28 depends on the preamble for completeness, and gives life, meaning, and vitality into this claim by the reference to “the product-sum operation device”. A skilled person in the art reading the claims would consider the claim in view of the body and the preamble, and identify them limited to device as described by claim 10.
Regarding claim 29, in addition to the teachings addressed in the claim 10 analysis, the rejection of claim 10 is incorporated. Claim 29 is directed towards a method of performing the limitations recited in claim 10 and includes no additional new limitations. Therefore, the claim 10 analysis equally applies to claim 29.
Response to Arguments
35 USC 112(f). The previous interpretation is no longer invoked due to the amendments to the claims.
Specification. The amendments to the claims have overcome the specification objections.
35 USC 112(a). The rejections are withdrawn based on the amendment to the claims.
35 USC 112(b). The rejections are withdrawn based on the amendment to the claims.
35 USC 103. Applicant’s arguments, see Remarks p. 10 ¶3, filed 13 May 2026, with respect to the rejection(s) of claim(s) 10,12,14,16,18,20,22-23,25-26 and 28-29 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ge as necessitated by the amendment to the claims.
Applicant asserts that, Wang is also materially different from the presently claimed detection scheme. Wang's model uses spike timing and transient response behavior for weighted-sum computation. By contrast, the specification defines a steady part after convergence of the first transient response and before occurrence of the second transient response, and teaches executing the current detecting process within that steady part. The specification further teaches that the sum operation unit calculates a product of a sum current and a coefficient time. Wang does not teach or suggest this steady-state current-sampling scheme (see Remarks p. 10 ¶2).
Examiner respectfully disagrees. The steady state is achieved before and after the output spike is transmitted, thus is a perquisite before firing the output during current sensing (p. 3 Sec. 2-2.1).
Conclusion
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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