DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are not found persuasive.
In response to applicant's argument that “the cited references fail to recognize the technical problem solved by the present application: preventing dissolution of MoOx hole-transport layers during fabrication” on page 1 of the remarks, the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
More specifically, the claim recites a structure having an ETL, absorption material, and a HTL, where the absorption layer and ETL are configured to shield the hole transport layer in a cleaning process.
Firstly, this claim recites functional limitations of the instant invention where an N-type silicon ETL and an intrinsic silicon absorption layer are provided above a HTL. Since Nakamura and Wang both teach an N-type silicon ETL and an intrinsic silicon absorption layer provided above a HTL, said elements would be capable of performing the functional limitation of “configured to shield the hole transport layer in a cleaning process” since they are substantially identical (see MPEP 2114(II)).
Secondly, even though the prior art structure is identical to that claimed, the method claim does not positively recite a cleaning process so the “configured to shield the hole transport layer in a cleaning process” limitation is not given patentable weight in the method claim.
Thirdly, if this functional limitation is given weight, the structure of Wang would have the N-type silicon layer and intrinsic silicon layer on top of the MoOx HTL and the etching method of Yoon shows that the N-type silicon layer and intrinsic silicon layer would shield the lowest-most layer.
On page 3 of the remarks, Applicant argues that even though Wang teaches N-type silicon layer and intrinsic silicon layer on top of the MoOx HTL, Wang does not acknowledge the technical issue of “process difficulties in photosensors using molybdenum oxide as a hole-transport layer material,” nor does he suggest a technical solution to this problem.
Again, Examiner repeats that the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
Applicant argues on page 4 that using one mask plate to prevent MoOx dissolution.
Examiner has relied on Yoon to teach the concept of using one mask plate, where the subsequent layers above are used ask etch masks for the lower layers. This concept is a known technique. Applicant has not argued how the teachings of Yoon would not support Examiner’s position that each and every limitation has been taught by Nakamura, Wang, Yoon, and/or Nomura.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-14, 17-19, 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (US PGPub 2010/0134735; hereinafter “Nakamura”) in view of Wang et al. (CN109980020; hereinafter “Wang”; see attached machine translation for paragraph numbers) and Yoon et al. (US PGPub 2019/0198702; hereinafter “Yoon”).
Re claim 9: Nakamura teaches (e.g. figs. 4, 5A-5D, and 6A-6D) a method of manufacturing a photoelectric sensor (250), comprising steps of: forming a first electrode (129) on a transparent substrate (100); depositing a layer of hole transport material (p-type semiconductor 250a; e.g. paragraph 92) on the transparent substrate (100) and the first electrode (129); sequentially depositing a light absorption material (intrinsic semiconductor 250b) and an electron transport material (n-type semiconductor 250c; e.g. paragraph 92) on the hole transport material (250a); and performing a patterning process on the electron transport material (250c), the light absorption material (250b), and the hole transport material (250a) to form a hole transport layer (250a), a light absorption layer (250b), and an electron transport layer (250c) sequentially stacked and disposed on the first electrode (129), so that the light absorption layer (250b) and the electron transport layer (250c) are configured (the structure of Nakamura is configured to perform the below recited limitation to a cleaning process since the actual cleaning process has not been positively recited as being part of the multistep process) to shield the hole transport layer (250a) in a cleaning process, wherein the light absorption layer (250b) is an intrinsic non-doped semiconductor (250b is an amorphous silicon material having high resistance which is intrinsic and undoped; e.g. paragraph 92, 138), and a material of the electron transport layer (250c) is N-type heavily doped material (N-type amorphous silicon layer; e.g. paragraph 92) and comprises any one of amorphous silicon, microcrystalline silicon, and polycrystalline silicon.
Nakamura is silent as to explicitly teaching the hole transport material is molybdenum oxide; and wherein the performing of the patterning process comprises: performing a patterning process on the electron transport material by using one mask plate to form the electron transport layer; performing a patterning process on the light absorption material by using the electron transport layer as a mask plate to form the light absorption layer; and performing a patterning process on the molybdenum oxide by using the electron transport layer and the light absorption layer as a mask plate to form the hole transport layer.
Wang teaches (e.g. fig. 1) a material of the hole transport layer (hole selection layer 3 made form molybdenum oxide; e.g. paragraph 37) is molybdenum oxide (hole selection layer 3 made form molybdenum oxide; e.g. paragraph 37), and Wang further teaches wherein the light absorption layer (intrinsic amorphous silicon layer 4; e.g. paragraph 37) is an intrinsic non-doped semiconductor (intrinsic amorphous silicon layer 4; e.g. paragraph 37), and a material of the electron transport layer (N-type dopes amorphous silicon layer 5; e.g. paragraph 37) is an N-type heavily doped material (N-type dopes amorphous silicon layer 5; e.g. paragraph 37) and comprises any one of amorphous silicon, microcrystalline silicon, and polycrystalline silicon.
Yoon teaches (e.g. figs. 2, 3A-D, 4B) the performing of the patterning process comprises: performing a patterning process on the electron transport material (250c of Nakamura/5 of Wang) by using one mask plate (208a is used as a mask for dry etching operation; e.g. paragraph 39 of Yoon) to form the electron transport layer (250c of Nakamura/5 of Wang); performing a patterning process on the light absorption material (250b of Nakamura/4 of Wang) by using the electron transport layer (250c of Nakamura/5 of Wang) as a mask plate to form the light absorption layer (250b of Nakamura/4 of Wang); and performing a patterning process on the molybdenum oxide (3 of Wang) by using the electron transport layer (250c of Nakamura/5 of Wang) and the light absorption layer (250b of Nakamura/4 of Wang) as a mask plate to form the hole transport layer (3 of Wang).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the molybdenum doped indium oxide transparent conductive oxide, molybdenum oxide for the p-type hole transport material, and the remaining portion of the PIN diode as taught by Wang and the etching operation as taught by Yoon in the device of Nakamura in order to have the predictable result of using known PIN diode structure which has an increased response to short-wave bands of visible light with improved utilization of light, thereby improving battery efficiency of the device (see paragraph 38 of Wang), and in order to have the predictable result of using a known etching operation simplifying the manufacturing process to form a light receiving element, respectively.
Re claim 10: Nakamura in view of Wang teaches the method of manufacturing the photoelectric sensor according to claim 9, wherein the method further comprises steps of: forming an insulation layer (221) on the transparent substrate (100), wherein the insulation layer (221) covers the hole transport layer (250a of Nakamura/3 of Wang), the light absorption layer (250b/4 of Wang), and the electron transport layer (250c/5 of Wang); etching the insulation layer (221) to form a first via hole (233) exposing the first electrode (129) and a second via hole (232) exposing the electron transport layer (250c/5 of Wang); and forming a second electrode (227) on the electron transport layer (250c/5 of Wang) and the insulation layer (221).
Re claim 11: Nakamura in view of Wang teaches the method of manufacturing the photoelectric sensor according to claim 9, wherein a forbidden band width of the molybdenum oxide (3 of Wang) is greater than or equal to 2.8 eV and less than or equal to 3.6 eV, and a work function of the molybdenum oxide (3 of Wang) is greater than or equal to 5.2 eV and less than or equal to 6.8 eV. Since the claimed structure is substantially identical to that of the prior art, it is presumed that claimed properties are presumed to be present (see MPEP 2112.01(i)).
Re claim 12: Nakamura in view of Wang teaches the method of manufacturing the photoelectric sensor according to claim 9, wherein the electron transport layer (electron transport layer 250c of Nakamura/5 of Wang is n-type amorphous Si) is an N-type semiconductor, and the hole transport layer (3 of Wang), the light absorption layer (5 of Wang), and the electron transport layer (6 of Wang) form a semiconductor heterostructure.
Re claim 13: Nakamura in view of Wang teaches the method of manufacturing the photoelectric sensor according to claim 9, wherein a method of sequentially depositing the light absorption material and the electron transport material on the molybdenum oxide is a chemical vapor deposition method (CVD is a common method of depositing amorphous and molybdenum oxide; hole injecting layer can be amorphous silicon or molybdenum oxide; e.g. paragraph 137-139 and 247 of Nakamura) or an atomic layer deposition method.
Re claim 14: Nakamura teaches (e.g. figs. 4, 5A-5D, 6A-6D, 8, 9, and 11) a display panel, comprising a transparent substrate (100), a photoelectric sensor (250, 252) and pixel units (organic light emitting element 156; e.g. paragraph 175) disposed above the transparent substrate (100) in a vertical direction perpendicular to an upper surface of the transparent substrate (100), a cover plate (270) above the photoelectric sensor (250, 252) and pixel units (156) in the vertical direction, wherein the photoelectric sensor (250, 252) is disposed between and at least partially adjacent to the pixel units (156) in a horizontal direction perpendicular (fig. 11 shows the horizontal offset of 252 and 156) to the vertical direction, and the photoelectric sensor (250, 252) comprises: a first electrode (129) disposed on the transparent substrate (100) in the vertical direction; a hole transport layer (p-type semiconductor 250a; e.g. paragraph 92) disposed directly on the first electrode (129) in the vertical direction; a light absorption layer (intrinsic semiconductor 250b) disposed on one side of the hole transport layer (250a) away from the first electrode (129) in the vertical direction (100); and an electron transport layer (n-type semiconductor 250c; e.g. paragraph 92) disposed on one side (upper side) of the light absorption layer (250b) away from the hole transport layer (250a), so that the light absorption layer (250b) and the electron transport layer (250c) are configured to shield the hole transport layer (250a) in a cleaning process, wherein each of the pixel units (156) comprises a gate (111_4) disposed on the transparent substrate (100) in the vertical direction, wherein the first electrode (129) and the gate (111_4) are disposed at intervals in a same level (level of 102, 109, 121, 221), wherein an out light side of each of the pixel units (156) faces the transparent substrate (100), one side (bottom side of 100) of the transparent substrate (100) away from the hole transport layer (250a) is a light incident side of the photoelectric sensor (250, 252); and wherein the light absorption layer (250b) is an intrinsic non-doped semiconductor (250b is an amorphous silicon material having high resistance which is intrinsic and undoped; e.g. paragraph 92, 138), and a material of the electron transport layer (250c) is an N-type heavily doped material (N-type amorphous silicon layer; e.g. paragraph 92) and comprises any one of amorphous silicon, microcrystalline silicon, and polycrystalline silicon.
Nakamura is silent as to explicitly teaching a material of the hole transport layer is molybdenum oxide; black matrixes provided at a surface of the cover plate facing the transparent substrate, wherein the black matrixes respectively overlap the pixel units and the photoelectric sensor is disposed outside a coverage area of the black matrix in the vertical direction.
Wang teaches (e.g. fig. 1) a material of the hole transport layer (hole selection layer 3 made form molybdenum oxide; e.g. paragraph 37) is molybdenum oxide (hole selection layer 3 made form molybdenum oxide; e.g. paragraph 37), and Wang further teaches wherein the light absorption layer (intrinsic amorphous silicon layer 4; e.g. paragraph 37) is an intrinsic non-doped semiconductor (intrinsic amorphous silicon layer 4; e.g. paragraph 37), and a material of the electron transport layer (N-type dopes amorphous silicon layer 5; e.g. paragraph 37) is an N-type heavily doped material (N-type dopes amorphous silicon layer 5; e.g. paragraph 37) and comprises any one of amorphous silicon, microcrystalline silicon, and polycrystalline silicon.
Yoon teaches (e.g. figs. 2, 3A-D, 4B) black matrixes (light blocking film 210c; e.g. paragraph 36) provided at a surface (bottom surface of 270 of Nakamura) of the cover plate (270 of Nakamura) facing the transparent substrate (100 of Nakamura), wherein the black matrixes (210c) respectively overlap the pixel units (210c covers TFT channel preventing leakage current; e.g. paragraph 36) and the photoelectric sensor (250 of Nakamura) is disposed outside a coverage area of the black matrix (210c) in the vertical direction.
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the molybdenum doped indium oxide transparent conductive oxide, molybdenum oxide for the p-type hole transport material, and the remaining portion of the PIN diode as taught by Wang and to use the black matrix light blocking layer as taught by Yoon, in the device of Nakamura in order to have the predictable result of using known PIN diode structure which has an increased response to short-wave bands of visible light with improved utilization of light, thereby improving battery efficiency of the device (see paragraph 38 of Wang) and in order to have the predictable result of preventing leakage current of the TFTs (see paragraph 36 of Yoon), respectively.
Re claim 17: Nakamura in view of Wang teaches the display panel according to claim 14, wherein a forbidden band width of the molybdenum oxide (3 of Wang) is greater than or equal to 2.8 eV and less than or equal to 3.6 eV, and a work function of the molybdenum oxide (3 of Wang) is greater than or equal to 5.2 eV and less than or equal to 6.8 eV. Since the claimed structure is substantially identical to that of the prior art, it is presumed that claimed properties are presumed to be present (see MPEP 2112.01(i)).
Re claim 18: Nakamura in view of Wang teaches the photoelectric sensor according to claim 14, wherein the electron transport layer (electron transport layer 250c of Nakamura is n-type amorphous Si; e.g. paragraph 28) is an electronic semiconductor, and the hole transport layer (3 of Wang), the light absorption layer (4 of Wang), and the electron transport layer (5 of Wang) form a semiconductor heterostructure.
Re claim 19: Nakamura in view of Wang teaches the photoelectric sensor according to claim 14, wherein a material of the light absorption layer (250b of Nakamura) comprise any one of amorphous silicon (amorphous silicon; e.g. paragraph 92), microcrystalline silicon, and polycrystalline silicon.
Re claim 21: Nakamura in view of Wang and Yoon teaches the display panel according to claim 14, wherein the first electrode (129; e.g. paragraph 89 of Nakamura/206 of Yoon) is a single-layer structure or a multi-layer structure formed by at least one metal oxide material selected from indium zinc oxide, indium tin oxide (transparent electrode; e.g. paragraph 259 of Nakamura), zinc oxide, and gallium zinc oxide.
It would have been obvious to one of ordinary skill in the art, at the time of effective filing, absent unexpected results, to use the transparent electrode as taught by Nakamura for electrode 129 of Nakamura in order to have the predictable result of using a transparent electrode since it would prevent light from being blocked as shown in the device of fig. 4 of Nakamura.
Claim(s) 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura in view of Wang and Yoon as applied to claim 14 above, and further in view of Nomura et al. (US PGPub 2005/0025025; hereinafter “Nomura”).
Re claim 15: Nakamura in view of Wang and Yoon teaches substantially the entire structure as recited in claim 14 except explicitly teaching the display panel, wherein the display panel comprises: a first electrode layer disposed on the transparent substrate, wherein the first electrode layer comprises the first electrode and the gate; a gate insulation layer disposed on the first electrode layer; wherein the gate insulation layer exposes the first electrode; an active layer disposed on the gate insulation layer and overlapping the gate in the vertical direction, wherein the active layer comprises a non-doped region and two doped regions located on two sides of the non-doped region; a source and a drain disposed on the active layer and respectively connected to the two doped regions; an insulation layer disposed on the electron transport layer, the source, and the drain, wherein the insulation layer exposes the electron transport layer and the drain; and a second electrode disposed on one side of the electron transport layer away from the light absorption layer, wherein the second electrode is connected to the drain.
Nomura teaches (e.g. fig. 3C) the display panel wherein the display panel comprises: a first electrode layer (111_6 of Nakamura and 309 of Nomura) disposed on the transparent substrate (20 of Nomura and 100 of Nakamura), wherein the first electrode layer (111_6 of Nakamura and 309 of Nomura) comprises the first electrode (309 of Nomura which is equivalent to 129 of Nakamura) and the gate (111_4 of Nakamura); a gate insulation layer (102 of Nakamura and thin dielectric layer which covers 309, 311, 312, 313 of Nomura; hereinafter “GIL”) disposed on the first electrode layer (129 of Nakamura), wherein the gate insulation layer (GIL) exposes the first electrode (129 of Nakamura); an active layer (113_3 of Nakamura) disposed on the gate insulation layer (GIL) and overlapping the gate (111_4 of Nakamura) in the vertical direction, wherein the active layer (113_3 of Nakamura) comprises a non-doped region (113_3 of Nakamura) and two doped regions (114a_3, 114b_3 of Nakamura) located on two sides of the non-doped region (113_3 of Nakamura); a source and a drain (115a_3, 115b_3 of Nakamura) disposed on the active layer (113_3 of Nakamura) and respectively connected to the two doped regions (114a_3, 114b_3 of Nakamura); an insulation layer (221 of Nakamura/303 of Nomura) disposed on the electron transport layer (250c of Nakamura), the source (115a_3 of Nakamura), and the drain (115b_3 of Nakamura), wherein the insulation layer (221 of Nakamura/303 of Nomura) exposes the electron transport layer (250c of Nakamura) and the drain (115b_3 of Nakamura); and a second electrode (227 of Nakamura) disposed on one side of the electron transport layer (250c of Nakamura) away from the light absorption layer (250b of Nakamura), wherein the second electrode (227 of Nakamura) is connected to the drain (115b_3 of Nakamura).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the light sensing layer at the same level as the transistors as taught by Nomura in the device of Nakamura in view of Wang and Yoon in order to have the predictable result of using a structure which allows for a flatter disposition of the sensing elements and allows for a thinner overall device.
Re claim 16: Nakamura teaches the display panel according to claim 15, wherein the gate (111_3 of Nakamura), the active layer (113_1 of Nakamura), the source 115a_3 of Nakamura), and the drain (115b_3 of Nakamura) constitute a switching thin film transistor (153 of Nakamura), and the photoelectric sensor (250 of Nakamura) is connected to the switching thin film transistor (153 of Nakamura).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898