DETAILED ACTION
This Action is responsive to the Amendment filed on 05/26/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/26/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-2 and 4-14 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Claim 1 recites the limitation: “wherein each stacked layer has a single color solid state light source to thereby reduce routing complicity and distance between solid state light source(s).” It is unclear how each stack layer having a single color solid state light source reduces routing complicity and distance between solid state light source(s). Merely reciting a result achieved by the claimed invention is indefinite because the boundaries of the claimed scope are unclear.
Claims 2 and 4-14 are rejected under 35 U.S.C. 112(b) as being indefinite due to the claims’ dependency to Claim 1.
For purposes of compact prosecution, the Examiner will interpret the claimed limitation as each stacked layer having a single color solid state light source with a non-complicated connection to the printed circuit board and with a small separation distance between neighboring solid state light sources.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 8-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park (US 2016/0056345).
Regarding claim 1, Park (see, e.g., FIG. 7a) discloses a lighting device comprising:
a multi-layer PCB stack 210, 215, 225 comprising n stack layers 210, 215, 225, wherein n>2 e.g., number of layers of 210, 215, 225 greater than 2, wherein k layers 210, 100a; 215, 100b; 225, 100c of the n stacked layers 210, 215, 225 each comprise a PCB 210, 215, 225 with one or more solid state light source(s) 100a, 100b, 100c, and wherein each stacked layer 210, 215, 225 has a single color solid state light source 100a, 100b, 100c, e.g., red light emitting light sources to thereby reduce routing complicity and distance between solid state light source(s) 100a, 100b, 100c, wherein 2<k<n, e.g., number of k layers 210, 100a; 215, 100b; 225, 100c is greater than 2, wherein the solid state light sources 100a, 100b, 100c are configured to generate light source light, wherein the n layers 210, 215, 225 are shaped and stacked such that the light source light of the solid state light source 100a, 100b, 100c of any of the PCBs 210, 215, 225 is at least partly not physically blocked by any of the other PCBs 210, 215, 225 by applying a smaller PCB e.g., 225 in the n or k layer 225, 100c downstream of the k layer e.g., 210 comprising the solid state light source 100a (Para 0012-Para 0030, Para 0067, Para 0073, Para 0075-Para 0076, Para 0080-Para 0082, Para 0095-Para 0108, Para 0133-Para 0134);
wherein:
one or more of the k layers 215, 100b; 225, 100c configured downstream of a first light source 100a include one or more PCBs 215, 225 comprising one or more PCB holes e.g., opening in 215 (opening extending from left side lower portion to right side lower portion), opening in 225 (opening extending from left side portion to right side portion),
the PCB holes e.g., opening in 215 (opening extending from left side lower portion to right side lower portion), opening in 225 (opening extending from left side portion to right side portion), e.g., opening in 210 increase in size as the smaller PCB(s) 225 in the n or k layer 225, 100c downstream of the k layer e.g., 210, 100a comprising the solid state light source 100a are stacked,
the one or more PCB holes e.g., opening in 215 (opening extending from left side lower portion to right side lower portion), opening in 225 (opening extending from left side portion to right side portion) are configured downstream of the first light source 100a;
Examiner Note: Regarding the limitation “one or more solid state light source(s), wherein each stacked layer has a single color solid state light source to thereby reduce routing complicity and distance between solid state light source(s), the Examiner notes that the light emitting elements 100a, 100b, and 100c, e.g., red light emitting light sources are wire-bonded to their respective circuit boards 210, 215, and 225, which reduces complicated routing (Para 0073, Para 0078, Para 0102, Para 0133-Para 0134), and the distances between light emitting elements 100a, 100b, and 100c, e.g., red light emitting light sources are reduced to prevent generation of dark regions (Para 0011, Para 0067, Para 0082, Para 0095-Para 0096, Para 0133-Para 0134).
Regarding claim 2, Park (see, e.g., FIG. 7a) teaches lighting device according to claim 1, wherein one or more of the n layers 215, 225 configured downstream of a first light source 100a comprise one or more layer holes e.g., opening in 215 (opening extending from left side lower portion to right side lower portion), opening in 225 (opening extending from left side portion to right side portion), wherein the one or more layer holes e.g., opening in 215 (opening extending from left side lower portion to right side lower portion), opening in 225 (opening extending from left side portion to right side portion) are configured downstream of the first light source 100a.
Regarding claim 8, Park (see, e.g., FIG. 7a) teaches the lighting device according to claim 1, wherein each of the k layers 210, 100a; 215, 100b; 225, 100c comprise a plurality of light sources 100a, 100b, 100c (Para 0076, Para 0095, Para 0100).
Regarding claim 9, Park (see, e.g., FIG. 7a) teaches lighting device according to claim 8, wherein at least two of the k layers 215, 100b; 225, 100c each comprise a subset of light sources 100b, 100c of the respective plurality of light sources 100a, 100b, 100c, wherein the light sources 100b, 100c within each respective subset 100b, 100c are selected from a same bin e.g., same wavelength (Para 0133), and wherein the light sources of different subsets of different layers are selected from different bins.
Examiner note: Examiner notes that claim 1 provides the option of 2<k<n, where k is equal to or greater than 2. The option selected by the Examiner is k=2. Therefore, the option of k>2 does not apply to the selected option of k=2.
Regarding claim 10, Park (see, e.g., FIG. 7a) teaches lighting device according to claim 1, further comprising luminescent material configured in an entire one or more of the PCB holes or as a separate luminescent material comprising layer e.g., 150b between two n stacked layers e.g., 210, 225 (Para 0076), wherein the luminescent material 150b is configured to convert at least part of the light source light of the solid state light sources 100a, 100b, 100c configured upstream of the luminescent material 150b into luminescent material light (Para 0073, Para 0076, Para 0100).
Regarding claim 11, Park (see, e.g., FIG. 7a) teaches lighting device according to claim 10, wherein one or more of the following applies: (i) the luminescent material is comprised by the one or more PCB holes downstream of the one or more of the total number of solid state light sources, and (ii) n>2, e.g., n stack layers 210, 215, 225, and one or more of the layers 210, 215, 225 comprise the luminescent material e.g., phosphor material of 150a, 150b, 150c (Para 0073, Para 0076, Para 0100).
Regarding claim 12, Park (see, e.g., FIG. 7a) teaches lighting device according to claim 11, wherein the lighting device 200c is configured to generate lighting device light which comprises one or more (i) of the light source light of one or more of the light sources 100a, 100b, 100c and (ii) luminescent material light e.g., light emitted by 150a, 150b, 150c (Para 0073, Para 0076, Para 0095, Para 0100).
Regarding claim 13, Park (see, e.g., FIG. 7a) teaches a luminaire 200c comprising the lighting device according to claim 1 (Para 0095).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2016/0056345), in view of Lin (US 2019/0107271).
Regarding claim 4, although Park shows substantial features of the claimed invention, Park fails to expressly teach the lighting device according to claim 1, further comprising driver electronics, wherein the driver electronics are configured to control all solid-state light sources.
Lin (see, e.g., FIG. 1) teaches driver electronics 20, wherein the driver electronics 20 are configured to control all solid-state light sources 30 for the purpose of enabling the driver IC to control the LED chip in a most direct and shortest way (Para 0022-Para 0024, Para 0033-Para 0034).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the driver electronics as described by Lin to the device of Park for the purpose of enabling the driver IC to control the LED chip in a most direct and shortest way (Para 0033-Para 0034).
Regarding claim 5, the combination of Park (see, e.g., FIG. 7a) / Lin (see, e.g., FIG. 1-FIG. 3) teach the lighting device according to claim 4, wherein the driver electronics 20 (as taught by Lin) are comprised by or physically coupled to one of the n stacked layers 210, 215, 225 (as taught by Park) (Park: Para 0095; Lin: Para 0033).
Regarding claim 6, Lin (see, e.g., FIG. 1) teaches the lighting device according to claim 4, further comprising one or more vias e.g., blind holes for functionally coupling the light sources 30 and the driver electronics 20 (Para 0022).
Regarding claim 7, Park shows substantial features of the claimed invention; however, Park fails to specify the lighting device according to claim 1, wherein the solid-state light sources comprise dies having die areas of at maximum 1 mm2. Park, on the other hand, does teach that the height of the solid-state light sources 100a, 100b, 100c may be 90 µm to 100 µm (Para 0018). Lin (see, e.g., FIG. 1) teaches that the area of the solid-state light sources 30 are 0.15 mm x 0.15 mm (Para 0029). However, differences in area will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such area difference is critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph) of the dies having die areas of at maximum 1 mm2, it would have been obvious to one of ordinary skill in the art to modify the area of the dies in the device of Park.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed area of the dies or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 14, Lin (see, e.g., FIG. 1) teaches a lighting system comprising (i) the lighting device according to claim 4, wherein a control system 20 is configured to have the lighting device generate one or more of (a) white lighting system light e.g., monochrome light in a first controlling mode, and (b) colored system light in a second controlling mode (Para 0022, Para 0024, Para 0025, Para 0029).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571) 270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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