Prosecution Insights
Last updated: April 19, 2026
Application No. 17/434,863

SUBSTRATE FOR REMOVAL OF DEVICES USING VOID PORTIONS

Non-Final OA §103§112
Filed
Aug 30, 2021
Examiner
NIELSEN, DEREK LANG
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
The Regents of the University of California
OA Round
3 (Non-Final)
66%
Grant Probability
Favorable
3-4
OA Rounds
3y 9m
To Grant
99%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allow Rate
31 granted / 47 resolved
-2.0% vs TC avg
Strong +52% interview lift
Without
With
+51.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
29 currently pending
Career history
76
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
60.8%
+20.8% vs TC avg
§102
15.0%
-25.0% vs TC avg
§112
20.6%
-19.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 47 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 19, 2025 has been entered; claims 8, 9, 20 have been canceled, claims 1, 5, 7, 10, 12, 13, 14, 16, 17, 18, 19 have been amended, and new claim 21 has been added. Claims 1-7, 10, 12-19 and 21 are pending, with claim 7 currently withdrawn from consideration. Information Disclosure Statement The information disclosure statement (IDS) submitted on July 24, 2025 has been placed in the application file and is being considered by the examiner. Response to Amendment The amendments to the Claims filed May 19, 2025 have been entered. Applicant’s amendments to the Claims have failed to overcome each and every rejection set forth in the Office Action filed March 19, 2025. Response to Arguments Applicant's arguments filed May 19, 2025 have been fully considered but they are not persuasive. In response to applicant's arguments on pages 11-13 against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Specifically, Applicant argues on pages 11-12 that there is no discussion in Sumida of "an initial growth of the ELO III-nitride layers is higher than the growth restrict mask, subsequent growth of the ELO III nitride layers from the initial growth coalesce to create one or more triangular voids between a surface of the substrate and a surface of the ELO III-nitride layers, and the triangular voids occur directly on the growth restrict mask and are surrounded by the growth restrict mask and the ELO III-nitride layers." Applicant argues on page 13 that Applicant's claimed invention differs from Wierer in reciting "growing one or more epitaxial lateral overgrowth (ELO) III-nitride layers through opening areas in a growth restrict mask deposited on or above a substrate, wherein an initial growth of the ELO III-nitride layers is higher than the growth restrict mask, subsequent growth of the ELO III-nitride layers from the initial growth coalesce to create one or more triangular voids between a surface of the substrate and a surface of the ELO III-nitride layers, and the triangular voids occur directly on the growth restrict mask and are surrounded by the growth restrict mask and the ELO III-nitride layers." These arguments are not persuasive because, as explained in the rejection of claim 1 below, the rejection of claim 1 is not based on either Sumida or Wierer individually, but is instead based on the combination of the references. For example, Sumida, FIG. 18A shows GaN-based semiconductor layers 30 [the initial growth of the ELO III-nitride layers] is higher than the growth mask 20 [the growth restrict mask], and Sumida teaches that the growth conditions result in “inverted pyramid shape,” i.e., triangular shapes, at boundaries between each of GaN-based semiconductor layers 30 [the coalescence region of the ELO III-nitride layers] [0034-0035]; and that the “plurality of island-shaped GaN-based semiconductor layers 30 [the ELO III-nitride layers] individually serve as a base substrate for forming a semiconductor element,” [0039]. Additionally, as explained in the rejection of claim 1 below, Wierer, FIG. 9 shows gaps 76 [the triangular voids] directly on mask layer 70 [the growth restrict mask] and surrounded by mask layer 70 [the growth restrict mask] and semiconductor region 40 [the ELO III-nitride layers]. It would have been obvious to a person having ordinary skill in the art to combine the teachings of Sumida with the teachings of Wierer because, as expressly recognized by Sumida, the technique of growing one or more device layers on or above the ELO III-nitride layers; etching the ELO III-nitride layers and the device layers above the voids to at least expose the voids; and removing a bar comprised of the ELO III-nitride layers and the device layers from the substrate at the exposed voids was known in the art, and, as expressly recognized by Wierer, the additional ELO III-nitride device layers applied over the triangular voids is advantageous insofar as preserving the gaps between the voids, thereby resulting in improvements to device manufacturing and reliability. In response to Applicant’s argument on page 14 that the dependent claims are patentably distinct over the prior art, and are also allowable based at least on their dependency from the independent claim 1, as amended, see the rejections of the claims below. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claim 10 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 10 merely recites properties resulting from the method of claim 1, for example “the triangular voids release stress,” but fails to recite any additional structure or any additional method steps to further limit the subject matter of claim 1. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6, 12-16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sumida et al., JP2013251304A (hereinafter Sumida) in view of Wierer, Jr. et al., US 2006/0284187 A1 (hereinafter Wierer). Regarding claim 1, as amended, Sumida teaches: A method, comprising: growing one or more epitaxial lateral overgrowth (ELO) III-nitride layers (Sumida, FIG. 18, GaN-based semiconductor layers 30, [0039]) through opening areas in a growth restrict mask (Sumida, FIG. 18, openings 21 in growth mask 20, [0038]) deposited on or above a substrate (Sumida, FIG. 18A shows growth mask 20 [the growth restrict mask] on substrate 10), wherein an initial growth of the ELO III-nitride layers is higher than the growth restrict mask (Sumida, FIG. 18A shows GaN-based semiconductor layers 30 [the initial growth of the ELO III-nitride layers] is higher than the growth mask 20 [the growth restrict mask]), subsequent regrowth of the ELO III-nitride layers from the initial growth coalesces to create one or more (Sumida, FIG. 18B shows voids between upper surface of substrate 10 [the substrate] and lower surface of each of GaN-based semiconductor layers 30 [the ELO III-nitride layers] after etching, [0093]), Sumida teaches that the growth conditions result in “inverted pyramid shape,” i.e., triangular shapes, at boundaries between each of GaN-based semiconductor layers 30 [the coalescence region of the ELO III-nitride layers] [0034-0035]; and that the “plurality of island-shaped GaN-based semiconductor layers 30 [the ELO III-nitride layers] individually serve as a base substrate for forming a semiconductor element,” [0039] but is silent regarding: triangular voids which occur directly on the growth restrict mask and are surrounded by the growth restrict mask and the ELO III-nitride layers; growing one or more III-nitride device layers on or above the ELO III-nitride layers; etching the ELO III-nitride layers and the III-nitride device layers above the triangular voids to at least expose the triangular voids; and removing a bar comprised of the ELO III-nitride layers and the III-nitride device layers from the substrate at the exposed triangular voids. However, Wierer, in the same field of endeavor, teaches: the triangular voids occur directly on the growth restrict mask (Wierer, FIG. 9, gaps 76) and are surrounded by the growth restrict mask and the ELO III-nitride layers (Wierer, FIG. 9 shows gaps 76 [the triangular voids] directly on mask layer 70 [the growth restrict mask] and surrounded by mask layer 70 [the growth restrict mask] and semiconductor region 40 [the ELO III-nitride layers]); growing one or more III-nitride device layers (Wierer, FIG. 9, semiconductor region 40, “a layer that preserves the gaps 76 between pyramids 74, but ends in a planar, uninterrupted surface at the top, may be grown over pyramids 74,” [0053]) on or above the ELO III-nitride layers (Wierer, FIG. 9, shows semiconductor region 40 above p-type material 72, i.e. the ELO III-nitride layers, [see 0053-0054]). Neither Sumida or Wierer explicitly teach: etching the ELO III-nitride layers and the III-nitride device layers above the triangular voids to at least expose the triangular voids; and removing a bar comprised of the ELO III-nitride layers and the III-nitride device layers from the substrate at the exposed triangular voids. However, Sumida teaches that after growth of the GaN-based semiconductor islands 30 [the ELO III-nitride layer], a semiconductor device layer 50 [analogous to the III-nitride device layers] is formed, (Sumida, FIG. 20 shows GaN-based semiconductor layers 30 [the ELO III-nitride layers] and semiconductor device layers 50 [analogous to the III-nitride device layers] after etching to expose the voids, [0095-0096]). A person having ordinary skill in the art would have recognized from FIG. 20 of Sumida that the etch process resulting from the teachings of Sumida in view of Wierer exposes the triangular voids (see Sumida, [0095-0096]). Furthermore, Sumida in view of Wierer teaches that “[a]fter the device formation step S25, similarly, the growth mask 20 may be removed by wet etching, and the GaN-based semiconductor layer 30 [the ELO III-nitride layers] on which the semiconductor device 50 [analogous to the III-nitride device layers] is formed may be lifted off,” i.e., removing a bar comprised of the ELO III-nitride layers and the III-nitride device layers from the substrate at the exposed triangular voids, (Sumida, FIGs. 18C and 20, [0096]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sumida with the teachings of Wierer because, as expressly recognized by Sumida, the technique of growing one or more device layers on or above the ELO III-nitride layers; etching the ELO III-nitride layers and the device layers above the voids to at least expose the voids; and removing a bar comprised of the ELO III-nitride layers and the device layers from the substrate at the exposed voids was known in the art, and would be achievable with a high likelihood of success and without undue experimentation, and would be motivated to do so because, as expressly recognized by Wierer, the additional ELO III-nitride device layers applied over the triangular voids is advantageous insofar as preserving the gaps between the voids, thereby resulting in improvements to device manufacturing and reliability. Regarding claim 2, Sumida in view of Wierer teaches: The method of claim 1, wherein the ELO III-nitride layers include a regrowth layer and/or a flattening layer (Wierer, “after p-type posts 30 are grown, the growth conditions are changed such that inverted pyramids are formed over the posts, which pyramids eventually connect to form a planar layer 32 [i.e., a flattening layer],” [0037]). Regarding claim 3, Sumida in view of Wierer teaches: The method of claim 2, wherein the regrowth layer and/or the flattening layer includes Magnesium (Mg) (Wierer, in describing the growth of planar layer 32, teaches that the use of Magnesium is known in the art, “Hoffouz et al., incorporated above, describes lateral overgrowth techniques for p-type Mg-doped III-nitride materials,” [0037]). Regarding claim 4, Sumida in view of Wierer teaches: The method of claim 2, wherein the ELO III-nitride layers are polished after growth of the regrowth layer (Wierer, once the growth substrate 20 is removed, n-type region [i.e., the ELO III-nitride layers] may be thinned to a desired thickness [i.e., polished],” [0041]). Regarding claim 5, as amended, Sumida in view of Wierer teaches: The method of claim 1, wherein the bar does not contain a center of the triangular voids (Sumida, FIGs. 18 and 20; Wierer, see FIG. 9). Regarding claim 6, Sumida in view of Wierer teaches: The method of claim 1, wherein one or more devices are fabricated from the bar (Sumida, “Schottky diode, a light emitting diode, a semiconductor laser, a photodiode, a transistor or the like,” i.e., devices are fabricated from the bar,” [0095]). Regarding claim 12, as amended, Sumida in view of Wierer teaches: The method of claim 1, wherein a depressed portion at a no-growth region is buried by the subsequent regrowth of the III-nitride layers, which flattens a surface of the regrowth layer (Wierer, “after p-type posts 30 are grown, the growth conditions are changed such that inverted pyramids are formed over the posts, which pyramids eventually connect to form a planar layer 32 [i.e., the subsequent regrowth of the III-nitride layers flattens a surface of the regrowth layer],” [0037]). Regarding claim 13, as amended, Sumida in view of Wierer teaches: The method of claim 1, wherein the subsequent regrowth of the III-nitride layers is doped with Magnesium (Mg) (Wierer, in describing the growth of planar layer 32, teaches that the use of Magnesium is known in the art, “Hoffouz et al., incorporated above, describes lateral overgrowth techniques for p-type Mg-doped III-nitride materials,” [0037]) to reduce a number of holes at a surface of the subsequent regrowth of the III-nitride layers. While features of a device may be recited either structurally or functionally, claims directed to a device must be distinguished from the prior art in terms of structure rather than function or intended use. See MPEP 2114; see also MPEP 2103(C), generally. The intended function or use of a claimed structure is given patentable weight only so far as the structure is capable of performing that function or capable of the intended use. This capability is compared against the prior art, as opposed to prior teachings of the particular function or use. The claim language “to reduce a number of holes at a surface of the subsequent regrowth of the III-nitride layers” has not been given full patentable weight because it is merely descriptive of an intended use or function. Moreover, the claim language “to reduce a number of holes at a surface of the subsequent regrowth of the III-nitride layers” simply expresses the intended result of a process step and does not distinguish the claimed process over the lateral overgrowth technique for p-type Mg-doped III-nitride materials, as taught by Wierer, which is recognized as capable of reducing a number of holes at a surface of the subsequent regrowth of the III-nitride layers. Regarding claim 14, as amended, Sumida in view of Wierer teaches: The method of claim 1, wherein the triangular voids are formed by: optimizing growth conditions during the growth of the ELO III-nitride layers to make the triangular voids in the ELO III-nitride layers without removing a growth restrict mask (Sumida, FIGs. 2-3, growth conditions optimized to increase growth in the lateral direction, [0052]; Wierer, see FIG. 9, “pyramids result when III-nitride material is grown conventionally through openings in a mask,” [0053]). Regarding claim 15, Sumida in view of Wierer teaches: The method of claim 14, wherein the growth conditions form facets at an edge of the ELO III-nitride layers, and the facets comprise inverted taper shapes (Sumida, growth conditions result in “inverted pyramid shape,” i.e., inverted taper shapes, [0034-0035]). Regarding claim 16, as amended, Sumida in view of Wierer teaches: The method of claim 15, wherein the inverted taper shapes create the triangular voids that are triangular shapes at a coalescence region of the ELO III-nitride layers (Sumida, growth conditions result in “inverted pyramid shape,” i.e., triangular shapes, at boundaries between each of GaN-based semiconductor layers 30 [the coalescence region of the ELO III-nitride layers] [0034-0035]). Regarding claim 19, as amended, Sumida in view of Wierer teaches: The method of claim 1, further comprising smoothing the surface of the ELO III-nitride layers (Sumida, GaN-based semiconductor layers 30 [the ELO III-nitride layers] planarized, i.e., smoothed, [0035]; Wierer, once the growth substrate 20 is removed, n-type region [i.e., the ELO III-nitride layers] may be thinned to a desired thickness [i.e., smoothed],” [0041]). Claims 10, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Sumida in view of Wierer, and further in view of Usui et al., US 2006/0046325 A1 (hereinafter Usui). Regarding claim 10, Sumida in view of Wierer teaches every element of claim 10 but is silent regarding: wherein the triangular voids release stress resulting from the growth restrict mask. However, Usui, in disclosing a group III nitride semiconductor layer with a region of voids formed over a substrate, teaches “the region of voids functions as a region for strain-relaxing [i.e., the voids release stress], and thereby it will improve the quality of the group III nitride semiconductor layer formed thereon,” [0034] and the voids can “successfully relax the strain due to the difference in lattice constant or thermal expansion coefficient between base substrate and group III nitride semiconductor layer,” [0038]. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sumida in view of Wierer with the teachings of Usui because Usui expressly recognizes that the quality of the group III nitride semiconductor layer is improved by the stress relieving property of the voids, and a person having ordinary skill in the art would therefore have been able to arrive at Applicant’s claimed method with a high likelihood of success and without undue experimentation. Regarding claim 17, as amended, Sumida in view of Wierer, and further in view of Usui teaches: The method of claim 1, wherein stress is applied to separate the bar from the substrate (Usui, “the removal of substrate is easily performed, whereby such a self-supported substrate of GaN single crystal [i.e., the bar] can be easily obtained that has a large size, is free from crack or flaw and is well shaped. It is because a layer having voids is lying between a base substrate and a group III nitride semiconductor layer, which enables easy removal of the base substrate by spontaneous peeling, or by means of chemical solution or mechanical impact [i.e., stress is applied to separate the bar from the substrate].” [0040]). Regarding claim 18, as amended, Sumida in view of Wierer, and further in view of Usui teaches: The method of claim 17, wherein the stress is applied at the triangular voids (Usui, “the removal of substrate is easily performed ... by means of ... mechanical impact [i.e., stress is applied at the triangular voids],” [0040]). Claims 21 is rejected under 35 U.S.C. 103 as being unpatentable over Sumida in view of Wierer, as applied to claim 1 above, and further in view of Beaumont et al., US 2011/0316000 A1 (hereinafter Beaumont). Regarding claim 21, Sumida in view of Wierer teaches: The method of claim 1, wherein: the initial growth of the ELO III-nitride layers is stopped before the ELO III-nitride layers coalesce resulting in no growth regions (Wierer, FIG. 9, “growth is stopped before gaps 76 between pyramids 74 are filled in [i.e., before the ELO III-nitride layers coalesce],” [0053]); the subsequent regrowth of the ELO III-nitride layers coalesces to create the triangular voids between the surface of the substrate and the surface of the ELO III-nitride layers in the no-growth regions (Wierer, FIG. 9, semiconductor region 40, “a layer that preserves the gaps 76 [the triangular voids] between pyramids 74, but ends in a planar, uninterrupted surface at the top, may be grown over pyramids 74,” [0053]); Neither Sumida nor Wierer explicitly teach: the etching of the ELO III-nitride layers and the III-nitride device layers above the triangular voids exposes areas of the growth restrict mask in the no-growth regions; and the exposed areas of the growth restrict mask in the no-growth regions are etched to remove the bar comprised of the ELO III-nitride layers and the III-nitride device layers from the substrate. However, Beaumont, in the same field of endeavor, teaches that after ELO III-nitride layers coalesce to create triangular voids, i.e., after the subsequent regrowth, a new mask is applied on top of the grown layer, “this mask is patterned with opening area exactly aligned on the first openings required for the ELO technology [i.e., a person having ordinary skill in the art would have recognized that the mask openings align with the voids formed during growth of the ELO III-nitride layers],” then “deep etching through the openings is carried out by RIE approximately down to the sapphire substrate [i.e., to at least expose the voids],” [see 0096-0099]. Furthermore, Beaumont teaches that the process disclosed therein produces “a GaN freestanding crystal separated from the substrate,” i.e., the bar comprised of the ELO III-nitride layers and the III-nitride device layers from the substrate at the exposed voids [see 0118-0119]. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Beaumont with the teachings of Sumida in view of Wierer because, as expressly recognized by Beaumont, the technique of applying a mask, etching one or more III-nitride layers to expose the voids, and removing a bar comprised of the multiple ELO III-nitride layers from the substrate at the exposed voids was known in the art, and would be achievable with a high likelihood of success and without undue experimentation, and would be motivated to do so because the additional ELO III-nitride layer applied over the voids is advantageous insofar as preserving the gaps between the voids, thereby resulting in improvements to device manufacturing and reliability. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEREK NIELSEN whose telephone number is (703)756-1266. The examiner can normally be reached Monday - Friday, 8:30 A.M. - 5:30 P.M.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRENT A FAIRBANKS can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.L.N./Examiner, Art Unit 2899 /Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Aug 30, 2021
Application Filed
May 04, 2024
Non-Final Rejection — §103, §112
Nov 29, 2024
Response Filed
Mar 13, 2025
Final Rejection — §103, §112
May 19, 2025
Response after Non-Final Action
Jun 20, 2025
Request for Continued Examination
Jun 23, 2025
Response after Non-Final Action
Oct 28, 2025
Non-Final Rejection — §103, §112 (current)

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Expected OA Rounds
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Grant Probability
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3y 9m
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