DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/19/25 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Status
Claims 9-28 are under consideration in this application.
Claim 1-8 were canceled in the response of 11/26/24.
Information Disclosure Statement
Applicant’s IDS submitted on 11/26/24 and 9/7/21 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have been considered by the examiner and made of record.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-13, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al., US 20190326312 A1, hereafter Zhou in view of Liu et al., US 20200035699 A1, hereafter Liu.
Regarding claim 9, Zhou discloses the following limitations:
A method of manufacturing a three-dimensional flash memory, the method comprising:
forming a plurality of word lines (Zhou, Figure 2, second dielectric layers 110b, in alternating stack 110, and [0035] which discloses that the conductor of the alternating conductor/dielectric stack can be used as a word line, and [0049] discloses the replacement of the oxide with a conductive material), a plurality of insulating layers (Zhou, Figure 2, first dielectric layers 110a of alternating stack 110) stacked in a vertical direction, wherein an upper word line group includes a first word lines among the plurality of word lines and a first insulating layers among the plurality of insulating layers (Zhou, Figure 2, second sub-region 114, and [0051]), the first word lines and the first insulating layers are alternately stacked, and lower word line group includes a second word lines among the plurality of word lines and a second insulating layers among the plurality of insulating layers (Zhou, Figure 2, first sub-region 112, and [0051]), and the second word lines and the second insulating layers are alternately stacked, wherein the upper word line group and the lower word line group have different horizontal sizes and are stacked in order in a first stair shape such that at least a portion of an upper surface of each of the upper and lower word line groups is exposed (Zhou Figure 2, shows 114 and 112 forming a stair shape, and the upper surface of both regions are exposed);
forming photoresists on at least a portion of the upper surface of the upper word line group and at least a portion of the upper surface of the lower word line group (Zhou, Figure 6, photoresist layer 130 is formed on the top of both 112 and 114); and
simultaneously performing an etching operation on each of the upper word line group and the lower word line group (Zhou, Figure 6, staircases 200, and [0062] and [0054]–[0057] disclose that an etch-trim process is used to from staircases in the first region and the second region simultaneously), (Zhou, Figure 6, staircases 200 are formed in both 112 and 114),
Liu disclose the following limitations:
an etch stopper protection layer (Liu, Figure 9, joint insulating material layer 810, where layer 810 is an etch stopper layer because 810 is on top of the lower stack and would therefore necessarily prevent the lower stack from being etched because it prevents the etchant from contacting the lower stack.)
and the etch stopper protection layer is formed between the upper word line group and the lower word line group (Liu, Figure 9, joint insulating material layer 810 is between the first dielectric stack 803 and the second dielectric stack 906, and [0123]) and the etch stopper protection layer is different from the plurality of insulating layers (Liu, Figure 9, joint insulating material layer 810 is a different layer from insulating material layer 902),
which are provided with the etch stopper protection layer therebetween (Liu, Figure 9, 810 is between 803 and 906, and Figure 10 and 11 show that the upper and lower stack are joined prior to etching them)
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Liu to the process of Zhou and to therefore have formed an insulating material layer between the upper and lower stacks. Doing so is taught by Liu to provide numerous benefits, including, but not limited to simplifying the fabrication process, reducing the size of the three-dimensional memory device, and improving the space utility of the chip which the three-dimensional memory device is formed on (these advantages are disclosed by Liu in [0004]). Regarding the limitation “wherein after forming the second stair shape, a maximum width in a horizontal direction of the etch stopper protection layer is the same as a maximum width in the horizontal direction of a lowermost word line of the upper word line group” it would have been obvious to one of ordinary skill when combining the stack of the upper and lower word layers as in Figure 2 of Zhou, with the joint insulating material layer of Liu to have etched the joint insulating material layer to be the width of second sub-region 114. Doing so would expose the top of the first sub-region 112 of Zhou, allowing the mask of Zhou to be formed and would allow the upper and lower layers to be etched as taught by Zhou, using similar etch times and conditions for the second sub-region 114 and the first sub-region 112.
Regarding claim 10, Zhou further discloses the following limitations:
The method of claim 9, wherein the lower word line group (Zhou, Figure 2, 112 and [0051]) has a greater horizontal size than the upper word line group (Zhou, Figure 2, 114 and [0051]).
Regarding claim 11, Zhou and Liu further discloses the following limitations:
The method of claim 9, wherein the forming of the plurality of word lines, the plurality of insulating layers, and the etch stopper protection layer comprises:
determining a horizontal size of the lower word line group to include an etch stopper distance to prevent etching of a lowermost word line of the upper word line group when the etching operation is performed on the lower word line group (Zhou and Liu in combination would have the insulating material layer of Liu between the first sub-region 112 and second subregion 114, and the insulating material layer of Liu is an etch stopper that prevents etching of the lower word lines because block the lower word lines from the etchant).
Regarding claim 12, Zhou and Liu further discloses the following limitations:
The method of claim 9, wherein the etch stopper protection layer between the upper word line group and the lower word line group (Zhou and Liu in combination teach to include an insulation layer between the upper and lower stack) prevents etching of an uppermost word line of the lower word line group when the etching operation is performed on the upper word line group (The insulation layer of Liu, used combination with Zhou, protects the uppermost worldline because it physically blocks the word line from the etchant).
Regarding claim 13, Zhou further discloses the following limitations:
The method of claim 9, wherein the simultaneously performing of the etching operation on each of the upper word line group and the lower word line group is repeatedly performed (Zhou, [0057] discloses that multiple etch-trim processes can be performed repeatedly) based on a number of steps whereby the first word lines included in the upper word line group are stacked and a number of steps whereby the second word lines included in the lower word line group are stacked (Zhou, Figure 10, [0062] discloses that each staircase can include a number n of layers, and each step has a width of n×W/T, where W is the width of the stair region and T is the total number of layers in the stack).
Regarding claim 22, Zhou and Liu further disclose the following limitations:
The method of claim 9, wherein a width of the etch stopper protection layer before the simultaneously performing the etching operation is the same as a width of the etch stopper protection layer after the simultaneously performing the etching operation (Zhou discloses (Figure 2, and [0051]-[0052] etching the stack into a staircase with each region having half of the width and then discloses hard mask layer 120 can be formed to cover the top surfaces of the two step-platforms of the alternating layer stack 110 (Figure 3, hard mask layer 120). Therefore in the combination of Zhou and Liu the oxide layer would be removed so that hard mask layer 120 can be formed as required.
Claim 25 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou and Liu as applied to claim 9 above, and further in view of Guo 10566336 B1, hereafter Guo.
Regarding claim 25, Zhou and Liu disclose the following limitations:
The method of claim 9, wherein the forming the plurality of word lines and the etch stopper protection layer comprises forming a stair shape (Zhou, Figure 10 staircases 200, in combination with Liu as applied above to include the insulation layer between the upper and lower stack) using the plurality of word lines and the etch stopper protection layer, the stair shape including first portions having an equally spaced width and an equally spaced height (Zhou, Figure 10, and [0068]-[0070] disclose uniform steps, in combination with Liu as applied above to include the insulation layer between the upper and lower stack)
Zhou and Lui fail to disclose the following limitations:
a second portion having a different height from the first portions,
and wherein the second portion having the different height is formed by the etch stopper protection layer.
Gou disclose the following limitations:
a second portion having a different height from the first portions (Figure 4A, discloses a difference in step layer due to joint layer 212),
having the different height is formed by the etch stopper protection layer (Figure 4A, discloses a difference in step layer due to joint layer 212).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Gou to the process of Zhou and Lui because Lui teaches to use an oxide layer between the upper and lower stacks, but fails to show how to form the steps with an oxide layer between the stacks. Gou, who makes a similar device with an oxide layer between the upper and lower stacks, shows how to account for the additional width of the oxide layer when forming a stair shaped memory device. One of ordinary skill the art could have used the teaching of Gou to the device of Zhou and Lui and therefore have formed a larger vertical step where the oxide layer is doing so is taught by Gou and would result in a memory device of the smallest width, since separate step would be form of only the oxide layer.
Regarding claim 26, Zhou, Liu, and Gou further disclose the following limitations:
The method of claim 25, wherein forming the stair shape includes a third portion having a different width from the first portions, and wherein the third portion having the different width is formed by an etch stopper distance (Zhou, [0071] discloses forming steps that have width equal to 2nxmxW/T [0071], this is larger than the first steps that have width of the portion substantially equals to n×W/T, where this extra area is an “etch stopper distance” because it prevents etching of the word lines below it.)
Claims 14-18, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al., US 20190326312 A1, hereafter Zhou in view of Liu et al., US 20200035699 A1, hereafter Liu.
Regarding independent claim 14, Zhou discloses the following limitations:
A method of manufacturing a three-dimensional flash memory, the method comprising:
forming a plurality of word lines (Zhou, Figure 2, second dielectric layers 110b, in alternating stack 110, and [0035] which discloses that the conductor of the alternating conductor/dielectric stack can be used as a word line, and [0049] discloses the replacement of the oxide with a conductive material), a plurality of insulating layers (Zhou, Figure 2, first dielectric layers 110a of alternating stack 110), stacked in a vertical direction, wherein an upper word line group includes a first word lines among the plurality of word lines and a first insulating layers among the plurality of insulating layers (Zhou, Figure 2, second sub-region 114, and [0051]), the first word lines and the first insulating layers are alternately stacked, and lower word line group includes a second word lines among the plurality of word lines and a second insulating layers among the plurality of insulating layers (Zhou, Figure 2, first sub-region 112, and [0051]), and the second word lines and the second insulating layers are alternately stacked, wherein the upper word line group and the lower word line group have different horizontal sizes and are stacked in order in a first stair shape such that at least a portion of an upper surface of each of the upper and lower word line groups is exposed (Zhou Figure 2, shows 114 and 112 forming a stair shape, and the upper surface of both regions are exposed);
forming photoresists on at least a portion of the upper surface of the upper word line group and at least a portion of the upper surface of the lower word line group (Zhou, Figure 6, photoresist layer 130 is formed on the top of both 112 and 114); and
simultaneously performing an etching operation on each of the upper word line group and the lower word line group (Zhou, Figure 6, staircases 200, and [0062] and [0054]–[0057] disclose that an etch-trim process is used to from staircases in the first region and the second region simultaneously), on which the photoresists are formed, to form a second stair shape such that at least a portion of an upper surface of each of the first word lines and the second word lines is exposed (Zhou, Figure 6, staircases 200 are formed in both 112 and 114),
Zhou fails to disclose the following limitations:
and the etch stopper protection layer is formed between the upper word line group and the lower word line group and the etch stopper protection layer is different from the plurality of insulating layers,
providing a vertical string comprising a channel layer and a charge storage layer, the vertical string extending through the upper word line group, the etch stopper protection layer, and the lower word line group;
which are provided with the etch stopper protection layer therebetween
wherein after forming the second stair shape, a maximum width in a horizontal direction of the etch stopper protection layer is the same as a maximum width in the horizontal direction of a lowermost word line of the upper word line group.
Liu disclose the following limitations:
an etch stopper protection layer (Liu, Figure 9, joint insulating material layer 810, where layer 810 is an etch stopper layer because 810 is on top of the lower stack and would therefore necessarily prevent the lower stack from being etched because it prevents the etchant from contacting the lower stack.)
wherein and the etch stopper protection layer is formed between the upper word line group and the lower word line group (Liu, Figure 9, joint insulating material layer 810 is between the first dielectric stack 803 and the second dielectric stack 906, and [0123])and the etch stopper protection layer is different from the plurality of insulating layers (Liu, Figure 9, joint insulating material layer 810 is a different layer than insulating material layer 902),
providing a vertical string (Figure 8 sub-channels 805 and Figure 10, semiconductor channels 1001, containing channel-forming layers 802 [0115], and 1004 [0118]) comprising a channel layer and a charge storage layer ([0115] and [0118] discloses 802, and 1004, contain charge trapping film, semiconductor channel film, and dielectric core), the vertical string (Figure 10, semiconductor channels 1001) extending through the upper word line group, the etch stopper protection layer, and the lower word line group (Shown in Figure 10);
which are provided with the etch stopper protection layer therebetween (Liu, Figure 9, 810 is between 803 and 906, and Figure 10 and 11 show that the upper and lower stack are joined prior to etching them)
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Liu to the process of Zhou and to therefore have formed vertical string containing a channel layer and a charge storage layer, and an insulating material layer between the upper and lower stacks. Doing so is taught by Liu to provide numerous benefits, including, but not limited to simplifying the fabrication process, reducing the size of the three-dimensional memory device, and improving the space utility of the chip which the three-dimensional memory device is formed on (Liu discloses these advantages in [0004]). Regarding the limitation “wherein after forming the second stair shape, a maximum width in a horizontal direction of the etch stopper protection layer is the same as a maximum width in the horizontal direction of a lowermost word line of the upper word line group” it would have been obvious to one of ordinary skill when combining the stack of the upper and lower word layers as in Figure 2 of Zhou, with the joint insulating material layer of Liu, to have etched the joint insulating material layer to be the width of second sub-region 114. Doing so would expose the top of the first sub-region 112 of Zhou, and would therefore allow the mask of Zhou to be formed as required and allow the upper and lower layers to be etched as taught by Zhou, using similar etch times and conditions for the second sub-region 114 and the first sub-region 112.
Regarding claim 15, Zhou further discloses the following limitations:
The method of claim 14, wherein a horizontal width of the lower word line group (Zhou, Figure 2, 112 and [0051]) is greater than a horizontal width of the upper word line group (Zhou, Figure 2, 114 and [0051]).
Regarding claim 16, the combination of Zhou and Liu further discloses the following limitations:
The method of claim 14, wherein the forming of the plurality of word lines, the plurality of insulating layers, and the etch stopper protection layer comprises:
determining a horizontal width of the lower word line group to include an etch stopper distance to prevent etching of the lowermost word line of the upper word line group when the etching operation is performed on the lower word line group (Zhou and Liu in combination would have the insulation layer of Liu between the first sub-region 112 and second subregion 114, and the insulation layer is an etch stopper that prevents etching of the lower word lines because block the lower word lines from the etchant).
Regarding claim 17, the combination of Zhou and Liu further discloses the following limitations:
The method of claim 14, wherein the etch stopper protection layer between the upper word line group and the lower word line group (Zhou and Liu in combination teach to include an insulation layer between the upper and lower stack) prevents etching of an uppermost word line of the lower word line group when the etching operation is performed on the upper word line group (The insulation layer of Liu, used combination with Zhou, protects the uppermost worldline because it physically blocks the word line from the etchant).
Regarding claim 18, Zhou further discloses the following limitations:
The method of claim 14, wherein the simultaneously performing of the etching operation on each of the upper word line group and the lower word line group is repeatedly performed (Zhou, [0057] discloses that multiple etch-trim processes can be performed repeatedly) based on a number of steps whereby the first word lines included in the upper word line group are stacked and a number of steps whereby the first second lines included in the lower word line group are stacked (Zhou, Figure 10, [0062] discloses that each staircase can include a number n of layers, and each step has a width of n×W/T, where W is the width of the stair region and T is the total number of layers in the stack).
Regarding claim 23, Zhou further discloses the following limitations:
The method of claim 14, wherein a width of the etch stopper protection layer before the simultaneously performing the etching operation is the same as a width of the etch stopper protection layer after the simultaneously performing the etching operation (Zhou, Figure 2, and [0051]-[0052]) etching the stack into a staircase with each region having half of the width and then discloses hard mask layer 120 can be formed to cover the top surfaces of the two step-platforms of the alternating layer stack 110 (Figure 3, hard mask layer 120). Therefore in the combination of Zhou and Liu the oxide layer would be removed so that hard mask layer 120 can be formed as required).
wherein a maximum width in a horizontal direction of the etch stopper protection layer is the same as a maximum width in the horizontal direction of a lowermost word line of the upper word line group (In the combination of Zhou and Liu the etch stopper layer has a width that is the same as the lowest word line of the upper layer).
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Zhou and Liu as applied to claim 9 above, and further in view of Guo 10566336 B1, hereafter Guo.
Regarding claim 27, Zhou and Liu disclose the following limitations:
The method of claim 14, wherein the forming the plurality of word lines and the etch stopper protection layer comprises forming a stair shape (shown, Zhou, Figure 10 staircases 200) using the plurality of word lines and the etch stopper protection layer, the stair shape including first portions having an equally spaced width and an equally spaced height (Zhou, Figure 10, and [0068]-[0070] disclose uniform steps)
Zhou and Lui fail to disclose the following limitations:
a second portion having a different height from the first portions, and
wherein the second portion having the different height is formed by the etch stopper protection layer.
Gou disclose the following limitations:
having the different height is formed by the etch stopper protection layer (Figure 4A, discloses a difference in step layer due to joint layer 212).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Gou to the process of Zhou and Lui because Lui teaches to use an oxide layer between the upper and lower stacks, but fails to show how to form the steps with an oxide layer between the stacks. Gou, who makes a similar device with an oxide layer between the upper and lower stacks, shows how to account for the additional width of the oxide layer when forming a stair shaped memory device. One of ordinary skill the art could have used the teaching of Gou to the device of Zhou and Lui and therefore have formed a larger vertical step where the oxide layer is doing so is taught by Gou and would result in a memory device of the smallest width, since separate step would be form of only the oxide layer.
Claims 19-21, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al., US 20190326312 A1, hereafter Zhou in view of Liu et al., US 20200035699 A1, hereafter Liu.
Regarding independent claim 19, Zhou discloses the following limitations:
A method of manufacturing a three-dimensional flash memory, the method comprising:
forming an upper word line group including a first word lines and a first insulating layers alternately stacked in a vertical direction, (Zhou, Figure 2, second sub-region 114 of alternating stack 110, [0051] discloses that the stack be divided into two sub-regions, and [0035] which discloses that the conductor of the alternating conductor/dielectric stack can be used as a word line), a lower word line group including a second word lines and a second insulating layers alternately stacked in the vertical direction, (Zhou, Figure 2, first sub-region 112 of alternating stack 110),
forming photoresists (Zhou, Figure 6, photoresist layer 130) on at least a portion of an upper surface of the upper word line group and at least a portion of an upper surface of the lower word line group (Zhou, Figure 6, 130 is formed on both 112 and 114); and
simultaneously performing an etching operation on each of the upper word line group and the lower word line group, and on which the photoresists are formed to form a stair shape such that at least a portion of an upper surface of each of the first word lines and the second word lines is exposed, (Zhou, Figure 6, staircases 200, and [0062] and [0054]–[0057] disclose that an etch-trim process is used to from staircases in the first region and the second region simultaneously),
wherein a horizontal width of the upper word line group (Zhou, Figure 2, second sub-region 114, and [0051], [0035]) is smaller than a horizontal width of the lower word line group (Zhou, Figure 2, first sub-region 112, and [0051], [0035]).
Zhou fails to disclose the following limitations:
and an etch stopper protection layer between the upper word line group and the lower word line group, wherein the etch stopper protection layer is different from the first word lines and the second word lines;
forming a vertical string, the vertical string extending through the upper word line group, the etch stopper protection layer, and the lower word line group;
which are provided with the etch stopper protection layer therebetween
wherein after forming the stair shape, a maximum width in a horizontal direction of the etch stopper protection layer is the same as a maximum width in the horizontal direction of a lowermost word line of the upper word line group.
Liu discloses the following limitations:
and an etch stopper protection layer (Liu, Figure 9, joint insulating material layer 810, where layer 810 is an etch stopper layer because 810 is on top of the lower stack and would therefore necessarily prevent the lower stack from being etched because it prevents the etchant from contacting the lower stack) between the upper word line group (Liu, Figure 9, second dielectric stack 906, and [0123]) and the lower word line group (Figure 9, first dielectric stack 803, [0123]) wherein the etch stopper protection layer is different from the first word lines and the second word lines (Liu, Figure 9, joint insulating material layer 810 is different from the insulating layer of the stack, insulating material layer 902);
forming a vertical string (Liu, Figure 8 sub-channels 805 and Figure 10, semiconductor channels 1001 containing channel-forming layers 802 [0115], and 1004 [0118]), the vertical string extending through the upper word line group, the etch stopper protection layer, and the lower word line group (Liu, Shown in Figure 10);
which are provided with the etch stopper protection layer therebetween (Liu, Figure 9, 810 is between upper and lower stacks 803 and 906, and Figure 10 and 11 show that the upper and lower stack are joined prior to etching them)
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Liu to the process of Zhou and to therefore have formed vertical string containing a channel layer and a charge storage layer, and an insulating material layer between the upper and lower stacks. Doing so is taught by Liu to provide numerous benefits, including, but not limited to simplifying the fabrication process, reducing the size of the three-dimensional memory device, and improving the space utility of the chip which the three-dimensional memory device is formed on (Liu discloses these advantages in [0004]). Regarding the limitation “wherein after forming the second stair shape, a maximum width in a horizontal direction of the etch stopper protection layer is the same as a maximum width in the horizontal direction of a lowermost word line of the upper word line group” it would have been obvious to one of ordinary skill when combining the stack of the upper and lower word layers as in Figure 2 of Zhou, with the joint insulating material layer of Liu, to have etched the joint insulating material layer to be the width of second sub-region 114. Doing so would expose the top of the first sub-region 112 of Zhou, and would therefore allow the mask of Zhou to be formed as required and allow the upper and lower layers to be etched as taught by Zhou, using similar etch times and conditions for the second sub-region 114 and the first sub-region 112.
Regarding claim 20, the combination of Zhou and Liu further discloses the following limitations:
The method of claim 19, wherein the etch stopper protection layer between the upper word line group and the lower word line group prevents etching of an uppermost word line of the lower word line group when the etching operation is performed on the upper word line group (The insulation layer of Liu, used combination with Zhou, protects the uppermost worldline because it physically blocks the word line from the etchant).
Regarding claim 21, Zhou and Liu disclose the limitations of claim 19, as detailed above. Zhou further discloses the following limitations:
The method of claim 19, wherein the simultaneously performing of the etching operation on each of the upper word line group and the lower word line group is repeatedly performed (Zhou, [0057] discloses that multiple etch-trim processes can be performed repeatedly) based on a number of steps whereby word lines included in the upper word line group are stacked and a number of steps whereby word lines included in the lower word line group are stacked (Zhou, Figure 10, [0062] discloses that each staircase can include a number n of layers, and each step has a width of n×W/T, where W is the width of the stair region and T is the total number of layers in the stack).
Regarding claim 24, Zhou and Liu disclose the limitations of claim 19, as detailed above. Zhou further discloses the following limitations:
The method of claim 19, wherein a width of the etch stopper protection layer before the simultaneously performing the etching operation is the same as a width of the etch stopper protection layer after the simultaneously performing the etching operation (Zhou discloses, Figure 2, and [0051]-[0052]) etching the stack into a staircase with each region having half of the width and then discloses hard mask layer 120 can be formed to cover the top surfaces of the two step-platforms of the alternating layer stack 110 (Figure 3, hard mask layer 120). Therefore in the combination of Zhou and Liu the oxide layer would be removed so that hard mask layer 120 can be formed as required).
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Zhou and Liu as applied to claim 19 above, and further in view of Guo 10566336 B1, hereafter Guo.
Regarding clam 28, Zhou further discloses the following limitations:
The method of claim 19, wherein the forming the upper word line group, the lower word line group, and the etch stopper protection layer comprises forming the stair shape using the upper word line group, the lower word line group, and the etch stopper protection layer (shown Zhou, Figure 10), the stair shape including first portions having an equally spaced width and an equally spaced height
Zhou and Lui fail to disclose the following limitations:
a second portion having a different height from the first portions, and
wherein the second portion having the different height is formed by the etch stopper protection layer.
Gou disclose the following limitations:
a second portion having a different height from the first portions (Figure 4A, discloses a difference in step layer due to joint layer 212),
having the different height is formed by the etch stopper protection layer (Figure 4A, discloses a difference in step layer due to joint layer 212).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Gou to the process of Zhou and Lui because Lui teaches to use an oxide layer between the upper and lower stacks, but fails to show how to form the steps with an oxide layer between the stacks. Gou, who makes a similar device with an oxide layer between the upper and lower stacks, shows how to account for the additional width of the oxide layer when forming a stair shaped memory device. One of ordinary skill the art could have used the teaching of Gou to the device of Zhou and Lui and therefore have formed a larger vertical step where the oxide
Response to Arguments
Applicant's arguments filed 6/16/25 have been fully considered but they are not persuasive.
Applicants argument on page 14 that the joint insulating material layer 180 of Liu is not an “etch stopper protection layer” because in the combination of Zhou and Liu the material would be etched to form the initial stair stack as in Figure 2 of Zhou is not persuasive because the instant claims require an “etch stopper protection layer” for the trim-etch process, not in the process of forming the initial stair structure of Zhou Figure 2. Also, etch stopper protection layer does not imply or require the material to be un-etchable.
Applicants argument on page 15 that the joint insulting layer of Liu is wider than the maximum width of the upper stack is not persuasive because in the combination of Zhou and Liu the joint insulating layer would be etched to the width of the upper layers so that the process of Zhou would not be hindered by additional material on top of the lower stack.
Applicant’s argument on page 15-16 that one of ordinary skill would not have been motivated to modify Zhou with Liu because Liu would add additional fabrication steps is not persuasive because those additional steps, while increasing cost, also would allow more memory cells to be stacked into a given space increasing memory density which reduces overall memory cost.
Applicant’s argument on page 16 that hindsight was used to combine Liu and Zhou is not persuasive because the reasons for combining are a direct quote from [0004] of Liu:
“The disclosed structures and methods provide numerous benefits, including, but not limited to simplifying the fabrication process, reducing the size of the three-dimensional memory device, and improving the space utility of the chip which the three-dimensional memory device is formed on.” (Liu [0004]).
Applicant’s argument on page 17 that the insulating joint material layer 810 is formed on the top of the bottom stack and not on the bottom of the top stack is not persuasive because once the stacks are joined the insulating joint material layer is between the upper and lower stack regardless of where the layer was initially formed. Also, the instant claims are not limited as to if the etch stopping layer is formed on the top of the bottom stack or the bottom of the top stack.
In response to applicant's argument that on pages 17-20 that Zhou and Liu combined do not teach an etch stopping layer that has a maximum width of the lowermost layer of the upper stack because neither reference also shows this is not persuasive, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). When combining Liu with Zhou the etch stopping layer can with be left complete and cover the entire surface of the bottom stack or etched with the upper stack to the length of the lowermost layer of the upper stack. If the layer is etched with the upper stack the trim-etch process of Zhou is unchanged, if it is not etched with the upper stack then every time a trim-etch step is performed the etch stopping layer would need to be etched. For this reason one of ordinary skill in the art would etch the etch stopper layer with the upper stack.
For the above reasons the rejection, as amended, have been maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen US 9070447 B2, discloses a simultaneous trim and etch process for memory, See Figures 26-36. This process includes sub stack insulating layers.
Song et al., US 20220319600 A1, discloses a non-simultaneous trim-etch process with an intermediate layer between the upper and lower stacks.
Cheng et al., US 20210351196 A1, discloses a trim-etch method where the intermediate layer only covers half of the lower stack. See Figure 9-10.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/LINDA J. FLECK/ Examiner, Art Unit 2812
/William B Partridge/ Supervisory Patent Examiner, Art Unit 2812