DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to RCE filed on January 29, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over by Machida et al. (US 2007/0228401, hereinafter “Machida”) in view of Miyamoto et al. (US 2018/0026099, hereinafter “Miyamoto”).
Regarding claim 1, Machida discloses for a nitride-based semiconductor circuit comprising that
a nitride-based semiconductor carrier (substrate 2/buffer layer 3, Fig. 11), because “the buffer layer 3 comprises a nitride-based compound semiconductor” ([0042]);
a first nitride-based semiconductor layer (electron transit layer 4, Fig. 11) disposed over the semiconductor carrier (2/3, Fig. 11);
a second nitride-based semiconductor layer (electron supply layer 5, Fig. 11) disposed on the first nitride-based semiconductor layer (4, Fig. 11);
a source connector (source electrode 22, Fig. 11) disposed on the second nitride-based semiconductor layer (5, Fig. 11);
a gate connector (gate electrode 24, Fig. 11) disposed on the second nitride-based semiconductor layer (5, Fig. 11);
a drain connector (drain electrode 23, Fig. 11) disposed on the second nitride-based semiconductor layer (5, Fig. 11);
a connection line (connection conductor 8 between source electrode 22 and the battery 18, Fig. 11) electrically connected to the source connector (22, Fig. 11); and
a power supply line (connection conductor 8 between the battery 18 and the substrate 2, Fig. 11) electrically connected to the nitride-based semiconductor carrier (2/3, Fig. 11),
wherein a heterojunction is formed between the first and the second nitride-based semiconductor layers (4 and 5, Fig. 11), and the gate connector (24, Fig. 11) is located between the source connector (22, Fig. 11) and the drain connector (23, Fig. 11), and a potential difference is applied between the power supply line (connection conductor 8 between the battery 18 and the substrate 2, Fig. 11) and the connection line (connection conductor 8 between source electrode 22 and the battery 18, Fig. 11), such that the potential difference is applied between the source connector (22, Fig. 11) and the nitride-based semiconductor carrier (2/3, Fig. 11), because Machida further discloses “a voltage supply unit capable of applying electrical potential such that the electrical potential applied to the substrate or the nitride-based compound semiconductor layer is higher than the electrical potential applied to the gate electrode, the source electrode, and the drain electrode” (emphasis added, [0015]) and “when the state of applying high voltage reverse bias is changed to forward bias, an electrical field is generated in the semiconductor substrate 13 because the electrical potential (voltage supply unit) which higher than that of the source electrode 22, drain electrode 23, and the gate electrode 24 in the substrate 2 is generated” (emphasis added, [0068], Fig. 11).
Machida differs from the claimed invention by not showing that one or more interconnections, wherein the interconnections go through the first nitride-based semiconductor layer, and the second nitride-based semiconductor layer, and electrically connect the nitride-based semiconductor carrier, the power supply line is electrically connected to the interconnections, and orthographic projections of the interconnections onto the nitride-based semiconductor carrier do not overlap with orthographic projections of the source connector, the gate connector, and the drain connector onto the nitride-based semiconductor carrier.
However, Miyamoto discloses for a power transistor of a high electron mobility transistor (HEMT) that the device (Fig. 26) includes that the source electrode SE, drain electrode DE and gate electrode GE are disposed on the fifth (5S) and fourth (4S) nitride semiconductor layers, which corresponds to the second and first nitride-based semiconductor layers in the claimed invention, respectively, and the gate electrode GE is positioned between the source electrode SE and the drain electrode DE (Fig. 26); Miyamoto also discloses that the fourth electrode 4E including coupling electrode and coupling part is formed within the via hole VIA extending through the fifth and fourth nitride semiconductor layers and electrically connected to the external power supply 2P as the voltage application unit 2P (Fig. 26, [0084]), therefore, the fourth electrode 4E by Miyamoto corresponds to the interconnections in the claimed invention; and as shown in Fig. 43 of Miyamoto (plan view or orthographic projection), the fourth electrode 4E and via hole VIA are positioned such that they do not overlap with the source electrode SL, the gate electrode GE, and the drain electrode DL (Fig. 43), as claimed. Therefore, one of ordinary skill in the art would have recognized that the HEMT device of Machida can be modified to include the interconnections formed in via hole through the nitride semiconductor layers and it can be located outside of source/drain/gate electrodes in a plan view.
Since both Machia and Miyamoto teach the HEMT device, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the HEMT device of Machida to include interconnections formed within via holes through the nitride semiconductor layers and positioned outside of source/drain/gate electrodes in a plan view for routing electrical connections to an external power supply while avoiding overlap with source/drain/gate electrodes, as disclosed by Miyamoto, in order to reduce electrical interference and improve overall device performance.
Regarding claim 2, Miyamoto further discloses that the nitride-based semiconductor carrier (substrate SUB/buffer layer BUF/first and second nitride semiconductor layers 1S/2S, Fig. 26) comprises: a substrate (substrate SUB, Fig. 26); a buffer layer (buffer layer BUF or first nitride semiconductor layer 1S (buffer layer), Fig. 26); and a third nitride-based semiconductor layer (second nitride semiconductor layer 2S, Fig. 26) disposed on the buffer layer (BUF or 1S, Fig. 26), and the third nitride-based semiconductor layer (2S, Fig. 26) is doped with p-type dopant, because “an AlGaN layer (p-AlGaN layer) containing a p-type impurity is epitaxially grown as the second nitride semiconductor layer (voltage clamp layer) 2S on the first nitride semiconductor layer (buffer layer) 1S by a metal organic chemical vapor deposition process or the like” (emphasis added, [0092]).
Regarding claim 4, Machida further discloses that the power supply line (connection conductor 8 between the battery 18 and the substrate 2, Fig. 11) is electrically connected to the substrate (2, Fig. 11).
Regarding claim 6, Miyamoto further discloses that the third nitride-based semiconductor layer (2S, Fig. 26) and the first nitride-based semiconductor layer (fourth nitride semiconductor layer 4S, Fig. 26) form one or more parasitic diodes, and the potential difference biases the parasitic diodes, because it is obvious to one of ordinary skill in the art that heterojunctions formed between wide band gap nitride semiconductor layers can unintentionally behave like diode or parasitic diode, due to band discontinuities at the interface and/or differences in doping; the limitation “the potential difference biases the parasitic diodes” is directed to an intended use or field of use of a heterojunction structure and power supplied connected to HEMT device.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over by Machida et al. (US 2007/0228401, hereinafter “Machida”) in view of Miyamoto et al. (US 2018/0026099, hereinafter “Miyamoto”) as applied to claim 2 above, and further in view of Kohda et al. (US 2013/0240901; hereinafter “Kohda”).
Regarding claim 3, Machida in view of Miyamoto does not explicitly disclose that the p-type dopant is carbon.
However, Kohda discloses for a nitride-based semiconductor device that the second nitride semiconductor layer 4 is disposed on the first nitride semiconductor layer 3, buffer layer 2 and the substrate 1 (Fig. 1), and a composite layer of 1/2/3/4 by Kohda corresponds to the nitride-based semiconductor carrier in the claimed invention, and therefore, the second nitride semiconductor layer 4 can correspond to the third nitride-based semiconductor layer in the claimed invention; and Kohda further discloses “the second nitride semiconductor layer 4 is made of a compound of InxAlyGa1-x-yN…” ([0045]) and “the second nitride semiconductor layer 4 is lightly doped with carbon” (emphasis added, [0044]), and carbon is well-known p-type dopant for the nitride-based semiconductor layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the nitride-based semiconductor layer can be doped with carbon to form p-type semiconductor layer, as disclosed by Kohda, and carbon is well known in the semiconductor art as a p-type dopant for the nitride-based semiconductor layers.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over by Machida et al. (US 2007/0228401, hereinafter “Machida”) in view of Miyamoto et al. (US 2018/0026099, hereinafter “Miyamoto”) as applied to claim 1 above, and further in view of Oraw (US 2013/0221368).
Regarding claim 14, Machida in view of Miyamoto does not explicitly disclose that the power supply line is electrically connected to a negative voltage of a power supply, and the connection line is electrically connected to a positive voltage of the power supply.
However, Oraw discloses for GaN-based transistor such as HEMT, MOSFET or MESFET ([0072]) that the device includes the source terminal T3 and the cathode terminal T1 on the backside of the substrate (Fig. 3), and the device can be controlled by varying voltages of power supply connected to the device, as shown in Fig. 4 (see attached Fig. 4 of Oraw below); and one of the voltage configurations includes that a positive voltage is applied to the source terminal T3, a negative voltage is applied to the cathode terminal T1 ([0070]), which can be the same configuration of the claimed invention, therefore, it is obvious to one of ordinary skill in the art that the voltage of power supply connected to the source and the substrate can be varied to optimize the device performance.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the voltage of a power supply connected to a source and substrate (or cathode) electrode can be controlled, as disclosed by Oraw, in order to optimize the performance of GaN-based HEMT device.
Allowable Subject Matter
Claims 8 and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because the prior arts cited in this Office Action do not teach the claimed limitation, “the interconnection is electrically connected to the substrate” of claim 8 and “the orthographic projections of the interconnections onto the nitride-based semiconductor carrier extend along the first direction, and have a third edge and a fourth edge that are aligned with the first edge and the second edge along a second direction, respectively” of claim 26.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/WOO K LEE/Examiner, Art Unit 2815