Prosecution Insights
Last updated: July 17, 2026
Application No. 17/440,205

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Non-Final OA §103§112
Filed
Jan 19, 2023
Priority
Jul 16, 2021 — nonprovisional of PCTCN2021106915
Examiner
BELL, LAUREN R
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Innoscience (Suzhou) Technology Co. Ltd.
OA Round
2 (Non-Final)
40%
Grant Probability
Moderate
2-3
OA Rounds
0m
Est. Remaining
72%
With Interview

Examiner Intelligence

Grants 40% of resolved cases
40%
Career Allowance Rate
153 granted / 382 resolved
-27.9% vs TC avg
Strong +32% interview lift
Without
With
+31.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
48 currently pending
Career history
449
Total Applications
across all art units

Statute-Specific Performance

§103
79.0%
+39.0% vs TC avg
§102
6.5%
-33.5% vs TC avg
§112
5.6%
-34.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 382 resolved cases

Office Action

§103 §112
DETAILED ACTION Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-3 and 5-15 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claim 1, the limitation “wherein the passivation laver has an inner sidewall to define the air gap, and a minimum horizontal distance from the inner sidewall to the drain electrode is less than a minimum horizontal distance from the field plate to the drain electrode,” does not appear to have adequate support in the originally filed disclosure. Specifically, there is no disclosure of any “minimum horizontal distance.” It is noted that drawings are not to scale. Further, it is noted that one cannot ascertain any potential distances in any cross section other than the cross section of Fig. 4, and therefore even if a distance could be gleaned in the cross section of Fig. 4, it would not be known if said distance was a “minimum” distance. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim(s) 1-3 and 5-15 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1, the limitation “wherein the passivation laver has an inner sidewall to define the air gap, and a minimum horizontal distance from the inner sidewall to the drain electrode is less than a minimum horizontal distance from the field plate to the drain electrode,” is unclear as to what is required by the limitation. Specifically, it is noted that there is no disclosure of any “minimum horizontal distance.” Further, it is unclear what between which portions of the elements the distance is defined. For example, it is unclear as to if the “minimum horizontal distance” between the air gap and the drain electrode 128 meant to be taken at lower portion of 128 as shown in Fig. 4, which would be understood to represent a strictly “horizontal” distance, or if it is it meant to be taken at the upper portion of 128 which would be understood to be “minimum” in that cross section. Accordingly the proper interpretation of the claim, in light of the disclosure, is unclear. Regarding claims 2, 3 and 15, the limitation “the dielectric of the passivation layer,” is unclear as to how “the dielectric layer” is related to the previously recited “at last one dielectric of the passivation layer.” Regarding claims 5 and 12, the limitation “wherein the passivation layer has an inner sidewall to define a tunnel in which the air gap is located,” is unclear as to how it is related to the previously recited inner sidewall. Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-3, 5, 7, 9-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nogami at al. (US 20090014758; herein “Nogami”) in view of Ikeda et al. (US 20100117146; herein “Ikeda”). Regarding claim 1, Nogami discloses in Fig. 44 or 48 (including features disclosed in accordance with Fig. 1) and related text nitride-based semiconductor device, comprising: a first nitride-based semiconductor layer (e.g. 14, see [0039]); a second nitride-based semiconductor layer (e.g. 15, see [0039]) disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer (AlGaN has higher bandgap than GaN); a source electrode and a drain electrode (27 and 28, see [0043]) disposed above the second nitride-based semiconductor layer; a gate structure (e.g. 25, see [0022]) disposed above the second nitride-based semiconductor layer and between the source and drain electrodes; a passivation layer (e.g. 18/29/33, see [0022]-[0023]) disposed above the second nitride-based semiconductor layer and covering the gate structure and having an enclosed air gap (32, see [0024]) between the gate structure and the drain electrode, wherein the passivation layer comprises at least one dielectric; wherein the passivation laver has an inner sidewall to define the air gap (e.g. inner sidewall of 29 closest to 28), and a minimum horizontal distance from the inner sidewall to the drain electrode (e.g. distance between inner sidewall closest to 28 and left sidewall of 28). Nogami does not disclose a field plate disposed above the passivation layer and having a first portion directly over the gate structure and a second portion directly over the air gap, wherein the second portion is separated from the air gap by at least one dielectric of the passivation layer; a minimum horizontal distance from the inner sidewall to the drain electrode is less than a minimum horizontal distance from the field plate to the drain electrode. In the same field of endeavor, Ikeda teaches in Fig. 1 and related text a semiconductor device comprising a field plate (23a, see [0068]) disposed above the passivation layer (16, see [0083]) and having a first portion directly over the gate structure (21, see [0082]) and a second portion directly over a region between the gate structure and the source electrode, wherein the second portion is over at least one dielectric of the passivation layer, a minimum horizontal distance from the field plate to the drain electrode (e.g. distance from the right sidewall of the field plate to the left sidewall of drain 22d). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Nogami by having a field plate disposed above the passivation layer, having a first portion directly over the gate structure and a second portion directly over a region between the gate structure and the drain electrode, and the second portion is over at least one dielectric of the passivation layer, as taught by Ikeda, in order to enhance the performance of the semiconductor device, e.g. enhance withstanding characteristics (see [0068]). The limitation “a second portion directly over the air gap, wherein the second portion is separated from the air gap by at least one dielectric of the passivation layer,” is taught by the combination of a second portion directly over a region between the gate structure and the source electrode and the second portion is over at least one dielectric of the passivation layer, as shown by Ikeda, in combination with the air gap being at least partially in the region between the gate structure and the source electrode and the air gap being below the at least on dielectric of the passivation layer, as shown by Nogami. The limitation “a minimum horizontal distance from the inner sidewall to the drain electrode is less than a minimum horizontal distance from the field plate to the drain electrode” is taught by the combination of the air gap being between the gate structure and the drain electrode, as shown by Nogami, and the field plate only extending over the source side of the gate structure, as shown by Ikeda. Regarding claim 2, Nogami further discloses wherein the air gap (32) is separated from the second nitride-based semiconductor layer (15) by the dielectric of the passivation layer (18). Regarding claim 3, Nogami further discloses wherein the gate structure (25) and the air gap (32) are separated from the each other by the dielectric of the passivation layer (in the embodiment of Fig. 44, separated 18). Regarding claim 5, Nogami further discloses wherein the passivation layer has an inner sidewall (e.g. sidewall of 29 in embodiment of Fig. 48) to define a tunnel in which the air gap (32) is located. Regarding claim 7, the combined device shows the tunnel and the second portion of the field plate extend laterally along the same direction such that the tunnel and the second portion of the field plate have an overlapping area. Note that the limitation is taught by the combination of the tunnel/air gap extending horizontally in the region between the gate structure and the drain as shown in Fig. 48 of Nogami and the field plate extending horizontally over a region between the gate structure and the drain electrode as shown in Ikeda, therefore they overlap in the area between the gate structure and the drain electrode in the combined device. Regarding claim 9 and 10, the combined device shows wherein the passivation layer has a first protruding portion (Nogami: e.g. portion of 33 on the left corner of the gate) located between the gate structure and the first portion of the field plate; wherein the passivation layer has a second protruding portion (Nogami: e.g. portion of 29 above the right corner of the gate) located between the air gap and the second portion of the field plate and in a position lower than the first protruding portion. Regarding claim 11, the combined device shows wherein the field plate (Ikeda: 23a) has a third portion between the first and second portions thereof and extending laterally between the first and second protruding portions (note that one can choose “portions” such that the claimed limitation is met). Regarding claim 12, the combined device shows wherein the passivation layer has an inner sidewall to define a tunnel in which the air gap is located, and the tunnel has a width less than a width of the second protruding portion (Nogami: e.g. the region between 29 and upper portion of gate 25 is interpreted as a “tunnel” in which the air gap is at least partially located). Regarding claim 13, the combined device shows wherein the first portion of the field plate is in a position higher than the second portion of the field plate (Ikeda: note that one can choose “portions” such that the claimed limitation is met). Regarding claim 14, the combined device shows wherein the field plate has a third portion between the first and second portions thereof and in a position lower than the first and second portions thereof. Note that the limitation is taught by the combination of the field plate being conformal to the passivation layer, as shown by Ikeda, wherein the first portion of the field plate is above the portion of 33 on the left corner of the gate shown by Nogami, the second portion of the field plate is above the portion of 33 shown by Nogami, and the third portion of the field plate is above the recess in 33 over the middle of the gate shown by Nogami. Regarding claim 15, Nogami further discloses wherein the dielectric of the passivation layer comprises silicon nitride (see [0022]-[0023]). Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nogami in view of Ikeda, as applied to claim 1 above, and further in view of Lin et al. (US 10930745; herein “Lin”). Regarding claim 6, Nogami further discloses wherein the gate structure comprises a gate electrode (25) disposed on the second nitride-based semiconductor layer (15), and the gate electrode is formed as strips parallel with the tunnel (see Fig. 20 at least), but does not explicitly disclose the gate electrode comprises a doped III-V semiconductor layer disposed between the second nitride-based semiconductor layer and the gate electrode, and the doped III-V semiconductor layer is formed as a strip parallel with the tunnel. In the same field of endeavor, Lin teaches in Fig. 2 and related text a semiconductor device wherein the gate electrode comprises a doped III-V semiconductor layer (114, see col. 5 para. 4) disposed between the second nitride-based semiconductor layer (112) and the gate electrode (121), and the doped III-V semiconductor layer is formed as a strip. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Nogami by having the gate electrode comprise a doped III-V semiconductor layer disposed between the second nitride-based semiconductor layer and the gate electrode, and the doped III-V semiconductor layer is formed as a strip, as taught by Lin, in order to obtain a normally off device (Lin, see col. 5, para. 4). The limitation “the doped III-V semiconductor layer are formed as strips parallel with the tunnel,” is therefore taught by the combination of the doped III-V semiconductor layer formed under the entire gate electrode, as shown by Lin, and the gate electrode being formed in a strip parallel with the tunnel, as shown by Nogami. Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nogami in view of Ikeda, as applied to claim 1 above, and further in view of Park et al. (US 20040099951; herein “Park”). Regarding claim 8, Nogami does not explicitly disclose the tunnel comprises at least one oxide accommodated therein, and the at least one oxide is adhered to the inner sidewall. In the same field of endeavor, Park teaches in Fig. 1I and related text a semiconductor device comprising an air gap 144 in a tunnel, wherein at least one oxide (142, see [0020]) accommodated therein is adhered to the inner sidewall. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Nogami by having at least one oxide accommodated in the tunnel and adhered to the inner sidewall, as taught by Park, in order to provide support of the associated structures (see Park [0020]). Further, it is well known that residual material often remains after etching, and therefore it would be obvious to have at least one oxide accommodated in the tunnel and adhered to the inner sidewall in order to avoid excessive processing and cleaning steps and potential damage of the device associated therewith in order to completely remove the sacrificial material of Nogami. Response to Arguments Applicant's arguments filed 4/1/2026 have been fully considered but are moot in view of the new grounds of rejection presented above. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAUREN R BELL/Primary Examiner, Art Unit 2896
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Prosecution Timeline

Show 2 earlier events
May 13, 2025
Examiner Interview (Telephonic)
May 22, 2025
Applicant Interview (Telephonic)
May 22, 2025
Examiner Interview Summary
Dec 02, 2025
Non-Final Rejection (signed) — §103, §112
Jan 08, 2026
Non-Final Rejection mailed — §103, §112
Apr 01, 2026
Response Filed
May 18, 2026
Final Rejection mailed — §103, §112
Jun 22, 2026
Response after Non-Final Action

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Prosecution Projections

2-3
Expected OA Rounds
40%
Grant Probability
72%
With Interview (+31.5%)
3y 5m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 382 resolved cases by this examiner. Grant probability derived from career allowance rate.

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