DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Device Embodiment II and Modification A1 in the reply filed on 27 November 2025 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 1 April 2022 and 27 February 2024 have been considered by the examiner and made of record in the application file.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE COMPRISING A CHLORINE DOPED DIELECTRIC LAYER AND METHOD FOR MANUFACTURING THE SAME.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 10-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hang Liao (CN 111509041 A; using US 2021/0328029 A1 for English translation; hereinafter “Liao”).
Regarding Claim 1, Liao teaches a semiconductor device comprising:
a substrate (19, Fig. 1, para [0024] describes a substrate 19);
a first nitride-based semiconductor layer disposed above the substrate (181, Fig. 1, para [0027] describes a group III-V semiconductor layer 181 disposed on the substrate 19 that may comprise nitrogen);
a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer (182, Fig. 1, para [0028] describes a group III-V layer 182 disposed on the first nitride semiconductor layer 181 that may comprise nitrogen wherein second nitride semiconductor layer 182 is describes as having a larger bandgap than first nitride semiconductor layer 181);
a doped nitride-based semiconductor layer disposed over the second nitride-based semiconductor layer (16, Fig. 1, para [0030] describes a doped group III-V semiconductor layer 16 disposed over second semiconductor layer 182 wherein doped semiconductor layer 16 may comprise a nitride);
a gate electrode disposed on the doped nitride-based semiconductor layer (13, Fig. 1, para [0031] describes a gate conductor 13 disposed on the doped nitride semiconductor layer 16);
a first dielectric protection layer including oxygen and disposed on the gate electrode and the second nitride-based semiconductor layer (141, Fig. 1, para [0033] describes a passivation film 141 which may include oxygen being disposed on gate electrode 13 and second nitride semiconductor layer 182), wherein the first dielectric protection layer is conformal with a profile collectively constructed by the gate electrode, the doped nitride-based semiconductor layer, and the second nitride-based semiconductor layer (141, Fig. 1 depicts wherein first dielectric protection layer 141 is conformal with gate electrode 13, doped nitride semiconductor layer 16 and second nitride semiconductor layer 141)); and
a second dielectric protection layer including oxygen and disposed on and in contact with the first dielectric protection layer (142, Fig. 1, para [0034] describes a passivation layer 142 which may include oxygen disposed on and in contact with first dielectric protection layer 141), wherein the first dielectric protection layer has an oxygen concentration less than that of the second dielectric protection layer (141 and 142, Fig. 1, para [0033] and para [0034] describe wherein the first dielectric protection layer 141 may comprise a combination of an oxide and nitride such as Al2O3/Si3N4 and the second dielectric protection layer 142 may comprise just an oxide such as SiO2 or an oxynitride with a higher concentration of oxygen than the first dielectric protection layer wherein a resulting oxygen concentration of second dielectric protection layer 142 is higher than that of first dielectric protection layer 141).
Regarding Claim 2, Liao teaches the semiconductor device of claim 1, wherein the second dielectric protection layer is conformal with the first dielectric protection layer and is thicker than the first dielectric protection layer (142, Fig. 1, para [0032] describes wherein second dielectric protection layer 142 is disposed on first dielectric protection layer 141 and can be seen in Fig. 1 as conformal to layer 141 and having a greater thickness than layer 141).
Regarding Claim 3, Liao teaches the semiconductor device of claim 2, wherein the sum of thickness of the doped nitride-based semiconductor layer and the gate electrode is greater than the sum of thickness of the first and second dielectric protection layers (Fig. 1 depicts doped nitride semiconductor layer 16 and gate electrode 13 having a greater thickness in combination than first dielectric protection layer 141 and second dielectric protection layer 142 in combination).
Regarding Claim 10, Liao teaches the semiconductor device of claim 1, wherein the first dielectric protection layer extends from the second nitride-based semiconductor layer to the doped nitride-based semiconductor layer (141, Fig. 1 depicts wherein first dielectric protection layer 141 extends from the second nitride semiconductor layer 142 to the doped nitride semiconductor layer 16).
Regarding Claim 11, Liao teaches the semiconductor device of claim 10, wherein the first dielectric protection layer extends from the doped nitride-based semiconductor layer to the gate electrode (141, Fig. 1 depicts wherein first dielectric protection layer 141 extends from the doped nitride semiconductor layer 16 to the gate electrode 13).
Regarding Claim 12, Liao teaches the semiconductor device of claim 11, wherein the first dielectric protection layer extends laterally on a top surface of the gate electrode (141, Fig. 1 depicts wherein first nitride semiconductor layer 141 extends laterally from a top surface of gate electrode 13).
Regarding Claim 13, Liao teaches the semiconductor device of claim 1, further comprising a source/drain (S/D) electrode penetrating the first and second dielectric protection layers to make contact with the second nitride-based semiconductor layer (11 and 15, Fig. 1, para [0037] - para [0039] describes a source conductor 15 and a drain conductor 11 which may penetrate the first dielectric protection layer 141 and second dielectric protection layer 143 and be disposed on second nitride-based semiconductor layer 182).
Regarding Claim 14, Liao teaches the semiconductor device of claim 1, wherein both of the first and second dielectric protection layers comprises silicon nitride (Si3N4) (141 and 142, Fig. 1, para [0033] describes wherein first dielectric protection layer may including silicon nitride and para [0034] describes wherein second dielectric protection layer may include silicon nitride).
Regarding Claim 15, Liao teaches the semiconductor device of claim 1, wherein the second nitride-based semiconductor layer is separated from the second dielectric protection layer by the first dielectric protection layer (Fig. 1 depicts wherein second nitride-based semiconductor layer 16 is separated from second dielectric protection layer 142 by the first dielectric protection layer 141).
Regarding Claim 16, Liao teaches a manufacturing method of a semiconductor device, comprising:
forming a first nitride-based semiconductor layer (181, Fig. 5a, para [0097] describes forming a group III-V layer 181 wherein said group III-V layer may include a nitride as described in para [0027]);
forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer (182, Fig. 5a, para [0097] describes forming a group III-V layer 182 on the first nitride-based semiconductor layer 181 wherein said group III-V layer may include a nitride as described in para [0028]);
forming a doped nitride-based semiconductor layer over the second nitride-based semiconductor layer (16, Fig. 5a, para [0099] describes forming a doped group III-V layer 16 on the second nitride-based semiconductor layer 182 wherein said doped group III-V layer may include a nitride as described in para [0030]);
forming a gate electrode on the doped nitride-based semiconductor layer (13, Fig. 5a, para [0100] describes forming a gate conductor 13 on the doped nitride-based semiconductor layer 16);
forming a first dielectric protection layer including oxygen and on the gate electrode and the second nitride-based semiconductor layer (141, Fig. 5b, para [0104] describes forming a passivation layer 141 on the gate electrode 16 and second nitride-based semiconductor layer 182 wherein said passivation layer may include oxygen as described in para [0033]); and
forming a second dielectric protection layer including oxygen and on and in contact with the first dielectric protection layer (142, Fig. 5c, para [0104] describes forming a passivation layer 142 on the first dielectric protection layer 141 wherein said passivation layer 142 may include oxygen as described in para [0034]), wherein the first dielectric protection layer has an oxygen concentration less than that of the second dielectric protection layer and is thinner than the second dielectric protection layer (141 and 142, Fig. 1, para [0033] and para [0034] describe wherein the first dielectric protection layer 141 may comprise a combination of an oxide and nitride such as Al2O3/Si3N4 and the second dielectric protection layer 142 may comprise just an oxide such as SiO2 or an oxynitride with a higher concentration of oxygen than the first dielectric protection layer wherein a resulting oxygen concentration of second dielectric protection layer 142 is higher than that of first dielectric protection layer 141 and further wherein Fig. 5c depicts that the first dielectric protection layer is thinner than the second dielectric protection layer).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Hang Liao (CN 111509041 A; using US 2021/0328029 A1 for English translation; hereinafter “Liao”) in further view of Takuji Yamamura et al. (US 2021/0104395 A1; hereinafter “Yamamura”).
Regarding Claim 4, Liao discloses all the limitations of claim 1.
Liao fails to explicitly disclose the semiconductor device of claim 1, wherein a ratio of a thickness of the first dielectric protection layer to a thickness of the second dielectric protection layer is in a range from 0.01 to 0.5.
However, Yamamura discloses a similar semiconductor device, wherein a ratio of a thickness of the first dielectric protection layer to a thickness of the second dielectric protection layer is in a range from 0.01 to 0.5 (11 and 12, Fig. 1, para [0038] and para [0039] describes a thickness of a first dielectric protection layer 11 may be in a range from 10 nm to 100 nm and a thickness of a second dielectric layer 12 may be in a range from 10 nm to 100 nm wherein upon selecting a thickness of 10 nm for a first protective dielectric layer and a thickness of 100 nm for a second protective dielectric layer a resulting ratio of thickness of the first dielectric layer to a thickness of the second dielectric protection layer is 0.1 failing within a range of 0.01 to 0.5).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Liao with Yamamura to further disclose a semiconductor device wherein a ratio of a thickness of a first dielectric protective layer to a thickness of a second dielectric protective layer is 0.01 to 0.5 in order to provide the advantage of shortening the distance between an interface oxide layer and a semiconductor multilayer stack and a surface of a protection film is moved away from said semiconductor multilayer stack so that the effect of a fixed positive charge can be obtained more stably (Yamamura, para [0075]).
Regarding Claim 5, Liao discloses all the limitations of claim 1.
Liao fails to explicitly disclose the semiconductor device of claim 1, wherein the first and second dielectric protection layers forms an interface therebetween at which oxygen is distributed.
However, Yamamura discloses a similar semiconductor device, wherein the first and second dielectric protection layers forms an interface therebetween at which oxygen is distributed (13, Fig. 1, para [0038] describes an interface oxide layer 13 is formed between a first surface protection film 11 and a second surface protection film 12).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Liao with Yamamura to further disclose a semiconductor device wherein an interface oxide layer is formed between dielectric protection layers in order to provide the advantage of reducing current collapse by suppressing semiconductor surface potential (Yamamura, para [0057]).
Regarding Claim 6, the combination of Liao and Yamamura discloses the semiconductor device of claim 5, wherein an oxygen concentration at the interface is greater than the oxygen concentration of the second dielectric protection layer (Yamamura, 13, para [0040] describes wherein the interface oxide layer 13 contains oxygen atoms in excess of 5x10---21 atoms/cm3 and Fig. 5, para [0061] describes wherein a peak concentration of oxygen occurs at the interface oxide layer 13 between SiN protective films 11 and 12).
Regarding Claim 17, Liao discloses all the limitations of claim 16.
Liao fails to explicitly disclose the manufacturing method of claim 16, further comprising: breaking vacuum after forming the first dielectric protection layer and prior to forming the second dielectric protection layer.
However, Yamamura discloses a similar method of manufacturing a semiconductor device, further comprising:
breaking vacuum after forming the first dielectric protection layer and prior to forming the second dielectric protection layer (para [0040] describes a vacuum evacuation process between formation of a first protective film 11 and second protective film 12).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Liao with Yamamura to further disclose a method of manufacturing a semiconductor device wherein a vacuum is broken after forming a first dielectric protection layer in order to form an interface oxide layer between dielectric protection layers to provide the advantage of reducing current collapse by suppressing semiconductor surface potential (Yamamura, para [0057]).
Regarding Claim 18, the combination of Liao and Yamamura discloses the manufacturing method of claim 17, wherein an interface formed between the first and second dielectric protection layers contains oxygen due to breaking vacuum (13, Fig. 1, para [0040] describes wherein an interface oxide layer 13 is formed through a vacuum evacuation process between formation of a first protective film 11and second protective film 12).
Claims 7-9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hang Liao (CN 111509041 A; using US 2021/0328029 A1 for English translation; hereinafter “Liao”) in further view of Takahide Hirasaki (US 2021/0217853 A1; hereinafter “Hirasaki”).
Regarding Claim 7, Liao discloses all the limitations of claim 1.
Liao fails to explicitly disclose the semiconductor device of claim 1, wherein the second dielectric protection layer has a chlorine concentration greater than that of the first dielectric protection layer.
However, Hirasaki teaches a similar semiconductor device, wherein the second dielectric protection layer has a chlorine concentration greater than that of the first dielectric protection layer (25 and 22, Fig. 1, para [0056] describes wherein a first dielectric protection layer 22 may have a chlorine concentration of 1x1019 atoms/cm3 or less wherein said layer may be formed with a raw material gas containing no chlorine wherein a resulting first dielectric protection layer 22 may have no chlorine and para [0046] describes wherein a second dielectric protection layer 25 may be formed using dichlorosilane resulting in an insulating layer which may comprise chlorine wherein a resulting second dielectric protection layer 25 would have a greater chlorine concentration than a first dielectric protection layer 22).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Liao with Hirasaki to further disclose a semiconductor device wherein a second dielectric protection layer has a higher concentration of chlorine than a first dielectric protection layer to provide the advantage of being able to control a refractive index of dielectric protection layers so as to be able to refract wavelengths of a desired length (Hirasaki, para [0057]).
Regarding Claim 8, Liao discloses all the limitations of claim 1.
Liao fails to explicitly disclose the semiconductor device of claim 1, wherein the second dielectric protection layer is doped with chlorine.
However, Hirasaki teaches a similar semiconductor device, wherein the second dielectric protection layer is doped with chlorine (25, Fig. 1, para [0046] describes wherein a second dielectric protection layer 25 may be formed using dichlorosilane resulting in an insulating layer which may be doped with chlorine).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Liao with Hirasaki to further disclose a semiconductor device wherein a second dielectric protection layer is doped with chlorine in order to provide the advantage of suppressing a decrease in the insulating property of the insulating layers and to suppress an increase in the leakage current through the insulating layers (Hirasaki, para [0075] – para [0078]).
Regarding Claim 9, the combination of Liao and Hirasaki discloses the semiconductor device of claim 8, wherein the first dielectric protection layer is devoid of chlorine (22, Fig. 1, para [0056] describes wherein a first dielectric protection layer 22 may have a chlorine concentration of 1x1019 atoms/cm3 wherein said layer may be formed with a raw material gas containing no chlorine wherein a resulting first dielectric protection layer 22 may have no chlorine).
Regarding Claim 19, Liao discloses all the limitations of claim 16.
Liao fails to explicitly disclose the manufacturing method of claim 16, wherein forming the second dielectric protection layer is performed with introducing SiH2CL2 gas.
However, Hirasaki teaches a similar manufacturing method of a semiconductor device, wherein forming the second dielectric protection layer is performed with introducing SiH2CL2 gas (25, Fig. 1, para [0046] describes forming a second dielectric protection layer 25 on a first dielectric protection layer 22 wherein said second dielectric protection layer is formed through a process which introduces dichlorosilane (SiH2CL2) gas).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Liao with Hirasaki to further disclose a manufacturing method of a semiconductor device wherein a second dielectric protection layer is formed through a process introducing SiH2CL2 gas in order to provide the advantage of providing chlorine into a second dielectric protection layer further suppressing a decrease in the insulating property of the insulating layers and to suppress an increase in the leakage current through the insulating layers (Hirasaki, para [0075] – para [0078]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Hang Liao (CN 111509041 A; using US 2021/0328029 A1 for English translation; hereinafter “Liao”) in view of Takuji Yamamura et al. (US 2021/0104395 A1; hereinafter “Yamamura”) and in further view of Takahide Hirasaki (US 2021/0217853 A1; hereinafter “Hirasaki”).
Regarding Claim 20, the combination of Liao and Yamamura disclose all the limitations of claim 18.
The combination of Liao and Yamamura fails to explicitly disclose the manufacturing method of claim 18, wherein forming the first dielectric protection layer is performed without introducing SiH2CL2 gas.
However, Hirasaki teaches a similar manufacturing method of a semiconductor device, wherein forming the first dielectric protection layer is performed without introducing SiH2CL2 gas (22, Fig. 1, para [0056] describes wherein a first dielectric protection layer 22 may have a chlorine concentration of 1x1019 atoms/cm3 wherein said layer may be formed with a raw material gas containing no chlorine wherein a resulting first dielectric protection layer 22 may have no chlorine).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Liao and Yamamura with Hirasaki to further disclose a manufacturing method of a semiconductor device wherein a first dielectric protection layer is formed through a process without introducing SiH2CL2 gas in order to provide the advantage of providing a second dielectric protection layer devoid of chlorine further suppressing a decrease in the insulating property of the insulating layers and to suppress an increase in the leakage current through the insulating layers (Hirasaki, para [0075] – para [0078]).
Conclusion
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898