DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-9, 12-16, and 19-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakai (US 5563708 A) and Ghinovker (US 20130163852 A1).
Regarding Claim 1, Nakai discloses a method of generating an angular calibration factor (ACF)[Column 4 lines 45-59 – “The position with respect to the .theta. direction can be calculated and controlled on the basis of the difference between the lengths Ly and L.theta. as measured by the laser interferometers IFY and IF.theta. as well as the distance d between the laser beams of the interferometers IFY and IF.theta., such as follows:
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”The control of the motor for rotating to adjust for theta reads on the generation and use of the ACF.] for a metrology tool useful in a fabrication process [Column 2 lines 53-58 – “FIG. 1 is a perspective view schematically showing a step-and-repeat type semiconductor device manufacturing exposure apparatus according to an embodiment of the present invention.FIG. 2 is a schematic plan view of an X-Y-.theta. stage of this embodiment.”], the method comprising:
providing said metrology tool [See Figs. 1 and 2], said metrology tool comprising:
a stage [Column 3 lines 57-60 – “Denoted at MX and MY are motors for moving the X-Y-.theta. stage XYS in the X and Y directions. An unshown .theta. motor (M.theta.) is provided to rotate the X-Y-.theta. stage in a rotational .theta. direction.”]; and
a housing [The support structure for stage XYS, interferometer IFY, and interferometer IFθ. Although not explicitly depicted in Fig. 1, such support structure would have been understood to have been present as stage XYS rotates relative to interferometer IFY and interferometer IFθ as depicted in Fig. 2.];
at least two radiation transmitter-receiver pairs [Fig. 2 – Interferometers IFY and IFθ], wherein said radiation transmitter-receiver pairs transmit and receive laser light [Column 4 lines 45-59 – “laser interferometers IFY and IF.theta.”]; and
at least one radiation reflector [Fig. 2 - MRY];
measuring a rotational orientation of said stage in an x-y plane relative to said housing; and generating said ACF for said stage based at least partially on said rotational orientation [Column 4 lines 40-59 – “FIG. 2 is a schematic illustration of the X-Y-.theta. stage XYS, as the same is viewed from above (along the Z axis). The position of the X-Y-.theta. stage XYS with respect to the X and Y directions can be controlled on the basis of the lengths Lx and Ly as measured by the laser interferometers IFX and IFY. The position with respect to the .theta. direction can be calculated and controlled on the basis of the difference between the lengths Ly and L.theta. as measured by the laser interferometers IFY and IF.theta. as well as the distance d between the laser beams of the interferometers IFY and IF.theta., such as follows:
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The control of the motor for rotating to adjust for theta reads on the generation and use of an ACF.];
positioning a sample within said metrology tool [Column 5 lines 28-29 – “Subsequently, at step S003, a wafer is moved onto the wafer stage WS by means of a conveying hand, not shown. It is held by the wafer stage WS through attraction.”Column 6 lines 6-9 – “Referring to the flow chart of FIG. 6, description will be made of a case where a pattern is superposedly printed on a wafer W having a pattern already formed thereon. Steps S101-S103 are similar to steps S001-S003 of FIG. 5.”See Fig. 6.]; and
measuring said sample with said metrology tool thereby generating at least one output signal [See Column 8 lines 7-33, the measurement of the marks per Figs. 9A/B per S107.] generated in the x-y plane [Figs. 9A/B:
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], said sample being mounted on said stage and said stage having said rotational orientation during said measuring [Column 8 lines 24-26 discloses that θy and θx are present.], wherein said measuring includes receiving light from said sample at a metrology head [See Column 8 lines 7-33, the measurement of the marks per Figs. 9A/B per S107 through use of scope OS.].
Although Nakai discloses performing lithography [Column 4 lines 59-61 – “Subsequently, at steps S109-S111, the circuit pattern of the reticle RT is lithographically transferred to the wafer W in a step-and-repeat manner.”] in a manner to control misregistration between at least two layers formed on the sample, a dimension of one or more features formed on said sample, or a dimension of one or more spaces between features formed on said sample [See Figs. 3 and 4 and corresponding text], Nakai fails to disclose generating at least one quality parameter value of said sample in the x-y plane at least partially based on said ACF and said output signal, wherein said quality parameter value is a misregistration between at least two layers formed on the sample, a dimension of one or more features formed on said sample, or a dimension of one or more spaces between features formed on said sample; and adjusting a lithography step to ameliorate misregistration between said layers on said sample using said quality parameter value.
However, Ghinovker teaches that evaluating the alignment between layers of a semiconductor wafer is critical to ensuring proper fabrication [Paragraph [0002] – “The measurement of overlay error for patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer.”]. It would have been obvious to use the measured rotation of the stage and the measured rotation of the marks to evaluate the rotational alignment of the layers of a semiconductor wafer in order to ascertain whether the wafer is assembled properly or not as a process control parameter and to perform lithology in response to ensure that further wafer layers are properly etched.
Regarding Claim 3, Nakai discloses that said positioning said sample within said metrology tool further comprises:
mounting said sample on said stage [Column 5 lines 28-29 – “Subsequently, at step S003, a wafer is moved onto the wafer stage WS by means of a conveying hand, not shown. It is held by the wafer stage WS through attraction.”]; and
moving said stage relative to said housing [Column 8 lines 16-17 – “In this step, however, the X-Y-.theta. stage XYS is rotated, as compared with the case of step S105.”].
Regarding Claim 4, Nakai discloses that measuring said sample further comprises measuring at least one rotationally asymmetric misregistration target formed on said sample [Column 8 lines 7-11, 16-17, and 41-42 – “Subsequently, at step S107, the shot array measurement and the chip rotation measurement having been made at step S105 are executed again with higher precision by using an increased number of marks to be measured. … In this step, however, the X-Y-.theta. stage XYS is rotated, as compared with the case of step S105. … even if the rotation produces an Abbe error, it can be measured through the measurement at this step.”].
Regarding Claim 5, Nakai fails to disclose that said quality parameter value is a misregistration between at least a first layer formed on said sample and a second layer formed on said sample. However, Ghinovker teaches that evaluating the alignment between layers of a semiconductor wafer is critical to ensuring proper fabrication [Paragraph [0002] – “The measurement of overlay error for patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer.”]. It would have been obvious to use the measured rotation of the stage and the measured rotation of the marks to evaluate the rotational alignment of the layers of a semiconductor wafer in order to ascertain whether the wafer is assembled properly or not as a process control parameter.
Regarding Claim 6, Nakai fails to disclose that said quality parameter value is a dimension of at least one feature formed on said sample. However, Ghinovker teaches that evaluating the alignment between layers of a semiconductor wafer is critical to ensuring proper fabrication [Paragraph [0002] – “The measurement of overlay error for patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer.”]. It would have been obvious to use the measured rotation of the stage and the measured rotation of the marks to evaluate the rotational alignment (a dimension) of the layers of a semiconductor wafer in order to ascertain whether the wafer is assembled properly or not as a process control parameter.
Regarding Claim 7, Nakai fails to disclose that said quality parameter value is a dimension of at least one space between features formed on said sample. However, Ghinovker teaches that evaluating the alignment between layers of a semiconductor wafer is critical to ensuring proper fabrication [Paragraph [0002] – “The measurement of overlay error for patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer.”]. It would have been obvious to use the measured rotation of the stage and the measured rotation of the marks (and the spacing between them) to evaluate the rotational alignment of the layers of a semiconductor wafer in order to ascertain whether the wafer is assembled properly or not as a process control parameter.
Regarding Claim 8, Nakai discloses that said measuring said rotational orientation of said stage relative to said housing further comprises: measuring a first linear distance between a first portion of said stage and said housing [Fig. 2 – Ly]; measuring a second linear distance between a second portion of said stage and said housing [Fig. 2 – Lθ]; and calculating said rotational orientation of said stage relative to said housing at least partially based on said first linear distance and said second linear distance [See Figs. 1/2.Column 4 lines 45-59 – “The position with respect to the .theta. direction can be calculated and controlled on the basis of the difference between the lengths Ly and L.theta. as measured by the laser interferometers IFY and IF.theta. as well as the distance d between the laser beams of the interferometers IFY and IF.theta., such as follows:
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”].
Regarding Claim 9, Nakai discloses a system for generating an angular calibration factor (ACF)[Column 4 lines 45-59 – “The position with respect to the .theta. direction can be calculated and controlled on the basis of the difference between the lengths Ly and L.theta. as measured by the laser interferometers IFY and IF.theta. as well as the distance d between the laser beams of the interferometers IFY and IF.theta., such as follows:
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”The control of the motor for rotating to adjust for theta reads on the generation and use of the ACF.], the system comprising: a metrology tool [See Figs. 1 and 2] comprising:
a stage [Column 3 lines 57-60 – “Denoted at MX and MY are motors for moving the X-Y-.theta. stage XYS in the X and Y directions. An unshown .theta. motor (M.theta.) is provided to rotate the X-Y-.theta. stage in a rotational .theta. direction.”]; and
a housing [The support structure for stage XYS, interferometer IFY, and interferometer IFθ. Although not explicitly depicted in Fig. 1, such support structure would have been understood to have been present as stage XYS rotates relative to interferometer IFY and interferometer IFθ as depicted in Fig. 2.]; and
an angle monitoring sub-system (AMSS)[See the CU and associated components in Fig. 1.Column 3 lines 29-31 – “The control unit CU comprises computers, memories, image processing means, X-Y-.theta. stage control means, etc.”] operative to measure a rotational orientation of said stage in an x-y plane relative to said housing and to generate said ACF based at least partially on said rotational orientation [Column 4 lines 40-59 – “FIG. 2 is a schematic illustration of the X-Y-.theta. stage XYS, as the same is viewed from above (along the Z axis). The position of the X-Y-.theta. stage XYS with respect to the X and Y directions can be controlled on the basis of the lengths Lx and Ly as measured by the laser interferometers IFX and IFY. The position with respect to the .theta. direction can be calculated and controlled on the basis of the difference between the lengths Ly and L.theta. as measured by the laser interferometers IFY and IF.theta. as well as the distance d between the laser beams of the interferometers IFY and IF.theta., such as follows:
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The control of the motor for rotating to adjust for theta reads on the generation and use of an ACF.], wherein the AMSS includes:
at least two radiation transmitter-receiver pairs [Fig. 2 – Interferometers IFY and IFθ], wherein said radiation transmitter-receiver pairs transmit and receive laser light [Column 4 lines 45-59 – “laser interferometers IFY and IF.theta.”]; and
at least one radiation reflector [Fig. 2 - MRY]; and
a metrology head that receives light from a sample and generates an output signal of said sample [See Column 8 lines 7-33, the measurement of the marks per Figs. 9A/B per S107 through use of scope OS.] in the x-y plane [Figs. 9A/B:
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].
Although Nakai discloses performing lithography [Column 4 lines 59-61 – “Subsequently, at steps S109-S111, the circuit pattern of the reticle RT is lithographically transferred to the wafer W in a step-and-repeat manner.”] in a manner to control misregistration between at least two layers formed on the sample, a dimension of one or more features formed on said sample, or a dimension of one or more spaces between features formed on said sample [See Figs. 3 and 4 and corresponding text], Nakai fails to disclose a quality parameter generator (QPG), wherein said AMSS provides said ACF to said QPG, wherein said QPG is operative to generate a quality parameter value of a sample in the x-y plane based at least partially on said ACF and an output signal of said sample generated by said metrology tool, wherein said quality parameter value is a misregistration between at least two layers formed on the sample, a dimension of one or more features formed on said sample, or a dimension of one or more spaces between features formed on said sample, and wherein said QPG is further configured to determine instructions to adjust a lithography step to ameliorate misregistration between said layers on said sample using said quality parameter value.
However, Ghinovker teaches that evaluating the alignment between layers of a semiconductor wafer is critical to ensuring proper fabrication [Paragraph [0002] – “The measurement of overlay error for patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer.”]. It would have been obvious to use the measured rotation of the stage and the measured rotation of the marks to evaluate the rotational alignment of the layers of a semiconductor wafer (using control unit CU or console CS) in order to ascertain whether the wafer is assembled properly or not as a process control parameter and to perform lithology in response to ensure that further wafer layers are properly etched.
Regarding Claim 12, Nakai fails to disclose that said radiation transmitter-receiver pairs are each fixedly mounted on said stage; and said radiation reflector is fixedly mounted on said housing. This is because the arrangement in Fig. 2 is inverted with the respect to the location of the interferometers and radiation reflector. However, re-arranging the interferometers and radiation reflector as recited amounts to an obvious design choice that would not affect the measurement and angle determination process. Such a type of re-arrangement of sensing components has been held obvious by the Court (See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007)).
Regarding Claim 13, Nakai discloses that said radiation transmitter-receiver pairs are each fixedly mounted on said housing [Fig. 2 – Interferometers IFY and IFθ]; and said radiation reflector is fixedly mounted on said stage [Fig. 2 - MRY].
Regarding Claim 14, Nakai discloses that said angle monitoring sub-system comprises at least two encoders [Fig. 2 – Interferometers IFY and IFθ measure rotation].
Regarding Claim 15, Nakai discloses that said stage is movable relative to said housing [Column 3 lines 57-60 – “Denoted at MX and MY are motors for moving the X-Y-.theta. stage XYS in the X and Y directions. An unshown .theta. motor (M.theta.) is provided to rotate the X-Y-.theta. stage in a rotational .theta. direction.”].
Regarding Claim 16, Nakai discloses that said metrology tool comprises one of: an imaging-based misregistration metrology tool [See Column 8 lines 7-33, the measurement of the marks per Figs. 9A/B per S107 through use of scope OS.]; a scatterometry-based misregistration metrology tool; a critical dimension metrology tool; a shape metrology tool; a film metrology tool; an electron-beam metrology tool; or an x-ray-based metrology tool.
Regarding Claim 18, Nakai fails to disclose measuring said sample with said metrology tool thereby generating at least one output signal [See Column 8 lines 7-33, the measurement of the marks per Figs. 9A/B per S107.], but fails to disclose that said QPG is operative to generate a quality parameter value of a sample based at least partially on said ACF and an output signal of said sample generated by said metrology tool. However, Ghinovker teaches that evaluating the alignment between layers of a semiconductor wafer is critical to ensuring proper fabrication [Paragraph [0002] – “The measurement of overlay error for patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer.”]. It would have been obvious to use the measured rotation of the stage and the measured rotation of the marks to evaluate the rotational alignment of the layers of a semiconductor wafer (using control unit CU or console CS) in order to ascertain whether the wafer is assembled properly or not as a process control parameter.
Regarding Claim 19, Nakai fails to disclose that said quality parameter value is a dimension of at least one feature formed on said sample. However, Ghinovker teaches that evaluating the alignment between layers of a semiconductor wafer is critical to ensuring proper fabrication [Paragraph [0002] – “The measurement of overlay error for patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer.”]. It would have been obvious to use the measured rotation of the stage and the measured rotation of the marks to evaluate the rotational alignment (a dimension) of the layers of a semiconductor wafer in order to ascertain whether the wafer is assembled properly or not as a process control parameter.
Regarding Claim 20, Nakai fails to disclose that said quality parameter value is a dimension of at least one space between features formed on said sample. However, Ghinovker teaches that evaluating the alignment between layers of a semiconductor wafer is critical to ensuring proper fabrication [Paragraph [0002] – “The measurement of overlay error for patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer.”]. It would have been obvious to use the measured rotation of the stage and the measured rotation of the marks (and the spacing between them) to evaluate the rotational alignment of the layers of a semiconductor wafer in order to ascertain whether the wafer is assembled properly or not as a process control parameter.
Regarding Claim 21, Nakai fails to disclose that said quality parameter value is a misregistration between at least a first layer formed on said sample and a second layer formed on said sample. However, Ghinovker teaches that evaluating the alignment between layers of a semiconductor wafer is critical to ensuring proper fabrication [Paragraph [0002] – “The measurement of overlay error for patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer.”]. It would have been obvious to use the measured rotation of the stage and the measured rotation of the marks to evaluate the rotational alignment of the layers of a semiconductor wafer in order to ascertain whether the wafer is assembled properly or not as a process control parameter.
Regarding Claim 22, Nakai discloses that said sample comprises a semiconductor device wafer [wafer W].
Regarding Claim 23, Nakai discloses a misregistration target for calculating a misregistration between at least a first layer formed on said sample and a second layer formed on said sample for use with the system of claim 9, said misregistration target being rotationally asymmetric [See Figs. 9A/B.Column 8 lines 7-11, 16-17, and 41-42 – “Subsequently, at step S107, the shot array measurement and the chip rotation measurement having been made at step S105 are executed again with higher precision by using an increased number of marks to be measured. … In this step, however, the X-Y-.theta. stage XYS is rotated, as compared with the case of step S105. … even if the rotation produces an Abbe error, it can be measured through the measurement at this step.”].
Regarding Claims 24 and 25, Nakai discloses that said output signal is radiation that is reflected or refracted by said sample [Column 4 lines 27-35 – “Off-axis scope OS is a mark observing microscope having its focal plane placed substantially at the same Z position as the projection lens LN. By using this microscope OS, an image of a mark transferred to the wafer W or the photochromic plate, on the wafer stage WS, can be picked up. On the basis of the image output signal, the control unit CU then operates to calculate the amount of positional deviation of the image-picked-up mark from the center of the off-axis scope OS with respect to the X and Y directions.”].
Response to Arguments
Applicant argues:
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Examiner’s Response:
It is not asserted that Ghinovker discloses Applicant’s quality parameter value. Rather, Ghinovker teaches that evaluating the alignment between layers of a semiconductor wafer is critical to ensuring proper fabrication [Paragraph [0002] – “The measurement of overlay error for patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer.”]. It would have been obvious to use the measured rotation of the stage and the measured rotation of the marks to evaluate the rotational alignment of the layers of a semiconductor wafer in order to ascertain whether the wafer is assembled properly or not as a process control parameter and to perform lithology in response to ensure that further wafer layers are properly etched.
Applicant argues:
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Examiner’s Response:
The Examiner respectfully disagrees. It would have been obvious to apply the teaching of Ghinovker to the context of Nakai by using the measured rotation of the stage and the measured rotation of the marks (per Nakai) to evaluate the rotational alignment of the layers of a semiconductor wafer (per Ghinovker) in order to ascertain whether the wafer is assembled properly or not as a process control parameter and to perform lithology in response to ensure that further wafer layers are properly etched. The recited subject matter, all of which has been addressed, would have been obvious in light of the combination of Nakai and the teaching of Ghinovker.
Applicant argues:
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Examiner’s Response:
Claim 1 does not recite performing “post-fabrication metrology measurements.” Rather, Claim 1 recites in the last element “adjusting a lithography step to ameliorate misregistration between said layers on said sample using said quality parameter value,” which would appear to be occurring during fabrication because it is not apparent as to how one could “ameliorate misregistration between said layers” during post-fabrication.
Applicant argues:
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Examiner’s Response:
The instant grounds for rejection do not contemplate incorporating these aspects of Ghinovker into the context of Nakai.
Claim 1 does not recite performing “post-fabrication metrology measurements.” Rather, Claim 1 recites in the last element “adjusting a lithography step to ameliorate misregistration between said layers on said sample using said quality parameter value,” which would appear to be occurring during fabrication because it is not apparent as to how one could “ameliorate misregistration between said layers” during post-fabrication.
Claim 1 does not recite “correct[ing] quality parameter values.”
No improper hindsight has been used as Nakai discloses the use of the recited ACF and Ghinovker teaches that evaluating the alignment between layers of a semiconductor wafer is critical to ensuring proper fabrication [Paragraph [0002] – “The measurement of overlay error for patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer.”]. It would have been obvious to apply the teaching of Ghinovker to the context of Nakai by using the measured rotation of the stage and the measured rotation of the marks (per Nakai) to evaluate the rotational alignment of the layers of a semiconductor wafer (per Ghinovker) in order to ascertain whether the wafer is assembled properly or not as a process control parameter and to perform lithology in response to ensure that further wafer layers are properly etched.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20040135980 A1 (See Fig. 5) – In-process Correction Of Stage Mirror Deformations During A Photolithography Exposure Cycle
US 20220293448 A1 – Wafer Positioning Method And Apparatus
US 20150115986 A1 – ALIGNMENT TESTING FOR TIERED SEMICONDUCTOR STRUCTURE
US 20010016293 A1 – Method For Positioning Substrate
US 20180275530 A1 – Multi-Layer Overlay Metrology Target And Complimentary Overlay Metrology Measurement Systems
US 20130004283 A1 – Control Method And Apparatus For Positioning A Stage
US 20090224413 A1 – APPARATUS AND METHODS FOR DETERMINING OVERLAY OF STRUCTURES HAVING ROTATIONAL OR MIRROR SYMMETRY
US 6495847 B1 – Stage Control Apparatus And Exposure Apparatus
US 7292050 B1 – Measuring Rotational Misalignment Using Spatial Interference Patterns
US 6278957 B1 – Alignment Method And Apparatus Therefor
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYLE ROBERT QUIGLEY whose telephone number is (313)446-4879. The examiner can normally be reached 9AM-5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arleen Vazquez can be reached at (571) 272-2619. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KYLE R QUIGLEY/Primary Examiner, Art Unit 2857
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