DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The following office action is in response to the amendment and remarks filed on 11/7/25.
Applicant’s amendment to claims 1 and 13 is acknowledged.
Claims 1-20 are pending and claims 18-20 are withdrawn.
Claims 1-17 are subject to examination at this time.
Response to Arguments
Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7 and 12-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US Publication No. 2022/0367320 A1 in view of Hirabayashi, JP 2009186378 A (see attached English machine translation).
Lee teaches:
A semiconductor die, comprising (see fig. 1 rotated 180 degrees):
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a semiconductor substrate (111);
a plurality of transistors (121) arranged at a front side of the semiconductor substrate;
an electrically conductive structure (150), wherein a top surface of the electrically conductive structure is contacted at the front side of the semiconductor substrate (111) and a bottom surface of the electrically conductive structure is contacted at a backside of the semiconductor substrate (111); and
a backside metallization layer stack (140) attached to the backside of the semiconductor substrate, wherein a first portion (e.g. 141 top) of a wiring structure of the backside metallization layer stack is formed in a first metallization layer (e.g. 140 top) of the backside metallization layer stack, a second portion (e.g. 141 bottom) of the wiring structure is formed in a second metallization layer (e.g. 140 bottom ) of the backside metallization layer stack, and a tapered vertical connection (143) is formed between the first portion of the wiring structure and the second portion of the wiring structure, wherein the first metallization layer (e.g. 140 top) is closer to the semiconductor substrate (111) than the second metallization layer (e.g. 140 bottom), …wherein the semiconductor die (100) is a single semiconductor die and the plurality of transistors (121), the electrically conductive structure (150), and the backside metallization layer stack (140) belong to the single semiconductor die (100). See Lee at para. [0022] – [0061].
Regarding claim 1:
Lee does not expressly teach:
wherein a width of the tapered vertical connection increases towards the first metallization layer,
In an analogous art, Hirabayashi teaches:
(see figs. 1-3) wherein a width of the tapered vertical connection (10a) increases towards a top surface of a substrate (1). Hirabayashi teaches vertical connections (10a) having both a forward taper and a reverse taper. See Hirabayashi at English machine translation pages 5-6.
It would have been obvious to one of ordinary skill in the art to modify Lee with Hirabayashi to form the “wherein a width of the tapered vertical connection increases towards the first metallization layer” because forming vertical connections having both a forward taper and a reverse taper can help suppress bending of the substrate. See Hirabayashi at English machine translation page 3.
Lee further teaches:
2. The semiconductor die according to claim 1, wherein the first portion of the wiring structure (e.g. 141 top) is a contact interface structure (e.g. 141 top forming interface with 150) connected to the bottom surface of the electrically conductive structure (150), fig. 1.
3. The semiconductor die according to claim 2, wherein the backside metallization layer stack (140) further comprises a bonding surface layer (113) arranged besides the contact interface structure (e.g. 141 top forming interface with 150), fig. 1.
Regarding claim 3:
Lee is silent the bonding surface layer (133) comprises at least one of silicon carbon nitride, silicon oxide or polyimide.
However, it would have been obvious to one having ordinary skill in the art to form the bonding surface layer (133) comprises at least one of silicon carbon nitride, silicon oxide or polyimide, since it is within the general skill of a worker in the art to select known material on the basis of its suitability for the intended purpose as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose.
Lee further teaches:
4. The semiconductor die according to claim 2, wherein a length of the contact interface structure (e.g. 141 top forming interface with 150) is at most 100 nm (e.g. The width of 150 is 50-250 nm, para. [0047])
5. The semiconductor die according to claim 1, wherein a minimal lateral dimension of the bottom surface of the electrically conductive structure is at most 100nm (e.g. The width of 150 is 50-250 nm, para. [0047])
Regarding claims 4-5:
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
7. The semiconductor die according to claim 1, wherein the electrically conductive structure (150) is electrically insulated (115) from the semiconductor substrate, para. [0045], fig. 1.
12. The semiconductor die according to claim 1, further comprising a front side wiring layer stack (130) formed on the front side of the semiconductor substrate (111), wherein the front side wiring layer stack comprises a front side wiring structure (138) electrically connected to the wiring structure (141) of the backside metallization layer stack (140), fig. 1.
13. A semiconductor device, comprising (see fig. 9):
the semiconductor die (100) according to claim 1; and
a package substrate (400) attached to a front side of the semiconductor die.
14. The semiconductor device according to claim 13, further comprising a redistribution layer (200+190) formed on a backside of the semiconductor die (100), wherein the redistribution layer is electrically connected to a second contact interface structure (e.g. 141 bottom forming interface with 190) of the backside metallization layer stack (140), fig. 9.
15. The semiconductor device according to claim 14, wherein the second portion of the wiring structure (e.g. 141 bottom) is the second contact interface structure (e.g. 141 bottom forming interface with 190) connected to the backside metallization layer stack (140), fig. 9.
16. The semiconductor device according to claim 14, further comprising an interconnect structure (310) arranged laterally beside the semiconductor die (100) and extending from the redistribution layer (200+190) to the package substrate (400), fig. 9.
17. The semiconductor device according to claim 16, further comprising a mold compound (320) embedding the semiconductor die (100) and the interconnect structure (310), fig. 9
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Lee with the teachings of Hirabayashi because forming vertical connections having both a forward taper and a reverse taper can help suppress bending of the substrate. See Hirabayashi at English machine translation page 3.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Hirabayashi, as applied to claim 1 above, and further in view of Chang et al., US Publication No. 2016/0190233 a1 (of record).
Regarding claim 6:
Lee and Hirabayashi teach all the limitations of claim 1 above, and Lee further teaches the transistors comprise field effect transistors such as MOSFETS at para. [0030].
Leedoes not expressly teach:
wherein the plurality of transistors comprises at least one of a fin field-effect transistor, a nanowire transistor, a ribbon transistor or a gate all around transistor.
In an analogous art, Chang teaches field effect transistors can comprise a fin field-effect transistor (finFET) or a gate all around transistor (GAA). See Chang at para. [0001].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Lee with the teachings of Chang because “Since the drive currents of transistors are proportional to the channel widths, the drive currents of the FinFETs and GAA transistors are increased over that of conventional planar transistors.” See Chang at para. [0001].
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Hirabayashi, as applied to claim 1 above, and further in view of Reisner, US Publication No. 2008/0315356 A1 (of record).
Regarding claims 8 and 9:
Lee and Hirabayashi teach all the limitations of claim 1 above, but do not expressly teach:
wherein a layer of the backside metallization layer stack comprises a dielectric material of a capacitor;
wherein a layer of the backside metallization layer stack comprises a magnetic material of an inductor.
In an analogous art, Reisner teaches:
(see fig. 1A) wherein a layer of the backside metallization layer (105) stack comprises a dielectric material of a capacitor (114, 116);
wherein a layer of the backside metallization layer stack (105) comprises a magnetic material of an inductor (110, 112). See Reisner at para. [0024] – [0025].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Lee with the teachings of Reisner because integrating passive devices on the backside metallization layer can save space by forming passive devices on a surface that is typically utilized only for backside metallization. See Reisner at para. [0025].
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Hirabayashi, as applied to claim 1 above, and further in view of Bauer et al., German Publication No. DE 102013108075 A1 (of record, see attached English machine translation).
Regarding claim 10:
Lee and Hirabayashi teach all the limitations of 1 above, but do not expressly teach:
wherein the backside metallization layer stack comprises a circuit element electrically connected to the electrically conductive structure.
In an analogous art, Bauer teaches:
(see fig. 2) wherein the backside metallization layer stack (238) comprises a circuit element (e.g. source/drain region on back side of chip). See Bauer at English machine translation page 10, “The chip backside metallization layer 238 can provide an electrical connection, e.g. B. with one or more electrical circuits on the chip front 106 , z. In the active chip region 226 , For example, the chip backside metallization layer 238 provide an electrical connection to a source / drain region on the back side of a power semiconductor device.”)
It would have been obvious to a person of ordinary skill in the art to modify Lee to form the backside metallization layer stack to comprise a circuit element to be electrically connected to the electrically conductive structure because Bauer teaches electrical circuits can be formed on the chip front or back of the chip. See Bauer at English machine translation page 7.
Regarding claim 11:
Bauer further teaches:
further comprising circuitry comprising at least one transistor of the plurality of transistors (e.g. electrical circuit on chip front), wherein the circuit element (e.g. source/drain region on back side) is electrically connected to the transistor of the circuitry. See Bauer at English machine translation page 10, “The chip backside metallization layer 238 can provide an electrical connection, e.g. B. with one or more electrical circuits on the chip front 106 , z. In the active chip region 226 , For example, the chip backside metallization layer 238 provide an electrical connection to a source / drain region on the back side of a power semiconductor device.”)
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Lee with the teachings of Bauer
to form “the circuit element (e.g. source/drain region on back side of chip) is electrically connected to the transistor of the circuitry (e.g. electrical circuit on chip front) via the electrically conductive structure” in order to transmit and receive signals between the back of the chip and the chip front. See Bauer at English machine translation page 2, “…the active chip region is set up for transmitting a signal and / or for receiving a signal.”
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
27 February 2026