DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 17 October 2025 has been entered.
Response to Arguments
Applicant’s arguments/amendments, see Remarks/claims, filed 17 October 2025, with respect to the rejection(s) of claim(s) 1-7 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Debendra Millik et al. (US 20050093120 A1), as detailed below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Debendra Millik et al. (US 2005/0093120 A1; hereinafter Millik) in view of Lakshminarayana Pappu (US 2018/0096735 A1; hereinafter Pappu).
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Regarding Claim 1, Millik teaches a semiconductor device comprising (Fig. 2a/2d; ¶0020-¶0029):
a first semiconductor die (processor die 112; ¶0005) comprising a plurality of transistors, wherein the first semiconductor die (112) is arranged over a package substrate (110A; ¶0020) or a circuit board;
a second semiconductor die (VRM 202; ¶0003, ¶0021) comprising power supply circuitry configured to generate a supply voltage for the plurality of transistors of the first semiconductor die (112) (as described in ¶0021-¶0022); and
a heat spreader structure (204; ¶0021) arranged over the second semiconductor die (202) (as shown in Fig. 2a),
wherein a first power supply routing for a reference voltage or a power supply voltage extends from the heat spreader structure (204) to the first semiconductor die (112) and the second semiconductor die (202) (first routing 216 provides a reference voltage {ground} connection, utilizing the main body of 204 to extend and electrically connect 202 and 112 to ground via respective 232, 204, 214A, 110A, 118; ¶0024 and ¶0027; this is opposed to separate ground planes for the processor die, as described in ¶0028), and a second power supply routing for a reference voltage or a power supply voltage extends from the package substrate (110A) or the circuit board to the second semiconductor die (202) directly without via the heat spreader structure (204) (as shown in Fig. 2a/2d; power is routed to/from 110A directly to 202 via separate respective interconnect layers 232, 218, and respective 214 represented by 223/224/226 without utilizing heat spreader 204, as described in ¶0025, ¶0029).
Millik does not explicitly state the processor die (112) comprises a plurality of transistors. However, processors are well known to comprise transistors. In the same field of endeavor, Pappu discloses in ¶0146 that circuit dies (such as a processor) include transistors. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, that the processor of Millik would include transistors (such as in Pappu) in order to make a functional device.
Regarding Claim 3, modified Millik teaches the semiconductor device of claim 1, wherein a front side of the first semiconductor die (bottom of 112) is configured to connect to the package substrate (110A) or the circuit board (as shown in Fig. 2a, via 118).
Regarding Claim 4, modified Millik teaches the semiconductor device of claim 1, wherein the first power supply routing for the reference voltage or the power supply voltage comprises a first part (body of 204) at the heat spreader structure (204), a second part (respective 232) at the second semiconductor die (202), and a third part (118) at the first semiconductor die (112) (Fig. 2a/2d).
Regarding Claim 7, modified Millik teaches the semiconductor device of claim 1, wherein the heat spreader structure (204) forms a cavity, wherein the first semiconductor die (112) and the second semiconductor die (202) are arranged in the cavity (as shown in Fig. 2a; wherein there is a cavity formed by the heat spreader 204 and 102A; this is commensurate in scope with what is presented in Applicant’s Fig. 1A/1B).
Allowable Subject Matter
Claims 2, 5, and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 2, modified Mallik teaches the semiconductor device of claim 1. However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including wherein: the first power supply routing for the reference voltage or the power supply voltage includes a plurality of electrical connections at an interface of the first semiconductor die and the second semiconductor die; wherein the interface is at a back side of the first semiconductor die and a front side of the second semiconductor die.
Regarding Claim 5, modified Millik teaches the semiconductor device of claim 4, and wherein the first part (body of 204) is formed by a part of a main body of the heat spreader structure (204) (¶0023) or an electrically conductive trace arranged on or embedded in the heat spreader structure. However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including: wherein the second part is a through semiconductor via of the second semiconductor die; and wherein the third part is a through semiconductor via of the first semiconductor die.
Regarding Claim 6, modified Millik teaches the semiconductor device of claim 1. However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including: wherein the first power supply routing for the reference voltage or the power supply voltage includes at least one through semiconductor via through the second semiconductor die for providing the reference voltage or the power supply voltage to the first semiconductor die.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898