DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 03, 2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 43, 45, and 49 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claim 43, the limitation “further comprises a second portion” fails to establish “a first portion” that is only recited in claim 38. It is not clear whether the claim should depend on claim 38. Thus, the limitation renders the claim indefinite and clarification is required. As to claim 45, the limitation “further comprises a second contact portion” fails to establish “a first contact portion” that is only recited in claim 38. It is not clear whether the claim should depend on claim 38. Further, the limitation “the first portion” lacks sufficient antecedent basis. Thus, the limitation renders the claim indefinite and clarification is required. As to claim 49, the limitation “a second portion” fails to establish “a first portion”. It is not clear whether the claim should read “a first portion”. Thus, the limitation renders the claim indefinite and clarification is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Application Publication No. 2022/0037268 A1 to Shen et al. (“Shen”). As to claim 1, Shen discloses a semiconductor device, comprising: a first die (612) comprising a semiconductor layer (622) and a memory array (¶ 0044); a second die (512) comprising a substrate (522) and peripheral circuits (¶ 0021) on the substrate (522); wherein the memory array (¶ 0044) is between the semiconductor layer (622) and the substrate (522) in a first direction, the semiconductor layer (622) extends beyond the memory array (¶ 0044) in a second direction perpendicular to the first direction; and a seal ring structure (660) surrounding the memory array (¶ 0044) in a third direction perpendicular to the first direction, wherein the seal ring structure (660) extends through a portion of the semiconductor layer (622) beyond the memory array (¶ 0044) (See Fig. 15, Fig. 26-Fig. 30, Fig. 32-Fig. 34, ¶ 0021-¶ 0024, ¶ 0043-¶ 0046, ¶ 0066-¶ 0078).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-4 and 37-52 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2022/0037268 A1 to Shen et al. (“Shen”) as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2011/0193197 A1 to Farooq et al. (“Farooq”). The teaching of Shen has been discussed above. As to claim 2, although Shen discloses the semiconductor layer (622) (See Fig. 26), Shen does not further disclose wherein the semiconductor layer comprises a plurality of semiconductor portions insulated by a plurality of insulating portions along the second direction. However, Farooq does disclose wherein the semiconductor layer (201) comprises a plurality of semiconductor portions (between 262, 264) insulated by a plurality of insulating portions (262, 264) along the second direction (See Fig. 1-Fig. 7, ¶ 0022-¶ 0036). In view of the teachings of Shen and Farooq, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Shen to have wherein the semiconductor layer comprises a plurality of semiconductor portions insulated by a plurality of insulating portions along the second direction because the insulating portions separate the seal ring structure from the semiconductor layer such that an appropriate bias is applied without interference (See Shen ¶ 0073 and Farooq ¶ 0032). As to claim 3, Shen further discloses wherein the memory array (¶ 0044) is coupled to a first semiconductor portion of the semiconductor layer (622), the seal ring structure (660) extends through a second semiconductor portion of the semiconductor layer (622) outside the memory array (¶ 0044) (See Fig. 30). As to claim 4, although Shen discloses the first die (612) (See Fig. 30), Shen does not further disclose wherein the first die further comprises an insulating layer in the semiconductor layer, wherein the seal ring structure extends through the insulating layer, the insulating layer insulates the seal ring structure from the semiconductor layer. However, Farooq does disclose wherein the first die further comprises an insulating layer (262, 264) in the semiconductor layer (201), wherein the seal ring structure (590) extends through the insulating layer (262, 264), the insulating layer (262, 264) insulates the seal ring structure (590) from the semiconductor layer (201) (See Fig. 1-Fig. 7, ¶ 0022-¶ 0036). In view of the teachings of Shen and Farooq, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Shen to have wherein the first die further comprises an insulating layer in the semiconductor layer, wherein the seal ring structure extends through the insulating layer, the insulating layer insulates the seal ring structure from the semiconductor layer because the insulating layer separates the seal ring structure from the semiconductor layer such that an appropriate bias is applied without interference (See Shen ¶ 0073 and Farooq ¶ 0032). As to claim 37, although Shen discloses the semiconductor layer (622) (See Fig. 30), Shen does not disclose further comprises a contact structure extends through the semiconductor layer, wherein the contact structure is surrounded by the seal ring structure. However, Farooq does disclose further comprises a contact structure (268) extends through the semiconductor layer (201), wherein the contact structure (268) is surrounded by the seal ring structure (590) (See Fig. 1-Fig. 7, ¶ 0022-¶ 0036). In view of the teaching of Farooq, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Shen to have further comprises a contact structure extends through the semiconductor layer, wherein the contact structure is surrounded by the seal ring structure because the contact structure further provides interconnections between the bonded structures (See ¶ 0036). As to claim 38, Shen in view of Farooq further discloses wherein the seal ring structure (660/590) comprises a first portion extends through the semiconductor layer (622/201) along the first direction, the contact structure (268) comprises a first contact portion extends through the semiconductor layer (622/201) along the first direction, wherein a material of the first portion is same with a material of the first contact portion (See Farooq ¶ 0032). As to claim 39, Shen in view of Farooq further discloses wherein the first portion and the first contact portion are formed in a same process (See Farooq ¶ 0032). As to claim 40, Shen in view of Farooq further discloses wherein the seal ring structure (660/590) comprises a first pad structure (670) at a side of the first die (612) away from the substrate (522), the contact structure (268) comprises a second pad structure (670) at a side of the first die (612) away from the substrate (522), wherein a material of the first pad structure (670) is same with a material of the second pad structure (670) (See Shen Fig. 29, ¶ 0073 and Farooq Fig. 3, ¶ 0032) such that the first and second pad structures simultaneously formed provide respective bias voltages to the seal ring and contact structures. As to claim 41, Shen in view of Farooq further discloses wherein the first pad structure (670) and the second pad structure (670) are formed in a same process (See Shen Fig. 29, ¶ 0073 and Farooq Fig. 3, ¶ 0032). As to claim 42, although Shen discloses the seal ring structure (660) (See Fig. 33), Shen does not further disclose wherein the seal ring structure comprises a plurality of seal ring portions spaced from each other along the third direction. However, Farooq does disclose wherein the seal ring structure (590) comprises a plurality of seal ring portions (266) spaced from each other along the third direction (See Fig. 1-Fig. 7, ¶ 0022-¶ 0036). In view of the teaching of Farooq, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Shen to have wherein the seal ring structure comprises a plurality of seal ring portions spaced from each other along the third direction because a better crack stop is provided (See ¶ 0030, ¶ 0031). As to claim 43, Shen further discloses wherein the seal ring structure (660) further comprises a second portion (in 612), a first connect structure (670), a second connect structure (661) and a third portion (in 512) in the first direction, the second portion (in 612) extends in the first die (612) along the first direction and from the semiconductor layer (622) to the first connect structure (670), the third portion (in 512) extends in the second die (512) along the first direction and into (¶ 0070) the substrate (522), the first connect structure (670) is bonded with the second connect structure (661) (See Fig. 32, Fig. 33).
As to claim 44, Shen discloses further comprises a plurality of contact structures (542, 642), a length of a first seal ring portion of the seal ring structure (660) in the third direction is greater than a spacing between two adjacent contact structures (542, 642) of the plurality of contact structures (542, 642) (See Fig. 34). As to claim 45, Shen further disclose wherein the contact structure further comprises a second contact portion (532, 632) outside the memory array (¶ 0044), extending along the first direction and coupled to the first portion, the peripheral circuits (¶ 0021) comprise I/O circuit coupled to the second contact portion (532, 632) (See Fig. 30). As to claim 46, although Shen discloses a semiconductor device, comprising: a first die (612) comprising a semiconductor layer (622), and a memory array (¶ 0044); a second die (512) comprising a substrate (522), and peripheral circuits (¶ 0021) on the substrate (522); and a seal ring structure (660) comprises a first pad structure (670), wherein the first pad structure (670) is at a side of the first die (612) away from the second die (512) in a first direction (See Fig. 15, Fig. 26-Fig. 30, Fig. 32-Fig. 34, ¶ 0021-¶ 0024, ¶ 0043-¶ 0046, ¶ 0066-¶ 0078), Shen does not further disclose the seal ring structure comprises a first seal ring structure and a second seal ring structure, the first seal ring structure and the second seal ring structure surround the memory array in a third direction perpendicular to the first direction, the first pad structure is in contact with the first seal ring structure and the second seal ring structure.
However, Farooq does disclose the seal ring structure (590) comprises a first seal ring structure (266) and a second seal ring structure (266), the first seal ring structure (266) and the second seal ring structure (266) surround devices in a third direction perpendicular to the first direction, the first pad structure (105) is in contact with the first seal ring structure (266) and the second seal ring structure (266) (See Fig. 1-Fig. 7, ¶ 0022-¶ 0036). In view of the teachings of Shen and Farooq, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Shen to have the seal ring structure comprises a first seal ring structure and a second seal ring structure, the first seal ring structure and the second seal ring structure surround the memory array in a third direction perpendicular to the first direction, the first pad structure is in contact with the first seal ring structure and the second seal ring structure because the seal ring structure is properly biased and providing a better crack stop (See Shen ¶ 0073 and Farooq ¶ 0030, ¶ 0031). As to claim 47, Shen in view of Farooq further discloses wherein the semiconductor layer (622/201) comprises a plurality of semiconductor portions (between 262 and 264) insulated by a plurality of insulating portions (262, 264) along a second direction perpendicular to the first direction (See Farooq Fig. 3). As to claim 48, Shen in view of Farooq further discloses wherein the first seal ring structure (266) comprises a plurality of first seal ring portions (266) spaced from each other along the third direction (See Farooq Fig. 7). As to claim 49, Shen in view of Farooq further discloses wherein the first seal ring structure (660/266) comprises a second portion (in 612), a first connect structure (670), a second connect structure (661) and a third portion (in 512) in the first direction, the second portion (in 612) extends in the first die (612) along the first direction and from the semiconductor layer (622) to the first connect structure (670), the third portion (in 512) extends in the second die (512) along the first direction and into (¶ 0070) the substrate (522), the first connect structure (670) is bonded with the second connect structure (661) (See Fig. 32, Fig. 33). As to claim 50, Shen in view of Farooq discloses further comprises a contact structure (268) extends through the semiconductor layer (622/201), wherein the contact structure (268) is surrounded by the seal ring structure (660/590) (See Farooq Fig. 3). As to claim 51, Shen in view of Farooq further discloses wherein the contact structure (268) comprises a second pad structure (670) at a side of the first die (612) away from the substrate (522), wherein a material of the first pad structure (670) is same with a material of the second pad structure (670) (See Shen Fig. 29, ¶ 0073 and Farooq Fig. 3, ¶ 0032) such that the first and second pad structures simultaneously formed provide respective bias voltages to the seal ring and contact structures. As to claim 52, Shen in view of Farooq further discloses wherein the first pad structure (670) and the second pad structure (670) are formed in a same process (See Shen Fig. 29, ¶ 0073 and Farooq Fig. 3, ¶ 0032). Further regarding the claims above, the limitation “in a same process” is a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. It has been held it has been held that “The Patent Office bears a lesser burden of proof in making out a case of prima facie obviousness for product-by-process claims because of their peculiar nature” than when a product is claimed in the conventional fashion. In re Fessmann, 489 F.2d 742, 744, 180 USPQ 324, 326 (CCPA 1974). Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983). The structure implied by the process steps should be considered when assessing the patentability of product-by-process claims over the prior art, especially where the product can only be defined by the process steps by which the product is made, or where the manufacturing process steps would be expected to impart distinctive structural characteristics to the final product. See, e.g., In re Garnero, 412 F.2d 276, 279, 162 USPQ 221, 223 (CCPA 1979).
Conclusion
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/DAVID CHEN/Primary Examiner, Art Unit 2815
