DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office Action is in response to Amendments/Remarks filed on September 09, 2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 7-8, 21, and 33-36 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Application Publication No. 2022/0262695 A1 to Chang (“Chang”). As to claim 1, Chang discloses a semiconductor device, comprising: a first die (bottom) having a first side and a second side, the first die (bottom) comprising: an insulating layer (50A, 104, 150, 312) at the first side; a silicon layer (102) within the insulating layer (50A, 104, 150, 312), the silicon layer (102) having a plurality of discontinuous portions (between/outside 162, 410) in a direction perpendicular to a direction from the first side to the second side; first circuit structures (¶ 0030) formed in a region (at ¶ 0030) of the silicon layer (102); and a seal ring structure (130, 410) surrounding the region (at ¶ 0030), wherein the seal ring structure (130, 410) comprises a first wall structure (410SD), the first wall structure (410SD) including a portion (through 102) which surrounds the region (at ¶ 0030), the portion (through 102) extending through the silicon layer (102) and extending outward therefrom to contact a pad structure (308, metal pillar 340), a first length (FIG. 3) of the first wall structure (410SD) along a side periphery of the first die (bottom) being longer than a pitch (between 106 vias) of contact structures (110), and the seal ring structure (130, 410) further comprises a second wall structure (410EB) that extends through the insulating layer (50A, 104, 150, 312) (See Fig. 2, Fig. 3, Fig. 4, ¶ 0023-¶ 0049, ¶ 0053-¶ 0056, ¶ 0065, ¶ 0077-¶ 0082) (Notes: the recited “pad structure” is interpreted as a contact structure without any particular shape and/or material). As to claim 2, Chang further discloses wherein the first wall structure (410SD) is formed by a metal material (See ¶ 0079). As to claim 3, Chang further discloses wherein the first wall structure (410SD) through the silicon layer (102) is configured to be a closed loop that encloses the region (at ¶ 0030) (See Fig. 3). As to claim 7, Chang further discloses the second wall structure (410EB) is formed by a metal material (See ¶ 0079). As to claim 8, Chang further discloses wherein the first circuit structures (¶ 0030) are formed on the first side of the first die (bottom), and the semiconductor device further comprises: a second die (200) that is bonded face-to-face with the first die (bottom), the second die (200) comprising: second circuit structures (¶ 0048) formed on a first side of the second die (200) (See Fig. 4, ¶ 0048). As to claim 21, Chang further discloses wherein the portion (through 102) of the first wall structure (410SD), which extends through the silicon layer (102) and surrounds the region (at ¶ 0030), forms a closed loop that encloses the region (at ¶ 0030) (See Fig. 3). As to claim 33, Chang further discloses wherein the pad structure (308, metal pillar 340) is arranged within the insulating layer (50A, 104, 150, 312) (See Fig. 2A, Fig. 4A) (Notes: within the boundary of the insulating layer). As to claim 34, Chang further discloses wherein the first wall structure (410SD) and the contact structures (110) are formed of a same metal material (See Fig. 4, ¶ 0033, ¶ 0056, ¶ 0079). As to claim 35, Chang further discloses wherein the portion (through 102) contacts the pad structure (308, metal pillar 340) to form a conductive connection therebetween (See Fig. 4, ¶ 0080). As to claim 36, Chang further discloses wherein the first die (bottom) further comprises a passivation layer (322) that is arranged on the insulating layer (50A, 104, 150, 312) at the first side (See Fig. 4, ¶ 0053) (Notes: the passivation layer covers and protects the first die).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4, 22-26, 29, and 32 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2022/0262695 A1 to Chang (“Chang”) as applied to claims 1 and 26 above, and further in view of U.S. Patent Application Publication No. 2019/0348376 A1 to Yang et al. (“Yang”). The teaching of Chang has been discussed above. As to claim 4, although Chang discloses wherein the first die (bottom) comprises the first wall structure (410SD) (See Fig. 4), Chang does not further disclose wherein the first die comprises multiple first wall structures that extend through the silicon layer, the multiple first wall structures form a first loop along the side periphery of the first die, the first loop encloses the region and includes gaps between adjacent first wall structures. However, Yang does disclose wherein the first die (with 110) comprises multiple first wall structures (120, 130a, 130b) that extend through the insulating layer (160), the multiple first wall structures (120, 130a, 130b) form a first loop along the side periphery of the first die (with 110), the first loop encloses the region (at 110) and includes gaps between adjacent first wall structures (120, 130a, 130b) (See Fig. 3, Fig. 6, ¶ 0002, ¶ 0018-¶ 0023, ¶ 0028). In view of the teaching of Yang, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Chang to have wherein the first die comprises multiple first wall structures that extend through the silicon layer, the multiple first wall structures form a first loop along the side periphery of the first die, the first loop encloses the region and includes gaps between adjacent first wall structures because the multiple first wall structures provide structural reinforcement and stop undesirable moisture and mobile ionic contaminants without forming noise-coupling paths (See ¶ 0018-¶ 0023, ¶ 0028). As to claim 22, although Chang discloses the first wall structure (410SD) (See Fig. 4), Chang does not further disclose wherein the first wall structure comprises an inner first wall structure which extends through the silicon layer and surrounds the region, and an outer first wall structure which extends through the silicon layer and surrounds the inner first wall structure. However, Chang in view of Yang does disclose wherein the first wall structure (410SD/120, 130a, 130b) comprises an inner first wall structure (410SD/130a) which extends through the silicon layer (102) and surrounds the region (at ¶ 0030/at 110), and an outer first wall structure (410SD/120, 130b) which extends through the silicon layer (102) and surrounds the inner first wall structure (410SD/130a) (See Chang Fig. 4 and Yang Fig. 3, Fig. 6, Fig. 7, ¶ 0002, ¶ 0018-¶ 0023, ¶ 0028). In view of the teaching of Yang, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Chang to have wherein the first wall structure comprises an inner first wall structure which extends through the silicon layer and surrounds the region, and an outer first wall structure which extends through the silicon layer and surrounds the inner first wall structure because the inner and outer first wall structures provide structural reinforcement and stop undesirable moisture and mobile ionic contaminants without forming noise-coupling paths (See ¶ 0018-¶ 0023, ¶ 0028). As to claim 23, Chang in view of Yang further discloses wherein outer first wall structure (410SD/120, 130b), which extends through the silicon layer (102) and surrounds the inner first wall structure (410SD/130a), forms a closed loop that encloses the inner first wall structure (410SD/130a) (See Chang Fig. 4 and Yang Fig. 6). As to claim 24, Chang in view of Yang further discloses wherein the inner first wall structure (410SD/130a) is formed by a metal material, and the outer first wall structure (410SD/130b, 120) is formed by a metal material (See Chang Fig. 4, ¶ 0079 and Yang Fig. 3, ¶ 0018). As to claim 25, Chang in view of Yang further discloses wherein a second length of the outer first wall structure (410SD/120, 130b) along the side periphery of the first die (bottom/with 110) is longer than the pitch (between 106 vias/between 124) of contact structures (110/122, 124) (See Yang Fig. 3, Fig. 6). As to claim 26, Chang further discloses wherein the first circuit structures (¶ 0030) are formed on the first side of the first die (bottom), and the semiconductor device further comprises: a second die (200) that is bonded face-to-face with the first die (bottom), the second die (200) comprising: second circuit structures (¶ 0048) formed on a first side of the second die (200) (See Fig. 4, ¶ 0048). As to claim 29, Chang in view of Yang further discloses the inner first wall structure (410SD/130a), which extends through the silicon layer (102) and surrounds the region (at ¶ 0030/at 110), forms a closed loop that encloses the region (at ¶ 0030/at 110) (See Yang Fig. 7). As to claim 32, Chang in view of Yang further discloses wherein the inner first wall structure (410SD/130a) has a plurality of first gaps (Ga) arranged along a periphery of the inner first wall structure (410SD/130a), the outer first wall structure (410SD/130b) has a plurality of second gaps (Gb) arranged along a periphery of the outer first wall structure (410SD/130b), and the plurality of first gaps (Ga) and the plurality of second gaps (Gb) are staggered relative to each other (See Yang Fig. 6).
Claim(s) 9 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2022/0262695 A1 to Chang (“Chang”) and U.S. Patent Application Publication No. 2019/0348376 A1 to Yang et al. (“Yang”) as applied to claims 8 and 26 above, and further in view of U.S. Patent Application Publication No. 2017/0256504 A1 to Minami et al. (“Minami”). The teachings of Chang and Yang have been discussed above. As to clams 9 and 27, although Chang discloses wherein the first circuit structures (¶ 0030) include a memory, for example, and the second circuit structures (¶ 0048) include an application-specific integrated circuit (ASIC) chip, for example (See Fig. 4, ¶ 0030, ¶ 0048), Chang and Yang do not further disclose wherein the first circuit structures include an NAND memory array, and the second circuit structures include periphery circuitry for the NAND memory array. However, Minami does disclose wherein the first circuit structures (1) include an NAND memory array (6), and the second circuit structures (1) include periphery circuitry (7) for the NAND memory array (6) (See Fig. 1, ¶ 0021). In view of the teaching of Minami, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Chang to have wherein the first circuit structures include an NAND memory array, and the second circuit structures include periphery circuitry for the NAND memory array because the integrated NAND memory array along with its control periphery circuitry provide high memory density and proper corresponding commands (See ¶ 0021).
Response to Arguments
Applicant's arguments with respect to claim 1 have been considered but are moot
in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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/DAVID CHEN/Primary Examiner, Art Unit 2815
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