DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 07/01/2026 have been fully considered but they are not persuasive.
Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
The examiner respectfully reiterates that the application is directed to the use of a thin tantalum disulfide liner in a conventional dual damascene copper BEOL semiconductor manufacturing process. Harper et al. teaches the conventional process, while Chen provides motivation for modifying the Ta barrier of Harper to include the ultra-thin tantalum disulfide layer. The modification of the Ta layer to TaS2 can be completed either before or after the directional etch and the result will be identical. The liner material only exists on the sidewalls of opening, with an etch stop material on the bottoms of the openings where there is no conductor. Harper then fills the via and trench with continuous copper interconnects. The examiner respectfully reiterates that he does not identify any patentable subject matter in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4 – 6, and 8 – 22 are rejected under 35 U.S.C. 103 as being unpatentable over Harper et al. (US 6,300,236) in view of Chen et al. (US 2020/0395311).
Regarding claim 1, Harper teaches (FIG 2A-2E):
A method of making a semiconductor component, the method comprising:
forming a lower level of the semiconductor component, wherein the lower level includes a first dielectric layer (11c), and a lower level line trench formed in the first dielectric layer;
lining the lower level line trench with a first barrier layer (15);
filling the lower level line trench with a first interconnect material (12) in order to form a lower level line of an interconnect structure;
forming an upper level of the semiconductor component by depositing a capping layer (16) on the first dielectric layer, the second barrier layer, and the lower level line, depositing a second dielectric layer (11b) on top of the capping layer, depositing an etch stop layer (28) on top of the second dielectric layer, and depositing a third dielectric layer (11a) on top of the etch stop layer;
forming a cavity in the upper level including an upper level line trench and an upper level via trench, wherein the upper level line trench extends through the third dielectric layer and from an uppermost surface of the upper level to the etch stop layer, and the upper level via trench is continuous with the upper level line trench and extends down to the first interconnect material of the lower level line (FIG. 2A);
forming a third barrier layer (15) made of tantalum on all surfaces exposed by the forming the cavity;
anisotropically etching the third barrier layer to remove the third barrier layer from substantially horizontal surfaces of the semiconductor component (FIG. 2B, directional etch) such that the third barrier layer is removed from a bottom of the upper level via trench exposing the first interconnect material and from a bottom of the upper level line trench exposing the etch stop layer, which retains the third barrier layer only on non-horizontal sidewall surfaces; and
filling the cavity with a second interconnect material comprising copper (14, 12a, copper taught throughout as preferred material) to form an upper level line of the interconnect structure and an upper level via of the interconnect structure, wherein the second interconnect material is in direct contact with the lower level line at the bottom of the upper level via trench without any intervening barrier layer (FIG. 2E),
wherein a bottom of the upper level line comprises a material that is compositionally different from tantalum disulfide (28), the interconnect structure forms a single, continuous interconnect (FIG. 2E), is adapted to provide an electrical connection between a power delivery network on a back side of the semiconductor component and at least one device on a front side of the semiconductor component (wiring layers inherently provide electrical connection between BEOL power delivery networks and transistor source/drain areas to enable transistor operation), the fourth barrier layer is disposed only on the sidewalls of the upper level via and the upper level line, a bottom of the upper level via is substantially free of the fourth barrier layer, and a bottom of the upper level line includes the etch stop layer that is compositionally different from the fourth barrier layer.
Harper fails to expressly disclose converting the tantalum barrier layers to two-dimensional tantalum disulfide layers wherein sidewalls of the upper level via are lined with two-dimensional tantalum disulfide.
However, Chen teaches the formation of extremely thin copper diffusion barrier layers in interconnect structures formed of 2D tantalum disulfide having a thickness as small as 0.7 nm ([0038] – [0039]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the liner of Harper by converting the Ta layer to a TaS2 layer for the predictable advantage of reducing liner thickness (Chen [0007], [0030] – [0038]). Performing the same conversion process to multiple liners is obvious since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
It has been held that the recitation that an element is "adapted to" perform a function is not a positive limitation but only requires the ability to so perform. It does not constitute a limitation in any patentable sense. In re Hutchison, 69 USPQ 138.
Regarding claim 4, Harper teaches (FIG. 2B):
The method of claim 1, wherein forming the cavity includes the upper level via trench exposing a portion of lower level line such that a top surface of the lower level line is free of any barrier material prior to filling, and the upper level line trench exposing a portion of the etch stop layer.
Regarding claim 5, Harper teaches (FIG. 2B):
The method of claim 1, further comprising:
Removing the etch stop layer that is arranged outside of the upper level line after filling the cavity.
Regarding claim 6, Chen in view of Harper teaches:
The method of claim 1, wherein the second barrier layer is made of a different material than the third barrier layer (conversion of the first Ta barrier layer must occur prior to deposition of the third barrier material), and wherein the etch stop layer at the bottom of the upper level line trench is different from the fourth barrier layer (28).
Regarding claim 8, Harper teaches (FIG. 2E):
A semiconductor component, comprising:
an interconnect structure including:
a lower level line (12) separated from surrounding dielectric material by a sidewall made of a first liner material (15);
a via (14) arranged in direct contact with the lower level line and separated from surrounding dielectric material by a sidewall made of a second liner material (15); and
an upper level line (12a) arranged in direct contact with the via and separated from surrounding dielectric material by a sidewall made of the second liner material (15) and by a bottom wall made of a third liner material that comprises a material that is compositionally different from tantalum disulfide (28),
wherein the second liner material is present only on non-horizontal sidewall surfaces of the via and the upper level line, a bottom interface between the via and the lower level line is free of the second liner material such that the via is in direct copper-to-copper contact with the lower level line, the lower level line, the via, and the upper level line are filled with a single interconnect material comprising copper (copper is taught throughout as the preferred material) that is continuous and that extends from a bottom of the lower level line to an uppermost surface of the interconnect structure (FIG. 2E), and the interconnect structure is adapted to provide an electrical connection between a power delivery network on a back side of the semiconductor component and at least one device on a front side of the semiconductor component (wiring layers inherently provide electrical connection between BEOL power delivery networks and transistor source/drain areas to enable transistor operation).
Harper fails to expressly disclose two-dimensional tantalum disulfide liners having a thickness of 0.7-1.5 nanometers.
However, Chen teaches the formation of extremely thin copper diffusion barrier layers in interconnect structures formed of 2D tantalum disulfide having a thickness as small as 0.7 nm ([0038] – [0039]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the liner of Harper by converting the Ta layer to a TaS2 layer for the predictable advantage of reducing liner thickness (Chen [0007], [0030] – [0038]). Performing the same conversion process to multiple liners is obvious since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 9, Harper teaches:
The semiconductor component of claim 8, wherein the second liner material is different from the third liner material (Ta/”etch stop”) and the third liner material is positioned only at a bottom surface of the upper level line and not at the bottom of the via.
Regarding claim 10, Harper teaches:
The semiconductor component of claim 8, wherein the first liner material is the same as the second liner material (15).
Regarding claim 11, Harper teaches:
The semiconductor component of claim 8, wherein the surrounding dielectric material surrounding the lower level line is separated from the surrounding dielectric material surrounding the via by a capping layer (16).
Regarding claim 12, Harper teaches:
The semiconductor component of claim 8, wherein the via is integrally formed with the lower level line (FIG. 2E).
Regarding claim 13, Harper teaches:
The semiconductor component of claim 8, wherein the bottom wall is substantially horizontal, and the non-horizontal sidewall surfaces are not substantially horizontal (FIG. 2E).
Regarding claim 14, Harper teaches:
The semiconductor component of claim 8, wherein the bottom wall is in direct contact with the sidewall that separates the via from the surrounding dielectric material, and the bottom wall is in direct contact with the sidewall that separates the upper level line from the surrounding dielectric material (FIG. 2E).
Regarding claim 15, Harper teaches:
The semiconductor component of claim 8, wherein the lower level line is made of an interconnect material, the via is made of the interconnect material, and the interconnect material of the lower level line and of the via are continuous with one another (FIG. 2E).
Regarding claim 16, Harper teaches (FIG. 2E):
A semiconductor component, comprising:
a continuous interconnect structure made of a single piece of interconnect material comprising copper (copper is taught throughout as the preferred material) extending from a bottom surface of the continuous interconnect structure to a top surface of the continuous interconnect structure, the continuous interconnect structure including:
a lower level line (12) separated from surrounding dielectric material (11c) by a sidewall made of a first liner material (15);
an upper level line (12a) including a sidewall (15) that separates the upper level line from surrounding dielectric material (11a), a bottom of the upper level line comprises a material that is compositionally different from tantalum disulfide (28); and
a via (14) extending from the lower level line to the upper level line, the via arranged in direct contact with the lower level line, separated from surrounding dielectric material (11b) by a sidewall made of a second liner material (15), and arranged in direct contact with the upper level line (FIG. 2E), wherein the continuous interconnect structure is adapted to provide an electrical connection between a power delivery network on a back side of the semiconductor component and at least one device on a front side of the semiconductor component (wiring layers inherently provide electrical connection between BEOL power delivery networks and transistor source/drain areas to enable transistor operation),
wherein the two-dimensional tantalum disulfide is disposed only on non-horizontal surfaces of the continuous interconnect structure, and a bottom interface between the via and the lower level line is devoid of any barrier layer such that the continuous interconnect structure includes direct sopper-to-copper contact at the bottom interface
Harper fails to expressly disclose two-dimensional tantalum disulfide liners having a thickness of 0.7-1.5 nanometers.
However, Chen teaches the formation of extremely thin copper diffusion barrier layers in interconnect structures formed of 2D tantalum disulfide having a thickness as small as 0.7 nm ([0038] – [0039]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the liner of Harper by converting the Ta layer to a TaS2 layer for the predictable advantage of reducing liner thickness (Chen [0007], [0030] – [0038]). Performing the same conversion process to multiple liners is obvious since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 17, Harper teaches:
The semiconductor component of claim 16, wherein the lower level line is partially delimited by the bottom surface of the continuous interconnect structure (FIG. 2E).
Regarding claim 18, Harper teaches:
The semiconductor component of claim 16, wherein the upper level line is partially delimited by the top surface of the continuous interconnect structure (FIG. 2E).
Regarding claim 19, Harper teaches:
The semiconductor component of claim 18, wherein the upper level line is partially delimited by a bottom wall made of a first barrier material (FIG. 2E).
Regarding claim 20, Harper teaches:
The semiconductor component of claim 19, wherein the via is partially delimited by a sidewall made of a second barrier material, and the second barrier material is different than the first barrier material (FIG. 2E).
Regarding claim 21, Harper teaches:
The method of claim 1, wherein the interconnect structure is a single, continuous structure made of copper (FIG. 2E) extending uninterrupted through the upper level via and the lower level line.
Regarding claim 22, Harper teaches:
The method of claim 1, wherein the lower level line is in direct contact with the second barrier layer (FIG. 2E).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Madonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 2898
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