Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
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For example, the first and second positive terminal 1624 and 1524, capacitor 1625, and negative terminal are not disclosed in the original drawing of FIG. 16C as shown above.
Appropriate action is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 21, 24-25 and 26-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakaiso (Pub. No.: US 2017/0338038) in view of SHIH (Pub. No.: US 2022/0085145).
Re claim 1, Nakaiso teaches a capacitance device, comprising:
a semiconductor substrate (10+30, FIG. 2);
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a capacitor ([C], FIGS. 2/6, ¶ [0051]) having at least a portion thereof disposed within insulating material (30) of the semiconductor substrate (10+30), the capacitor including first and second positive terminals (61A-E, FIG. 1-2, ¶ [0044]) and first and second negative terminals (62A-D);
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a passivation layer (L1-L9, FIGS. 6 & 9, [as shown above], ¶ [0098]) formed over the capacitor, the first and second positive terminals (51A/61A & 61B/51B) and the first and second negative terminals (62C/52 & 62A/52), the passivation layer defining a first opening (occupied by 61A) over the first positive terminal (51A/61A), a second opening (occupied by 61B) over the second positive terminal (61B/51B), a third opening (occupied by 62C) over the first negative terminal (62C/52) and a fourth opening (occupied by 62A) over the second negative terminal (62A/52), wherein the passivation layer (90) has a first surface (top) opposite a second surface (bottom) defining a thickness therebetween and wherein each of the first, second, third, and fourth openings (occupied by 61A/61B/62C/62A) extend through the thickness;
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a first electrical connection ([81A+81B+42B+62+52] or [8a+42+82+52] as shown in FIG. 8B], FIGS. 4/5/6, note that 81A/81B are connected to positive terminals 62/52 as shown in FIG. 6, note that 81A/81B formed on L5 and 62/52 formed on L9 or [8a+42+82+52 as shown in FIG. 8B]) having a first portion (top portion) and directly disposed on the first surface (top) of passivation layer (L1-L9 or [P] in different embodiment [as shown in FIG. 8BB]) and including first extending portions that extend through each of the first and second openings (note that “openings that will serve as contact holes are formed in the SiO2 film by performing inductive coupling plasma reactive ion etching (ICP-RIE)”, ¶ [0062]), the first electrical connection [81A+81B+62+52] electrically coupling the first positive terminal to the second positive terminal; and
a second electrical connection ([71A+71B++41+61+51], FIGS. 4/5/6, note that 71A/71B are connected to negative terminals 61/51 as shown in FIG. 633 and note that 71A/71B are belong to L5 and 61/51 are belong to L9 of FIG. 5) having a second portion disposed directly on the first surface (top) of the passivation layer (L1-L9) and including second extending portions that extend through each of the third and fourth openings (note that “openings that will serve as contact holes are formed in the SiO2 film by performing inductive coupling plasma reactive ion etching (ICP-RIE)”, ¶ [0062]), the second electrical connection [71A+71B+61+51] electrically coupling the first negative terminal to the second negative terminal.
Nakaiso fails to teach a capacitor having at least a portion thereof disposed within semiconductor material of the semiconductor substrate.
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SHIH teaches a capacitor ([C], FIG. 1 [as shown above]) having at least a portion thereof disposed within semiconductor material of the semiconductor substrate (110, ¶ [0015]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of reducing cost of manufacturing as taught by Nakaiso, [0003].
Re claim 2, Nakaiso teaches the capacitance device of claim 1 wherein the first and the second positive terminals (51A/61A & 61B/51B) and the first and the second negative terminals (62C/52 & 62A/52) each comprise parallel metallic traces (71/72/81/82, Fig. 9), extending across a surface of the semiconductor substrate.
Re claim 3, Nakaiso teaches the capacitance device of claim 1 wherein the first [81A+81B+62+52] and second [71A+71B+61+51] electrical connection are conductive pillars configured to be electrically and mechanically coupled to the semiconductor substrate (10).
Nakaiso differs from the invention by not showing copper material.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to include the above said teaching because copper is a very well-known material for making a contact since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416.
Re claim 4, Nakaiso, FIGS. 1-2 teaches the capacitance device of claim 1, wherein the capacitor further comprises third and fourth positive terminals (51C/61C & 61D/51D) and third and fourth negative terminals (62D/52 & 62B/52).
Re claim 5, Nakaiso, FIG. 1 and FIG. 2 teaches the capacitance device of claim 4, wherein the passivation layer (90) defines a fifth opening (occupied by 61C) over the third positive terminal (51C/61C), a sixth opening (occupied by 61D) over the fourth positive terminal (61D/51D), a seventh opening (occupied by 62D) over the third negative terminal (62D/52) and an eighth opening (occupied by 62B) over the fourth negative terminal (62B/52).
Re claim 6, Nakaiso teaches he capacitance device of claim 5, further comprising a third electrical connection disposed on the passivation layer and including third extending portions that extend through each of the fifth and sixth openings (occupied by 61C/61D), electrically coupling the third positive terminal to the fourth positive terminal (61C/51C & 61D/51D); and
a fourth electrical connection disposed on the passivation layer and including fourth extending portions that extend through each of the seventh and eighth openings (occupied by 62D/62B), electrically coupling the third negative terminal to the fourth negative terminal (62D/52 & 62B/52).
Re claim 7, Nakaiso teaches the capacitance device of claim 6 wherein the first (61A/51A & 61B/51B) and third (61C/51B & 61D/51D) electrical connection are arranged in a first column and the second (62C/52 & 62A/52) and fourth (62D/52 & 62B/52) electrical connection are arranged in a second column.
Re claim 21, Nakaiso teaches the capacitance device of claim 1, wherein the capacitor is a first capacitor (connected to [F&ST], FIG. 4 [as shown above]), and the capacitance device further comprises a second capacitor disposed on the semiconductor substrate, the second capacitor comprising third and fourth positive ([T&FT], note that in manufacturing they are not made just one capacitor) terminals and third and fourth negative terminals [T&FNT].
Re claim 24, Nakaiso, FIGS. 4/6 and 9 teaches the capacitance device of claim 21, wherein the first, the second, the third, and the fourth positive terminals ([F&ST] & [T&FT]) and the first, the second, the third, and the fourth negative terminals ([F&SNT] & [T& FNT]) each comprise parallel metallic traces extending across a surface of the semiconductor substrate.
Re claim 25, Nakaiso, FIGS. 4/6 and 9 teaches the capacitance device of claim 21, the passivation layer further defining a fifth opening (located in layer 22B of FIGS. 4 and 6) over the third positive terminal (located in layer 21A), a sixth opening (located in layer 22B) over the fourth positive terminal (located in layer 21A), a seventh opening (located in layer 21B) over the third negative terminal (located in layer 22B), and an eighth opening (located in layer 21B) over the fourth negative terminal (located in layer 22B).
Re claim 26, Nakaiso teaches he capacitance device of claim 25, further comprising a third electrical connection ((51A/61A/72//41/71A/71B) & (61B/51B/72//41/71A/71B)) disposed on the passivation layer and including third extending portions that extend through each of the fifth and sixth openings (occupied by 61C/61D), electrically coupling the third positive terminal to the fourth positive terminal (61C/51C & 61D/51D); and
a fourth electrical connection ((62C/52/82//42B/81A/81B) & (62A/52/82/42B/81A/81B)) disposed on the passivation layer and including fourth extending portions that extend through each of the seventh and eighth openings (occupied by 62D/62B), electrically coupling the third negative terminal to the fourth negative terminal (62D/52 & 62B/52).
Re claim 27, Nakaiso, FIGS. 4/6 and 9 teaches the capacitance device of claim 26 wherein the third and fourth electrical connections are copper pillars (71A/71B & 81A/81B) configured to be electrically and mechanically coupled to the semiconductor substrate.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakaiso/SHIH in view of YU et al. (Pub. No.: US 2014/0225222) (hereinafter Yu).
Nakaiso/SHIH teaches all the limitation of claim 21.
Nakaiso/SHIH fails to teach wherein the first capacitor has a first capacitance and the second capacitor has a second capacitance, and wherein the first capacitance is equal to the second capacitance.
Yu teaches wherein the first capacitor has a first capacitance and the second capacitor has a second capacitance, and wherein the first capacitance is equal to the second capacitance (MIM capacitors 200, Fig. 3, [0013]).
It would have been for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of providing depletion-free, high-conductance electrodes suitable for high-speed applications at low cost as taught by Yu, [0002].
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakaiso/SHIH in view of Randall (Pub. No.: US 2012/0081870).
Nakaiso/SHIH teaches all the limitation of claim 21.
Nakaiso/SHIH fails to teach the limitation of claim 22.
Randall teaches the capacitance device of claim 21, wherein the first capacitor has a first capacitance and the second capacitor has a second capacitance, and wherein the first capacitance (210) is different than the second capacitance (219, Fig. 1, [0032]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of minimizing the device foot print as taught by Randall, [0002].
Claim(s) 1-7, 21, 24-25 and 26-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over XIAO (Pub. No.: US 2012/0279771) filed in the IDS on 02/18/2025 in view of Nakaiso and further in view of SHIH.
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Re claim 1, XIAO, FIG. 1 [as shown above] teaches a capacitance device, comprising:
a semiconductor substrate (10);
a capacitor (20, ¶¶ [0014]/[0004]) disposed on the semiconductor substrate, the capacitor including first and second positive terminals (said left 32) and first and second negative terminals (said right 32);
a passivation layer (40+30) formed over the capacitor, the first and second unknown terminals [F&SUPT] and the first and second unknown terminals [F&SUNT], the passivation layer (40) defining a first opening (holes 45/[FO], [0017]) over the first unknown terminal, a second opening [SO] over the second unknown terminal, a third opening [TO] over the first unknown terminal and a fourth opening [FO] over the second unknown terminal, wherein the passivation layer (40) has a first surface (bottom) opposite a second surface (top) defining a thickness therebetween and wherein each of the first, second, third, and fourth openings extend through the thickness;
a first electrical connection having a first portion ([452+42+44] of [F&SUPT], note that it was mislabel in paragraph [0017] as 425) disposed directly on the first surface (left) of the passivation layer (40+30) and including first extending portions that extend through each of the first and second openings, the first electrical connection electrically coupling the first positive terminal to the second unknown terminal [F&SUPT]; and
a second electrical connection having a second portion ([452+42+44] of [F&SUNT]) disposed on the first surface of the passivation layer and including second extending portions that extend through each of the third and fourth openings, electrically coupling the first negative terminal to the second unknown terminal [F&SUNT].
XIAO fails to teach the capacitors with positive and negative terminals.
Nakaiso teaches the capacitors with positive and negative terminals [(51A/61A & 61B/51B) and (62C/52 & 62A/52)].
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of eliminating noise as taught by Nakaiso, [0004].
Moreover, XIAO/Nakaiso fails to teach a capacitor having at least a portion thereof disposed within semiconductor material of the semiconductor substrate.
SHIH teaches a capacitor ([C], FIG. 1 [as shown above]) having at least a portion thereof disposed within semiconductor material of the semiconductor substrate (110, ¶ [0015]).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of reducing cost of manufacturing as taught by Nakaiso, [0003].
Re claim 2, in the combination, XIAO, FIG. 1 teaches the capacitance device of claim 1 wherein the first and the second positive terminals [F&SUPT] and the first and the second negative terminals [F&SUNT] each comprise parallel metallic traces (42/44) extending across a surface of the semiconductor substrate.
Re claim 3, in the combination, XIAO, FIG. 1 teaches the capacitance device of claim 1 wherein the first and second electrical connections are copper pillars (452) configured to be electrically and mechanically coupled to the semiconductor substrate.
Re claim 4, in the combination, Nakaiso, FIGS. 1-2 teaches the capacitance device of claim 1, wherein the capacitor further comprises third and fourth positive terminals (51C/61C & 61D/51D) and third and fourth negative terminals (62D/52 & 62B/52).
Re claim 5, in the combination, Nakaiso, FIG. 1 and FIG. 2 teaches the capacitance device of claim 4, wherein the passivation layer (90) defines a fifth opening (occupied by 61C) over the third positive terminal (51C/61C), a sixth opening (occupied by 61D) over the fourth positive terminal (61D/51D), a seventh opening (occupied by 62D) over the third negative terminal (62D/52) and an eighth opening (occupied by 62B) over the fourth negative terminal (62B/52).
Re claim 6, in the combination, Nakaiso teaches he capacitance device of claim 5, further comprising a third electrical connection disposed on the passivation layer and including third extending portions that extend through each of the fifth and sixth openings (occupied by 61C/61D), electrically coupling the third positive terminal to the fourth positive terminal (61C/51C & 61D/51D); and
a fourth electrical connection disposed on the passivation layer and including fourth extending portions that extend through each of the seventh and eighth openings (occupied by 62D/62B), electrically coupling the third negative terminal to the fourth negative terminal (62D/52 & 62B/52).
Re claim 7, in the combination, Nakaiso teaches the capacitance device of claim 6 wherein the first (61A/51A & 61B/51B) and third (61C/51B & 61D/51D) electrical connection are arranged in a first column and the second (62C/52 & 62A/52) and fourth (62D/52 & 62B/52) electrical connection are arranged in a second column.
Re claim 21, in the combination, Nakaiso teaches the capacitance device of claim 1, wherein the capacitor is a first capacitor (connected to [F&ST], FIG. 4 [as shown above]), and the capacitance device further comprises a second capacitor disposed on the semiconductor substrate, the second capacitor comprising third and fourth positive ([T&FT], note that in manufacturing they are not made just one capacitor) terminals and third and fourth negative terminals [T&FNT].
Re claim 24, in the combination, Nakaiso, FIGS. 4/6 and 9 teaches the capacitance device of claim 21, wherein the first, the second, the third, and the fourth positive terminals ([F&ST] & [T&FT]) and the first, the second, the third, and the fourth negative terminals ([F&SNT] & [T& FNT]) each comprise parallel metallic traces extending across a surface of the semiconductor substrate.
Re claim 25, in the combination, Nakaiso, FIGS. 4/6 and 9 teaches the capacitance device of claim 21, the passivation layer further defining a fifth opening (located in layer 22B of FIGS. 4 and 6) over the third positive terminal (located in layer 21A), a sixth opening (located in layer 22B) over the fourth positive terminal (located in layer 21A), a seventh opening (located in layer 21B) over the third negative terminal (located in layer 22B), and an eighth opening (located in layer 21B) over the fourth negative terminal (located in layer 22B).
Re claim 26, in the combination, Nakaiso teaches he capacitance device of claim 25, further comprising a third electrical connection ((51A/61A/72//41/71A/71B) & (61B/51B/72//41/71A/71B)) disposed on the passivation layer and including third extending portions that extend through each of the fifth and sixth openings (occupied by 61C/61D), electrically coupling the third positive terminal to the fourth positive terminal (61C/51C & 61D/51D); and
a fourth electrical connection ((62C/52/82//42B/81A/81B) & (62A/52/82/42B/81A/81B)) disposed on the passivation layer and including fourth extending portions that extend through each of the seventh and eighth openings (occupied by 62D/62B), electrically coupling the third negative terminal to the fourth negative terminal (62D/52 & 62B/52).
Re claim 27, in the combination, Nakaiso, FIGS. 4/6 and 9 teaches the capacitance device of claim 26 wherein the third and fourth electrical connections are copper pillars (71A/71B & 81A/81B) configured to be electrically and mechanically coupled to the semiconductor substrate.
Response to Arguments
Applicant's arguments filed 04/20/2026 have been fully considered but they are moot in view of new ground of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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