DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/21/2025 has been entered.
Response to Arguments
Applicant's arguments filed 10/8/2025 have been fully considered but they are moot in view of the new grounds of rejection. As described in the interview summary, Chen et al. (US PGPub 2020/0135562) disclosed a bypass interconnect in fig. 14 which is being incorporated into the current rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10, 11, 21, 22, 24, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (US PGPub 2013/0001796; hereinafter “Song”) in view of Kawamura (US PGPub 2013/0082393) and Chen et al. (US PGPub 2020/0135562; hereinafter “Chen”).
Re claim 10: Song teaches (e.g. fig. 2B) a semiconductor component, comprising: a dielectric layer (insulating film 40; e.g. paragraph 65) having an uppermost surface (CVP); a further dielectric layer (insulating film 100; e.g. paragraph 133) arranged above the uppermost surface (CVP) of the dielectric layer (40); an interconnect (plugs 84, 88; e.g. paragraph 56) formed in the dielectric layer (40), wherein the interconnect (84, 88) is comprised of a plurality of interconnect elements (84, 88), wherein each of the plurality of interconnect elements (84, 88) have a first tapered sidewall (sidewall of 84, 88 are tapered; hereinafter “1TS”) and an uppermost surface (upper most surface of 84, 88; hereinafter “US84”) that is arranged higher than the uppermost surface (CVP) of the dielectric layer (40); a further interconnect (wiring 153; e.g. paragraph 54) that includes a plurality of further interconnect elements (153, 159), the further interconnect (153, 159) formed in the further dielectric layer (100) such that the one of plurality of further interconnect elements (153, 159) is in direct contact with one of the plurality of the interconnect elements(84, 88); and a spacer (184, 188) comprising an uppermost surface (uppermost surface of portion of 184, 188 which abuts both 84, 88; hereinafter “US184”) that is arranged higher than the uppermost surface (US84) of the interconnect (84, 88), a bottom surface (bottom most surface of 84, 88 which abuts 40; hereinafter “BS84”) in direct contact with the uppermost surface (CVP) of the dielectric layer (40), a first internal side surface (inner surface of 184 which abuts sidewall of 84, 88; hereinafter “1ISS”) in direct contact with the first tapered sidewall (1TS) of the interconnect (84, 88).
Song is silent as to explicitly teaching wherein each of the further interconnect elements have a second tapered sidewall; and a second internal side surface in direct contact with the second tapered sidewall of the further interconnect; and a metal line connecting two of the plurality of further interconnect elements, wherein the metal line extends over a bypassed interconnect element, wherein the bypassed interconnect element is located between two of the plurality of interconnect elements that are connected to two of the plurality of further interconnect elements.
Kawamura teaches (e.g. fig. 25) wherein each of the further interconnect elements have (wiring W1; e.g. paragraph 126) having a second tapered sidewall (sidewall of W1 is tapered; hereinafter “2TS”); and a second internal side surface (inner surface of IL1 of Kawamura/184 of Song, which abuts sidewall of W1; hereinafter “2ISS”) in direct contact with the second tapered sidewall (2TS) of the further interconnect (W1).
Chen teaches (e.g. fig. 14) a metal line (129) connecting two of the plurality of further interconnect elements (129V of Chen/153,159 of Song), wherein the metal line (129) extends over a bypassed interconnect element (middle 115), wherein the bypassed interconnect element (middle 115) is located between two of the plurality of interconnect elements (left 115, right 115 of Chen/84, 88 of Song) that are connected to two of the plurality of further interconnect elements (129V of Chen/153, 159 of Song).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the tapered further interconnect which contacts the inner sidewall of the spacer as taught by Kawamura and the metal line which bypasses an interconnect as taught by Chen in the device of Song in order to have the predictable result of using a further interconnect structure which would not restrict current capacity by narrowing of the interconnect and therefore improve device performance and in order to have the predictable result of using the structure of Song in an application which requires bypassing an interconnect due to a desired design choice, respectively.
Re claim 11: Song in view of Kawamura and Chen teaches the semiconductor component of claim 10, wherein: the first tapered sidewall (1TS of Song) extends above the uppermost surface (CVP) of the dielectric layer (40).
Re claim 21: Song teaches (e.g. fig. 2B) a semiconductor component, comprising: a lower level dielectric (insulating film 40; e.g. paragraph 65) having an uppermost surface (CVP); a upper level dielectric (insulating film 100; e.g. paragraph 133) arranged above the uppermost surface (CVP) of the lower level dielectric (40); a lower interconnect (plugs 84, 88; e.g. paragraph 56) formed in the lower level dielectric (40), wherein the lower interconnect (84, 88) is comprised of a plurality of lower interconnect elements (84, 88), wherein each of the plurality of interconnect elements (84, 88) have a first tapered sidewall (sidewall of 84, 88 is tapered; hereinafter “1TS”) and an uppermost surface (upper most surface of 84, 88; hereinafter “US84”) that is arranged higher than the uppermost surface (CVP) of the lower level dielectric (40); an upper interconnect (153, 159) that includes a plurality of further upper interconnect elements (153, 159), the upper interconnect (153, 159) formed in the upper level dielectric (100) such that the one of plurality upper interconnect elements (153, 159) is in direct contact with one of the plurality of the lower interconnect elements (84, 88); and a spacer (184, 188) comprising an uppermost surface (uppermost surface of portion of 184, 188; hereinafter “US184”) that is arranged higher than the uppermost surface (US84) of the lower interconnect (40), a bottom surface (bottom most surface of 184, 188 which abuts 40; hereinafter “BS184”) in direct contact with the uppermost surface (CVP) of the lower level dielectric (40), a first internal side surface (inner surface of 184, 188 which abuts sidewall of 84, 88; hereinafter “1ISS”) in direct contact with the first tapered sidewall (1TS) of the lower interconnect (84, 88).
Song is silent as to explicitly teaching each of the plurality of lower interconnect elements have a second tapered sidewall; and a metal line connecting two of the plurality of further interconnect elements, wherein the metal line extends over a bypassed interconnect element, wherein the bypassed interconnect element is located between two of the plurality of interconnect elements that are connected to two of the plurality of further interconnect elements; the spacer having a second internal side surface in direct contact with the second tapered sidewall of the upper interconnect.
Kawamura teaches (e.g. fig. 25) each of the plurality of lower interconnect elements (wiring W1; e.g. paragraph 126) have a second tapered sidewall (sidewall of W1 is tapered; hereinafter “2TS”); the spacer (184, 188 of Song) having a second internal side surface (inner surface of 184, 188 of Song would abuts sidewall of W1; hereinafter “2ISS”) in direct contact with the second tapered sidewall (2TS) of the upper interconnect (W1).
Chen teaches (e.g. fig. 14) a metal line (129) connecting two of the plurality of further interconnect elements (129V of Chen/153,159 of Song), wherein the metal line (129) extends over a bypassed interconnect element (middle 115), wherein the bypassed interconnect element (middle 115) is located between two of the plurality of interconnect elements (left 115, right 115 of Chen/84, 88 of Song) that are connected to two of the plurality of further interconnect elements (129V of Chen/153, 159 of Song).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the tapered further interconnect which contacts the inner sidewall of the spacer as taught by Kawamura and the metal line which bypasses an interconnect as taught by Chen in the device of Song in order to have the predictable result of using a further interconnect structure which would not restrict current capacity by narrowing of the interconnect and therefore improve device performance and in order to have the predictable result of using the structure of Song in an application which requires bypassing an interconnect due to a desired design choice, respectively.
Re claim 22: Song in view of Kawamura and Chen teaches the semiconductor component of claim 21, wherein: the first tapered sidewall (1TS of Song) of the lower interconnect (84, 88 of Song) extend partially above the uppermost surface (CVP of Song) of the lower level dielectric (40).
Re claim 24: Song in view of Kawamura and Chen teaches the semiconductor component of claim 21, wherein: the upper interconnect (153, 159 of Song) is in direct contact with the lower interconnect (84, 88 of Song) at an interface (interface between 153,159 and 84,88; hereinafter “IF”), and the interface (IF) is arranged higher than the uppermost surface (CVP) of the lower level dielectric (40) and lower than the uppermost surface (US184) of the spacers (184,188).
Re claim 25: Song in view of Kawamura and Chen teaches the semiconductor component of claim 21, wherein: the upper interconnect (W1 of Kawamura) is in direct contact the spacer (184, 188 of Song).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Kawamura and Chen as applied to claims 10, above, and further in view of Chan et al. (US PGPub 2018/0342459; hereinafter “Chan”).
Re claim 12: Song teaches the semiconductor component of claim 10, wherein: the interconnect (84, 88) includes: a barrier (barrier conductor film 65; e.g. paragraph 58) arranged in direct contact with the dielectric layer (40).
Song in view of Kawamura and Chen is silent as to a liner arranged in direct contact with the barrier, and an interconnect body arranged in direct contact with the liner.
Chan teaches (e.g. fig. 12) a liner (liner 270; e.g. paragraph 30) arranged in direct contact with the barrier (barrier layer 250, 260; e.g. paragraphs 24 and 25), and an interconnect body (conductive layer 280; e.g. paragraph 31) arranged in direct contact with the liner (270).
It would have been obvious to one of ordinary skill in the art at the time of effective filling, absent unexpected results, to use the liner layer between the barrier and metal fill as taught by Chan in the device of Song in view of Kawamura and Chen in order to have the predictable result of improving adhesion between barrier and metal fill layers.
Claim(s) 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Kawamura and Chen, as applied to claim 10 above, and further in view of Noguchi et al. (US PGPub 2003/0183940; hereinafter “Noguchi”).
Re claim 13: Song in view of Kawamura and Chen teaches substantially the entire structure as recited in claim 10 except explicitly teaching the semiconductor component further comprising: an etch stop layer between and in direct contact with the dielectric layer and the further dielectric layer.
Noguchi teaches (e.g. fig. 26) an etch stop layer (insulating film 30 acting as an etch stopper; e.g. paragraph 119) between and in direct contact with the dielectric layer (40 of Song/SO of Kawamura) and the further dielectric layer (100 of Song/IL2 of Kawamura).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the etch stopper as taught by Noguchi in the device of Kawamura in order to have the predictable result of using a known method to simplify manufacturing via holes uniformly across a wafer that is being processed, such that over etching a via hole is prevented.
Re claim 14: Song in view of Kawamura, Chen and Noguchi teaches the semiconductor component of claim 13, wherein: the further interconnect (153 of Song/W1 of Kawamura) is in direct contact with the interconnect (84 of Song/PL1 of Kawamura) at an interface (interface between 153 and 84; hereinafter “IF”), and the interface (IF) is arranged higher than the uppermost surface (CVP) of the dielectric layer (40) and lower than the uppermost surface (US184) of the spacer (184).
Re claim 15: Song in view of Kawamura, Chen and Noguchi teaches the semiconductor component of claim 13, wherein: the etch stop layer (30 of Noguchi) is in direct contact with and respectively between the further dielectric layer (100 of Song) and the spacers (184 of Song).
Conclusion
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898