DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed April 02, 2026 is acknowledged. New claims 28-30 have been added. Claims 1, 3-7, 10-17 and 19-27 have been amended. Non-Elected Species, claims 4-7 have been withdrawn from consideration. Claims 1, 3-7, 10-17 and 19-30 are pending.
New claim 28 recites:
The trench gate type power semiconductor device according to claim 27, wherein a depth of the first one of the plurality of conducting portions is the same as a depth of the second one of the plurality of conducting portions, and both a depth of a bottom of the base region from the front surface of the semiconductor substrate in touch with the first trench portion and a depth of a bottom of the base region from the front surface of the semiconductor substrate in touch with the second trench portion is a same.
These limitations directs to non-Elected Species.
Therefore, claim 28 is effectively withdrawn from consideration.
Action on merits of claims 1, 3, 10-17, 19-27 and 29-30 follows.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 29 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There does not appear to be a written description of the claim limitation “the trench gate type power semiconductor device according to claim 1, wherein a length where the base region contacts the conductive portion of the first trench is longer than a length where the base region contacts the conductive portion of the second trench” (new Claim 29) (emphasis added) in the application as filed.
The base region 14 cannot and has never contacted the conductive portion (polysilicon 44). (See FIG. 11).
Applicant must cancel the un-support new matters in response to the Office Action.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 29 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 29 recites the limitation "the trench gate type power semiconductor device according to claim 1, wherein a length where the base region contacts the conductive portion of the first trench is longer than a length where the base region contacts the conductive portion of the second trench". There is insufficient antecedent basis for this limitation in the claim.
There are neither first trench nor the second trench in independent claim 1.
Claim 29 lacks antecedent support. Therefore, claim 29 is indefinite.
Claim 29 contains new matter and indefinite.
Therefore, an action on merits of claim 29 is excluded.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 10-15, 27 and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KOCON et al. (US. Patent No. 6,916,712).
With respect to claim 1, KOCON teaches a trench gate type power semiconductor device including a semiconductor substrate which is a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate, substantially as claimed including:
a drift region (10; 203) with a first conductivity type (N) provided on the semiconductor substrate;
a base region (105; 205) with a second conductivity type (P) formed on a side of a front surface of the semiconductor substrate with a first conductivity type;
an emitter region (106; 206) with the first conductivity type (N) selectively formed on closer to a portion of the side of the front surface than the base region (105; 205);
a first contact region (104; 204) with the second conductivity type (P) formed on a side of a front surface of the base region (105; 205);
a plurality of linear trenches (107; 207) extending in a predetermined extension direction in the side of the front surface of the semiconductor substrate and reaching below the base region (105; 205);
a plurality of conducting portions (110; 210) filled within the plurality of linear trenches (107, 207);
an interlayer insulating film (111; 212) covering the front surface of the semiconductor substrate with a prescribed pattern; and
an emitter electrode (113; 215) connecting to the semiconductor substrate via a region exposed from the interlayer insulating film (111; 212) in a mesa region (317) between adjacent ones of the plurality of linear trenches (107; 207); and
a collector electrode (not shown) connected to a back surface of the semiconductor substrate,
wherein in a cross section perpendicular to the extension direction, a first trench portion and a second trench portion of the plurality of linear trenches (107; 207) are provided, the first trench portion having a first predetermined distance from the front surface of the semiconductor substrate to a deepest portion on a surface of a first one of the plurality of conducting portions (110), and the second trench portion having a second predetermined distance that is longer than the first predetermined distance from the front surface of the semiconductor substrate to a deepest portion on the surface of a second one of the plurality of conducting portions (207), and each of the first trench portion and the second trench portion includes, on a top end, a shoulder portion, and
the mesa region includes one or more active mesa regions that form a channel in a front layer of the base region (105; 205) when the trench power gate type power semiconductor device is turned on and allow current to flow between the collector electrode (not shown) and the emitter electrode (113; 215), and
the first trench portion and the second trench portion are each adjacent to any of the one or more active mesa regions. (See FIGs. 1-2, 3C).
Regarding the term “the mesa region includes one or more active mesa regions that form a channel in a front layer of the base region when the trench power gate type power semiconductor device is turned on and allow current to flow between the collector electrode and the emitter electrode”, the channel is inherently formed when the device is turned on.
With respect to claim 3, the first contact region (304) of KOCON has the second conductivity type (P), has a higher impurity concentration (P+) than (P) the base region (305), and is selectively formed on closer to a portion of the side of front surface than the base region (305); and
the first contact region (304) and the emitter region (306) are formed to be exposed in a predetermined manner along the extension direction of the plurality of linear trenches (307) in the mesa region (317), the first contact region (304) being in contact with at least one of the plurality of linear trenches (307). (See FIG. 3C).
With respect to claim 10, the emitter region of KOCON is formed such that a side thereof adjacent to at least one of the plurality of linear trenches is relatively long.
With respect to claim 11, the trench gate type power semiconductor device of KOCON is an IGBT,
the emitter region is arranged in a mesa region (317) adjacent at least one of the first trench portion and the second trench portion in the cross section perpendicular to the extension direction, and
the emitter region is not arranged symmetrically regarding a side of the first trench portion and a side of the second trench portion.
With respect to claim 12, the emitter region of KOCON has different depth at the side of the first trench portion (107) and the side of the second trench portion (207).
With respect to claim 13, the deepest portion on the surface of the first one of the plurality of conducting portions (110) in the first trench portion (107) or of the second one of the plurality of conducting portions (210) in the second trench portion (207) of KOCON is arranged at a center of the respective first trench (107) of the second trench (207) in the cross section perpendicular to the extension direction.
With respect to claim 14, a side of a side wall on the surface of the first one of the plurality of conducting portions (110) in the first trench portion (107) or of the second one of the plurality of conducting portions (210) in the second trench portion (207) of KOCON is relatively close to the front surface of the semiconductor substrate in the cross section perpendicular to the extension direction.
With respect to claim 15, the cross section perpendicular to the extension direction of KOCON passes through the emitter region.
With respect to claim 27, a depth of the second trench portion of KOCON is greater than a depth of the first trench portion.
With respect to claim 30, the interlayer insulating film (111; 212) of KOCON covers respective openings of the first trench (107) and the second trench (207) so as to extend beyond the front surface of the semiconductor substrate.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 16-17 and 19-26 are rejected under 35 U.S.C. 103 as being unpatentable over KOCON ‘712 as applied to claim 15 above, and further in view of KALNITSKY et al. (US. Pub. No. 2011/0298045).
With respect to claim 16, KOCON teaches the trench gate type power semiconductor device as described in claim 15 above, wherein the plurality of conducting portions (110; 210) are formed of a polysilicon, and the shoulder portion.
Thus, KOCON is shown to teach all the features of the claim with the exception of explicitly disclosing the shoulder portion has a convex curved surface portion that protrudes toward an inside of the semiconductor substrate.
However, KALNITSKY teaches a trench gate type power semiconductor device including: plurality of conducting portions (105) are formed of a polysilicon, and shoulder portion, wherein the shoulder portion has a convex curved surface portion that protrudes toward an inside of semiconductor substrate (160). (See FIG. 2I).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the trench gate type power semiconductor device of KOCON having the convex curved shoulder portion that protrudes toward the inside of the semiconductor substrate as taught by KALNITSKY to reduce cell pitch, thus increasing the number of active devices.
With respect to claim 17, the semiconductor device of KOCON or KALNITSKY, further comprises: an insulating film (*08) covering an inner wall of the trench to provide insulation between the semiconductor substrate and the conducting portion.
With respect to claim 19, in view of KALNITSKY, the shoulder portion has an average slope that is greater than a slope of the side wall, relative to a depth direction of the semiconductor substrate.
With respect to claim 20, in view of KALNITSKY, the shoulder portion has a linear shape in at least a portion thereof.
With respect to claim 21, in view of KALNITSKY, a length D1 of the shoulder portion in a depth direction of the semiconductor substrate is greater than a width W1 of the shoulder portion in a direction perpendicular to the extension direction. (See FIG. 2D).
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."). Applicable to claims 21-25.
With respect to claim 22, in view of KALNITSKY, the width W1 of the shoulder portion is greater than or equal to 1/20 and is less than or equal to 1/2 of a width of the first trench portion at a position opposite a top end of each of the plurality of conducting portions.
With respect to claim 23, in view of KALNITSKY, the width W1 of the shoulder portion is less than or equal to 1/4 of the width of the first trench portion at the position opposite the top end of each of the plurality of conducting portions.
With respect to claim 24, in view of KALNITSKY, the width W1 of the shoulder portion is greater than or equal to 1/10 of the width of the first trench portion at the position opposite the top end of each of the plurality of conducting portions.
With respect to claim 25, in view of KALNITSKY, at least a part of the shoulder portion has a slope greater than or equal to 20 degrees in a depth direction of the semiconductor substrate.
With respect to claim 26, in view of KALNITSKY, a top end of each of the plurality of conducting portions in the first trench portion (102) and in the second trench portion (101) is arranged at a position deeper than the front surface of the semiconductor substrate.
Response to Arguments
Applicant’s arguments with respect to amended and new claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANH D MAI/ Primary Examiner, Art Unit 2893
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