DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/13/2026 has been entered.
Claims 1, 13 and 16 have been amended. Claims 1-20 have been examined.
Response to Arguments/Amendments
The prior rejections under 35 USC § 112 are withdrawn in view of the claim amendments.
Applicant’s arguments, see pp. 10-11, filed 4/13/2026, with respect to the rejection(s) of claim(s) 1-4 and 7-18 under 35 USC § 103, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of U.S. Patent Application Publication 20210342733 by Kotler et al.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 7-18 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 20210342673 by Shah et al. ("Shah") in view of U.S. Patent Application Publication 20210073625 by Cai et al. ("Cai") and U.S. Patent Application Publication 20210342733 by Kotler et al. ("Kotler").
In regard to claim 1, Shah discloses:
1. A method comprising: See Shah, Fig. 1.
gathering first layers of a neural network graph by a data processing system into groups of layers using layer-wise … data that indicate respective execution times of the layers … Shah, ¶ 0023, “For each data transfer, the compiler analyzes all possible data transfer paths and generates a non-colliding data transfer path. Because the compiler can determine these at compile-time rather than at run-time, it can ensure that the data transfer instructions are not conflicting …” ¶ 0032, “In the example of FIG. 1B, the computations performed by layers 102A-D are allocated to groups 182A-D of Tiles as indicated. The allocation is not required to be 1:1. For example, multiple layers could be allocated to a single Tile or vice versa.” Also ¶ 0053, “The compiler knows when regions A/B will be ready and the instructions to implement layer K+1 will execute after that time.”
Shah does not expressly disclose profile data. See Cai ¶ 0045, “For example, a computation graph may include subgraphs that are commonly used in many machine learning models as their components. For example, the commonly used subgraphs can include MobileNets layers, ResNet layers, Region Proposal Network, etc. In some embodiments, prior history of execution, experiments, or simulations of a certain subgraph on accelerators can identify which accelerator is optimal for processing the certain subgraph.” Also ¶ 0046, “The operation profiling information may include execution time or speed information and delay information of an accelerator for executing a certain operation such as a convolution, matrix multiplication, etc.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Cai’s profile data with Shah’s execution data in order to identify which accelerator is optimal for processing the certain subgraph as suggested by Cai.
Shah and Cai also teach:
the profile data obtained by a compiler, and Shah, ¶ 0042, “In order to statically schedule the instructions in a deterministic phase, the compiler typically will know the duration of each instruction (i.e., how long each instruction takes to execute), the capabilities of each Tile (which Tiles can execute which instructions), the topology of data transfer paths to and from Tiles (including between Tiles, and between Tiles and on-chip memory), and the computations required and their dependencies (i.e., the MLN description). With this information, the compiler can schedule unconditional start times for the Tile instructions.” Also see Cai, ¶ 0029, “The compiler is a program or computer software that transforms computer codes written in one programming language into NPU instructions to create an executable program.” Note that since a compiler generates the executable program, associated profile data must be utilized by the compiler in order to produce the associated subgraphs. Also ¶ 0035, “In some embodiments, scheduler 210 may be implemented within a compiler.”
based on profiled compute times of the layers, determining total compute times for candidate groups of layers and assigning layers to groups …, Shah ¶ 0057, “… the compiler may optimize to increase the utilization of compute resources in the Tiles.” ¶ 0058, “Graph optimization 326 includes analysis of the graph representing the MLN to prune, merge or quantize links, parameters, values, and layers to achieve better performance. … This includes determining which computations are allocated to which Tiles and how data flows through the mesh of Tiles during computation.” ¶ 0061, “Other Tile meshes may also be statically scheduled, so long as the time required to execute computations and to transfer data between Tiles is deterministic and may be determined at compile time.” ¶ 0062, “Here, a single group Gi may perform computations associated with a set of adjacent layers of the MLN.” ¶ 0063, “The specific Tiles in each group may be assigned based on a set of predefined constraints and one or more optimization criteria.” ¶ 0065, “The compiler 120 determines 504 a proportion of the partial computation metric Ci for the layer i relative to the overall computation metric Ctotal, e.g., Ci/Ctotal.”
As indicated above, Shah provides broad disclosure regarding layer analysis for compute optimization. Shah does not expressly disclose: until the total compute times of the groups satisfy a compute-time balancing criterion. This is taught by Kotler. See ¶ 0022, “For example, the compiler may size the different groups such that the processing times for each group to implement computations of a respective layer on an input sample are substantially similar (e.g., within a threshold time).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Kotler’s layer-wise compute-time balancing with Shah’s optimization in order to provide lower cost, lower power consumption and higher performance as suggested by Kotler (see ¶ 0023).
Shah and Cai also teach:
forming the groups so that total compute times of groups are balanced according to the layer-wise profile data. Shah, ¶ 0057, “the compiler may optimize to increase the utilization of compute resources in the Tiles—to keep the compute pipelines as busy as possible. … the compiler may optimize with respect to data transfer to reduce the wait times of computations.” ¶ 0067, “For example, the Tiles may be selected to minimize data transfer times between the groups. In an embodiment, the process for identifying 510 Tiles for inclusion in particular groups of Tiles may be performed iteratively to refine the groupings over multiple iterations according to a specified set of constraints and/or a specified set of optimization criteria.” Also see Cai, ¶ 0045, “In some embodiments, graph partitioner 320 can partition a computation graph into multiple subgraphs that are executed on different accelerators based on the subgraph profiling information to optimize performance in executing the computation graph.” Also ¶ 0046, “The operation profiling information may include execution time or speed information and delay information of an accelerator for executing a certain operation such as a convolution, matrix multiplication, etc.”
wherein each group is a subgraph of one or more of the layers of the neural network; Shah, Fig. 3, depicting an optimized graph 335 which is then partitioned 328 into subgraphs for tile execution. Also see ¶ 0032, “In the example of FIG. 1B, the computations performed by layers 102A-D are allocated to groups 182A-D of Tiles as indicated. The allocation is not required to be 1:1. For example, multiple layers could be allocated to a single Tile or vice versa.”
compiling the neural network graph into instructions for pipelined execution of subgraphs across multiple compute circuits based on the balanced total compute times of the subgraphs; See Shah Fig. 2A, depicting compute circuits. Also Fig. 3 element 320 “Compiler,” along with ¶ 0055, “The compiler 320 receives the optimized graph 335 and produces the resulting computer program 350.” Also ¶ 0064, “The groups of Tiles G may operate in a pipelined manner.”
wherein the compiling includes designating, for each first subgraph of the subgraphs having output activations that are input activations of a second subgraph of the subgraphs, operations of the first subgraph to be performed by a first compute circuit of the plurality of compute circuits and operations of the second subgraph to be performed by a second compute circuit of the plurality of compute circuits; and See Shah Fig. 1B where elements 102A-D depict a neural network (i.e. “MLN”) whereby “output activations” flow from 1 layer to “input activations” of a following layer. Also ¶ 0032, “In each mesh, the Tiles 180 are organized in a regular pattern and the interconnections within each mesh provide data transfer paths between Tiles in the mesh. … In the example of FIG. 1B, the computations performed by layers 102A-D are allocated to groups 182A-D of Tiles as indicated.” Also see Fig. 3 and ¶ 0058, “Partitioning 328 concerns mapping the computations in the MLN to an implementation on the MLA. This includes determining which computations are allocated to which Tiles and how data flows through the mesh of Tiles during computation.” Also ¶ 0062, “For example, an MLN with fifteen layers may be allocated between five groups of Tiles in which the first group of Tiles G1 may perform computations associated with layers 1, 2, and 3; the second group of Tiles G2 may perform computations associated with layers 4, 5, and 6; the third group of Tiles G3 may perform computations associated with layers 7, 8, and 9; and so on.”
configuring the multiple compute circuits to execute the instructions such that intermediate activations generated within a compute circuit of the multiple compute circuits remain in on-chip memory during execution of its assigned subgraph. See Shah ¶ 0028, “The compiler 120 receives a description of a machine learning network 100 and generates a computer program 150 that implements the machine learning network using MLA 170.” Also Fig. 2B and ¶ 0047, “Each Tile 280 includes an L1 memory 282.” Also ¶ 0057, “It may also allocate computations to Tiles in order to reduce data transfers between Tiles in the same mesh, to reduce data transfers from outside the MLA and/or to reduce data transfers that cross the boundary of the mesh (e.g., reducing data transfers between L1 and L2 memory and trying to keep all data in L1 memory).”
In regard to claim 2, Shah also discloses:
2. The method of claim 1, further comprising:
gathering second layers of the neural network into another subgraph, wherein the second layers are serially connected and include layer 1 through layer N, and each layer 1 through layer N specifies generation of respective output activations based on respective input activations; wherein the compiling includes for the other subgraph: decomposing the input activations to layer 1 into a plurality of tiles; specifying for first layer processing, tile-by-tile processing of the plurality of tiles; and specifying for each layer M processing for 2 ≤M ≤(N - 1), tile-by-tile processing of output tiles from layer M as input tiles to layer (M + 1), where M is in an intermediate layer and N is a last layer. See Shah, Fig. 4 and ¶ 0062-0064, e.g. “For example, an MLN with fifteen layers may be allocated between five groups of Tiles in which the first group of Tiles G1 may perform computations associated with layers 1, 2, and 3; the second group of Tiles G2 may perform computations associated with layers 4, 5, and 6; the third group of Tiles G3 may perform computations associated with layers 7, 8, and 9; and so on. … The groups of Tiles implementing the intermediate layers of the MLN each perform computations on the outputs from the group of Tiles implementing the previous layer in the MLN and generate outputs to the groups of Tiles implementing the subsequent layer of the MLN.”
In regard to claim 3, Shah also discloses:
3. The method of claim 2, wherein the compiling includes specifying stitching of output tiles from layer N into a complete set of output activations of the other subgraph. Shah, ¶ 0053, “The layer K output may be stored in L2 memory and then retrieved from L2 memory as needed for the next layer's computations.”
In regard to claim 4, Shah also discloses:
4. The method of claim 2, wherein: the compute circuits are programmable logic circuits; the programmable logic circuits include the on-chip memory coupled to the compute circuits; and See Fig. 2A, depicting programmable logic circuits coupled to memory 274.
the compiling includes specifying that the output tiles from each layer M remain in the on-chip memory for processing as input tiles in layer (M + 1). Shah Fig. 1B elements 102A-D depict a neural network with 4 layers whereby output from one layer is provided as input for the next layer. Also see ¶ 0068, “The L2 memories 274 and Tiles 280 are interconnected nodes for data transfers to implement an MLN.”
In regard to claim 7, Shah discloses:
7. The method of claim 1, further comprising:
gathering second layers of the neural network into another subgraph, wherein the second layers are serially connected and include a first layer configured to generate first output activations based on first input activations and to provide the first output activations as second input activations to a second layer of the other subgraph; Shah, ¶ 0032, “In each mesh, the Tiles 180 are organized in a regular pattern and the interconnections within each mesh provide data transfer paths between Tiles in the mesh.” Also see Shah, Fig. 4 and ¶ 0062-0064, e.g. “For example, an MLN with fifteen layers may be allocated between five groups of Tiles in which the first group of Tiles G1 may perform computations associated with layers 1, 2, and 3; the second group of Tiles G2 may perform computations associated with layers 4, 5, and 6; the third group of Tiles G3 may perform computations associated with layers 7, 8, and 9; and so on. … The groups of Tiles implementing the intermediate layers of the MLN each perform computations on the outputs from the group of Tiles implementing the previous layer in the MLN and generate outputs to the groups of Tiles implementing the subsequent layer of the MLN.”
wherein the compiling includes for the other subgraph:
decomposing the first input activations into a plurality of tiles that includes a first input tile and a second input tile; Shah, ¶ 0032, “For example, multiple layers could be allocated to a single Tile or vice versa.” Here, the “vice versa” provides multiple tiles for a single layer.
specifying first layer processing of the first input tile and the second input tile by one compute circuit at different times or by two compute circuits in parallel; and ¶ 0035, “In FIG. 1C, the deterministic and non-deterministic phases are shown as alternating. This is not required. For example, deterministic and non-deterministic phases may execute concurrently.”
specifying, for a first output tile generated from the first layer processing of the first input tile and for a second output tile generated from the first layer processing of the second input tile, second layer processing of the first output tile and the second output tile without stitching the first output tile and the second output tile, wherein the second layer processing is by one compute circuit at different times or by two compute circuits in parallel. Shah, ¶ 0047, “In FIG. 2B, the L1 memory 282 may receive data from any of its adjacent Tiles and/or from L2 memory if it is an edge Tile. Similarly, it may transfer data to any of its adjacent Tiles and/or to L2 memory if it is an edge Tile. The data transfer operations are controlled by data transfer instructions received and executed by the Tiles.” Also ¶ 0064, “The groups of Tiles implementing the intermediate layers of the MLN each perform computations on the outputs from the group of Tiles implementing the previous layer in the MLN and generate outputs to the groups of Tiles implementing the subsequent layer of the MLN.”
In regard to claim 8, Shah discloses:
8. The method of claim 1, wherein:
the first and second compute circuits are disposed on a programmable device, the first compute circuit is coupled to a first on-platform memory bank, and the second compute circuit is coupled to a second on-platform memory bank; and See Fig. 2A, depicting compute circuits on a programmable device coupled to memory 274. Also Fig. 6, depicting multiple on-platform L2 memory banks .
the compiling includes generating instructions executable by a host processor coupled to the programmable device and when executed cause the host processor to initiate moving the output activations from the first on-platform memory bank to the second on-platform memory bank in response to completion of the operations associated with the first subgraph. Shah, Fig. 2A, depicting MLA 270 which consists of mosaics 272A-N. Any transfer of data among mosaics necessarily requires movement between respective memory banks 274 associated with a particular mosaic.
In regard to claim 9, Shah discloses:
9. The method of claim 1, wherein:
the first and second compute circuits are disposed on a programmable device, the first compute circuit is coupled to a first on-platform memory bank, and the second compute circuit is coupled to a second on-platform memory bank; and See Fig. 2A, depicting compute circuits on a programmable device coupled to memory 274. Also Fig. 6, depicting multiple on-platform L2 memory banks .
the compiling includes generating instructions executable by an on-device controller and when executed cause the on-device controller to initiate moving the output activations from the first on-platform memory bank to the second on-platform memory bank in response to completion of the operations associated with the first subgraph. Shah, ¶ 0036, “The Tiles may have circuitry that synchronizes the Tiles. For example, each Tile may monitor when it is ready to begin execution of a deterministic phase 152B and then actual execution begins when all Tiles signal that they are ready. Alternatively, an external controller may synchronize the Tiles and start the deterministic phase 152B when all Tiles are ready.”
In regard to claim 10, Shah does not expressly disclose:
10. The method of claim 1, wherein the compiler determines tile dimensions for inter-layer tile-by-tile processing based on profiled compute-time information and available on-chip memory capacity to minimize off-chip transfers. See Shah, Fig. 1B and ¶ 0032, “In the example of FIG. 1B, the computations performed by layers 102A-D are allocated to groups 182A-D of Tiles as indicated.” Also ¶ 0063, “The groups G may be limited to blocks of specific shapes (e.g., rectangles or squares) or the shape of the blocks may be unconstrained and may comprise arbitrary shapes.” Also ¶ 0067, “The compiler 120 identifies 510 specific Tiles for inclusion in the group of Tiles Gi having the size Ti. … For example, the Tiles may be selected to minimize data transfer times between the groups.”
In regard to claim 11, Cai also teaches:
11. The method of claim 1, wherein the profile data specify for each layer a respective number of cycles of a clock signal. Cai, ¶ 0046, “3) subgraph profiling information per accelerator. … The operation profiling information may include execution time.”
In regard to claim 12, Cai also teaches:
12. The method of claim 1, wherein the profile data specify for each layer a respective elapsed real time. Cai, ¶ 0046, “3) subgraph profiling information per accelerator. … The operation profiling information may include execution time.”
In regard to claim 13, Shah discloses:
13. A system, comprising: a computer storage arrangement configured with program code that when executed by one or more processors causes the one or more processors to perform operations including: See Shah, p. 11 at claim 20, “A non-transitory computer readable storage medium storing instructions for implementing a machine learning network on a machine learning accelerator (MLA), … the instructions when executed by one or more processors causing the one or more processors to perform steps …”
…
assigning layers to the groups based on the respective execution times indicated by the layer-wise profile data … Shah ¶ 0058, “Graph optimization 326 includes analysis of the graph representing the MLN to prune, merge or quantize links, parameters, values, and layers to achieve better performance. … This includes determining which computations are allocated to which Tiles and how data flows through the mesh of Tiles during computation.” ¶ 0061, “Other Tile meshes may also be statically scheduled, so long as the time required to execute computations and to transfer data between Tiles is deterministic and may be determined at compile time.” ¶ 0062, “Here, a single group Gi may perform computations associated with a set of adjacent layers of the MLN.” ¶ 0063, “The specific Tiles in each group may be assigned based on a set of predefined constraints and one or more optimization criteria.” ¶ 0065, “The compiler 120 determines 504 a proportion of the partial computation metric Ci for the layer i relative to the overall computation metric Ctotal, e.g., Ci/Ctotal.”
As indicated above, Shah provides broad disclosure regarding layer analysis for compute optimization. Shah does not expressly disclose: to balance total compute times of the groups, This is taught by Kotler. See ¶ 0022, “For example, the compiler may size the different groups such that the processing times for each group to implement computations of a respective layer on an input sample are substantially similar (e.g., within a threshold time).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Kotler’s layer-wise compute-time balancing with Shah’s optimization in order to provide lower cost, lower power consumption and higher performance as suggested by Kotler (see ¶ 0023).
…
an arrangement of one or more processors coupled to the computer storage arrangement and configured to communicate the program code to another computer storage arrangement in response to download instructions. Shah, ¶ 0059, “The resulting computer program 350 may be loaded into memory for execution on a machine learning accelerator 370.”
All further limitations of claim 13 have been addressed in the above rejection of claim 1.
In regard to claims 14-15, parent claim 13 is addressed above.
All further limitations of claims 14-15 have been addressed in the above rejections of claims 2-3, respectively.
In regard to claim 16, Shah discloses:
16. A method comprising: Shah, Fig. 1A, depicting a method.
…
assigning layers to the subgraph based on the respective execution times indicated by the layer-wise profile data … Shah ¶ 0058, “Graph optimization 326 includes analysis of the graph representing the MLN to prune, merge or quantize links, parameters, values, and layers to achieve better performance. … This includes determining which computations are allocated to which Tiles and how data flows through the mesh of Tiles during computation.” ¶ 0061, “Other Tile meshes may also be statically scheduled, so long as the time required to execute computations and to transfer data between Tiles is deterministic and may be determined at compile time.” ¶ 0062, “Here, a single group Gi may perform computations associated with a set of adjacent layers of the MLN.” ¶ 0063, “The specific Tiles in each group may be assigned based on a set of predefined constraints and one or more optimization criteria.” ¶ 0065, “The compiler 120 determines 504 a proportion of the partial computation metric Ci for the layer i relative to the overall computation metric Ctotal, e.g., Ci/Ctotal.”
As indicated above, Shah provides broad disclosure regarding layer analysis for compute optimization. Shah does not expressly disclose: to balance a total compute time of the layers in the subgraph relative to total compute times of other subgraphs; This is taught by Kotler. See ¶ 0022, “For example, the compiler may size the different groups such that the processing times for each group to implement computations of a respective layer on an input sample are substantially similar (e.g., within a threshold time).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Kotler’s layer-wise compute-time balancing with Shah’s optimization in order to provide lower cost, lower power consumption and higher performance as suggested by Kotler (see ¶ 0023).
All further limitations of claim 16 have been addressed in the above rejection of claims 1-2.
In regard to claims 17-18, parent claim 16 is addressed above.
All further limitations of claims 17-18 have been addressed in the above rejections of claims 3-4, respectively.
Claims 5 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Shah in view of Cai and Kotler and further in view of U.S. Patent 9436760 to Tacchi et al. ("Tacchi").
In regard to claim 5, Shah does not expressly disclose:
5. The method of claim 2, wherein the gathering includes: determining a quantity of the on-chip memory available to a compute circuit; and determining a tile size of the plurality of tiles of the input activations of layer 1 based on the quantity of on-chip memory available. This is taught by Tacchi. See col. 20, lines 16-20 “In some embodiments, tile size may be selected based on the amount of available memory at various levels of a memory hierarchy, such that a given tile can fit within a targeted level of the hierarchy, like the level 2 or level 3 cache.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Tacchi’s tile size selection with Shah’s memory in order to ensure that a tile can fit in the memory as suggested by Tacchi.
In regard to claim 19, parent claim 16 is addressed above.
All further limitations of claim 19 have been addressed in the above rejection of claim 5.
Claims 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shah in view of Cai and Kotler and further in view of U.S. Patent 10019668 to Woo ("Woo").
In regard to claim 6, Shah does not expressly disclose:
6. The method of claim 2, wherein the compiling includes: determining respective activation sizes of the layers of the neural network; and wherein the gathering the second layers of the neural network into groups of layers includes limiting the subgraphs to layers having activation sizes greater than a threshold. This is taught by Woo. See col. 15, lines 27-36, “Circuit 100 can compare the total memory usage for each group of layers to the 500 MB on-chip storage capacity. Circuit 100 can then determine a partitioning or grouping of layers that form a sequence of superlayers based on the results of the comparison. Circuit 100 determines the partitioning of the layers into a sequence of superlayers so as to not exceed the threshold storage capacity of the on-chip memory (500 MB) when a hardware circuit processes a batch of neural network inputs for the working sets.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Woo’s partitioning in Shah’s compiler in order to avoid exceeding storage capacity as suggested by Woo.
In regard to claim 20, parent claim 16 is addressed above.
All further limitations of claim 20 have been addressed in the above rejection of claim 6.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James D Rutten whose telephone number is (571)272-3703. The examiner can normally be reached M-F 9:00-5:30 ET.
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/James D. Rutten/Primary Examiner, Art Unit 2121
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