DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 15 September 2025 has been entered.
Response to Amendment
The Office acknowledges receipt on 15 September 2025 of Applicants’ amendments in which claims 1, 3, 5, 6, 8, 9, 12, 13, 17, and 21 are amended, claim 24 is cancelled, and claim 27 is newly added.
Response to Arguments
Applicants’ arguments with respect to claim(s) 1 and 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 26, and 27 is/are under 35 U.S.C. 103 as being unpatentable over Li et al. (US20130119494A1) in view of Chou et al. (US9550667B1) and Wang et al. (US20210035620A1).
Regarding claim 1, Li teaches in Fig. 6F, 6H a semiconductor structure comprising:
a bump of a conductive material (610) on a top electrode (605/TE) of a pillar-type memory device (601-606) {Figs. 6A, 6B, 6F}; and the bump of the conductive material (610) rises above a height of the top electrode (605/TE) {Fig. 5A; ¶0061, 0072; ¶0076, The top electrode contact (TEC) film 610 may … include … Ta, TaN, Ti, TiN; Also, bump 610 is stacked on top electrode 605/TE so as to rise above the height of the top electrode}; and
an encapsulation dielectric material (607) covers a sidewall of the pillar-type memory device (601-606), wherein the encapsulation dielectric material (607) has a top surface that is coplanar with a top surface of the top electrode (605/TE) and contacts a bottom surface of the bump of the conductive material (610) {Figs. 6C, 6F; ¶0074}.
Li does not teach:
the bump of conductive material has a semi-spherical-like shape;
a bottom surface of the semi-spherical-like shaped bump is of a first width;
the first width is narrower than a second width of the semi-spherical-like shaped bump, the second width parallel to the first width.
In an analogous art, Chou teaches in Fig. 3 and lines 1 and 2 of column 14 a bump (111b) of conductive material has a semi-spherical-like shape; a bottom surface of the semi-spherical-like shaped bump (111b) is of a first width; the first width is narrower than a second width of the semi-spherical-like shaped bump, the second width parallel to the first width. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li’s array of pillar-type memory devices based on the teachings of Chou – such that the bump of conductive material has a semi-spherical-like shape; a bottom surface of the semi-spherical-like shaped bump is of a first width; the first width is narrower than a second width of the semi-spherical-like shaped bump, and the second width parallel to the first width – because all the claimed elements (e.g., conductive bump, spherical shape, width) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Chou) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Furthermore, a change of shape is a matter of design choice which a person of ordinary skill in the art would have found obvious before the effective filing date of the claimed invention. MPEP §2144.04(IV)(B).
Li as modified by Chou does not teach wherein the encapsulation dielectric material has a bottom surface that is lower than a bottommost point of a bottom electrode of the pillar-type memory device
In an analogous art, Wang et al. teaches in Fig. 9 and paragraph [0018] an encapsulation dielectric material (402) has a bottom surface that is lower than a bottommost point of a bottom electrode (302) of a pillar-type memory device (330). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li’s array of pillar-type memory devices as modified by Chou based on the teachings of Wang – such that the encapsulation dielectric material has a bottom surface that is lower than a bottommost point of a bottom electrode of the pillar-type memory device – to prevent the exposed sidewalls … of the memory stack structures … from being oxidized or absorbing contamination. Wang ¶0018.
Regarding claim 2, Li as modified by Chou and Wang teaches the semiconductor structure of claim 1, and Li further teaches wherein the top electrode (605/TE) is a thin top {BRI of Li’s top electrode TE includes a thin top}.
Examiner’s Note: The claimed term “thin” is a relative term. Under BRI, the thickness of the top electrode is thinner than other structures.
Regarding claim 3, Li as modified by Chou and Wang teaches the semiconductor structure of claim 1, and Li further teaches wherein the semi-spherical-like-shaped bump (modified 610) is wider than the top electrode (605/TE) of the pillar-type memory device {Fig. 6F}.
Regarding claim 26, Li as modified by Chou and Wang teaches the semiconductor structure of claim 1, but Li does not teach wherein the bump of the conductive material is wider than the bottom electrode.
Wang teaches in Fig. 9 and paragraph [0023] a bump of conductive material (606) is wider than a bottom electrode (302). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li’s array of pillar-type memory devices as modified by Chou and Wang based on the further teachings of Wang – such that the bump of the conductive material is wider than the bottom electrode – because [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 27, Li as modified by Chou and Wang teaches the semiconductor structure of claim 1, and Li further teaches further comprising
a top electrode contact (613) contacting the semi-spherical-like shaped bump (modified 610) {Fig. 6H; ¶0079]}, wherein:
the semi-spherical-like shaped bump (modified 610) and the top electrode (605) are each a first material (Ta/TaN) {¶0072, 0076}; and
the top electrode contact (613) is a second material (copper), different from the first material (Ta/TaN) {¶0079).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Chou and Wang as applied to claim 1 above, and further in view of Kao et al. (US20230138005A1).
Regarding claim 4, Li as modified by Chou and Wang teaches the semiconductor structure of claim 1, and Li further teaches wherein the pillar-type memory device further comprises:
the bottom electrode contact (405) on a metal layer (407) in a selection from the group consisting of: a back end of line metal layer (407) and a middle of line metal layer {Fig. 4A; ¶0054, 0060, In the BEOL part of fabrication, stage contacts (e.g., pads), interconnect wires, vias and dielectric structures are formed; Bottom electrode contact 405 is a contact of BEOL and metal layer 407 is a via of BEOL},
wherein the bottom electrode (411/BE) is on the bottom electrode contact (405) {Fig. 4B; ¶0055};
one or more magnetic tunnel junctions (601-604 & 616) above the bottom electrode (411/BE) {Fig. 6A; ¶0072};
the top electrode (605/TE) on the one or more magnetic tunnel junctions (601-604 & 616) {Fig. 6A}.
Li does not teach the encapsulation dielectric material covering sidewalls of the top electrode, the one or more magnetic tunnel junctions, the bottom electrode, and a dielectric material surrounding the bottom electrode contact on a portion of a selection from the group consisting of: the back end of line metal layer and the middle of line metal layer.
In an analogous art, Kao teaches in Figs. 9 and 10 and paragraphs [0045] and [0050] the encapsulation dielectric material (185) covering sidewalls of the top electrode (160’), the one or more magnetic tunnel junctions (150’), the bottom electrode (140’), and a dielectric material (120C’) surrounding the bottom electrode contact (130B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li’s semiconductor structure as modified by Chou and Wang based on the teachings of Kao – to have the encapsulation dielectric material covering sidewalls of the top electrode, the one or more magnetic tunnel junctions, the bottom electrode, and a dielectric material surrounding the bottom electrode contact – for the purpose of enhanc[ing] insulation of sidewalls of MRAM cells [and] improv[ing] MTJ performance. Kao ¶0045. A consequence of this modification is that Kao’s encapsulation dielectric material surrounds Li’s bottom electrode contact on a portion of a selection from a group consisting of: the back end of line metal layer and the middle of line metal layer.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Chou, Wang, and Kao as applied to claim 4 above, and further in view of Shen et al. (WO2022048084A1) and Chiang et al. (US20200176032A1).
Regarding claim 6, Li as modified by Chou, Wang, and Kao teaches the semiconductor structure of claim 4, but Li does not teach wherein a bottom portion of the encapsulation dielectric material is surrounded by a self-leveling dielectric material; the self-leveling dielectric material has a topmost point in a logic area of the semiconductor structure that is below a bottom surface of the top electrode; and the logic area is a portion of the semiconductor structure that is above one or more logic devices.
In an analogous art, Shen teaches in Fig. 1 and paragraph [0044] a bottom portion (a portion above the horizontally extending section of 103 and surrounding 101) of an encapsulation dielectric material (103) is surrounded by another dielectric material (104); the other dielectric material (104) has a topmost point in a logic area (area above substrate 100, which has transistors ¶[0004, 0045]1) of a semiconductor structure (rightmost/leftmost structure illustrated by Fig. 1) that is below a bottom surface of a top electrode (105); and the logic area (area above substrate 100, which has transistors ¶[0004, 0045]) is a portion of the semiconductor structure that is above one or more logic devices (e.g., transistors ¶[0004, 0045]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li’s semiconductor structure as modified by Chou, Wang, and Kao based on the teachings of Shen – such that a bottom portion of the encapsulation dielectric material is surrounded by another dielectric material; the other dielectric material has a topmost point in a logic area of the semiconductor structure that is below a bottom surface of the top electrode; and the logic area is a portion of the semiconductor structure that is above one or more logic devices – for the purpose of increasing the surface area contact between a metal hard mask and an upper electrode of an MRAM to thereby reduce the resistance therebetween and a likelihood of an open circuit condition. Shen ¶0034.
Li as modified by Shen does not teach that Shen’s other dielectric material is self-leveling.
In an analogous art, Chiang teaches in Fig. 3 and paragraph [0048] a flowable dielectric material (30). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li’s semiconductor structure as modified by Chou, Wang, Kao, and Shen based on the teachings of Chiang – such that the dielectric material is self-leveling (i.e., flowable) – for the purpose of fill[ing] gaps or spaces with a high aspect ratio. Chiang ¶0048.
Claim(s) 8-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Chou, Wang, Kao, Chiang, and Chang et al. (US20220020917A1).
Regarding claim 8, Li teaches in Figs. 6C, 6D, 6F, and 6H an array of pillar-type memory devices comprising:
a plurality of pillar-type memory devices (601-606) in an array (1 row, 2 column array) {Figs. 6A, 6B, 6F}, wherein each of the pillar-type memory devices (601-606) has a bump of a conductive material (610) on a top electrode (605/TE) of each of the pillar-type memory devices (601-606) in the array (1 row, 2 column array) {Fig. 6F; ¶0076, The top electrode contact (TEC) film 610 may … include … Ta, TaN, Ti, TiN }; and
an encapsulation dielectric material (607) covers a sidewall of each of the plurality of pillar-type memory devices (601-606) in the array (1 row, 2 column array) and is not over the conductive material (610), wherein each encapsulation dielectric material (607): contacts a respective bottom surface of a corresponding respective conductive material (610) and has a top surface coplanar with a respective top surface of a corresponding respective top electrode (605) {Figs. 6C, 6F; ¶0074}.
Li does not teach:
the bump is semi-spherical-like shape;
a bottom surface of the semi-spherical-liked shaped bump is of a first width; and
the first width is narrower than a second width of the semi-spherical-like shaped bump, the second width parallel to the first width.
Chou teaches in Fig. 3 and lines 1 and 2 of column 14 a bump (111b) of conductive material has a semi-spherical-like shape; a bottom surface of the semi-spherical-like shaped bump (111b) is of a first width; the first width is narrower than a second width of the semi-spherical-like shaped bump, the second width parallel to the first width. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li’s array of pillar-type memory devices based on the teachings of Chou – such that the bump of conductive material has a semi-spherical-like shape; a bottom surface of the semi-spherical-like shaped bump is of a first width; the first width is narrower than a second width of the semi-spherical-like shaped bump, and the second width parallel to the first width – because all the claimed elements (e.g., conductive bump, spherical shape, width) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Chou) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Furthermore, a change of shape is a matter of design choice which a person of ordinary skill in the art would have found obvious before the effective filing date of the claimed invention. MPEP §2144.04(IV)(B).
Li as modified by Chou does not teach each encapsulation dielectric material has a bottom surface that is lower than a respective bottommost point of a corresponding respective bottom electrode of the respective pillar-type memory device.
Wang et al. teaches in Fig. 9 and paragraph [0018] that each encapsulation dielectric material (402) has a bottom surface that is lower than a respective bottommost point of a corresponding respective bottom electrode (302) of a respective pillar-type memory device (330). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li’s array of pillar-type memory devices as modified by Chou based on the teachings of Wang – such that each encapsulation dielectric material has a bottom surface that is lower than a respective bottommost point of a corresponding respective bottom electrode of the respective pillar-type memory device – to prevent the exposed sidewalls … of the memory stack structures … from being oxidized or absorbing contamination. Wang ¶0018.
Li as modified by Chou and Wang does not teach a self-leveling dielectric material between bottom portions of the encapsulation dielectric material.
Kao teaches in Fig. 9 and paragraph [0050] a dielectric material (190) between bottom portions of the encapsulation dielectric material (185). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li’s semiconductor structure as modified by Chou and Wang based on the teachings of Kao – such that a dielectric material is between bottom portions of the encapsulation dielectric material – for the purpose of forming a dielectric material filling spaces between the MTJ stacks, bottom electrodes, and/or top electrodes of the MRAM cells. Kao ¶0050.
Li as modified by Chou, Wang, and Kao does not teach Kao’s dielectric material is self-leveling.
Chiang teaches in Fig. 3 and paragraph [0048] a flowable dielectric material. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li’s semiconductor structure as modified by Chou, Wang, and Kao based on the teachings of Chiang – such that the dielectric material is self-leveling (i.e., flowable) – for the purpose of fill[ing] gaps or spaces with a high aspect ratio. Chiang ¶0048.
Li as modified by Chou, Wang, Kao, and Chiang does not teach an interlayer dielectric material is over the self-leveling dielectric material and between adjacent ones of the semi-spherical-like bumps of the conductive material on the top electrode of the pillar-type memory devices.
In an analogous art, Chang teaches in Fig. 11 and paragraphs [0076] and [0085] an interlayer dielectric material (170) is over the dielectric material (110) and between adjacent ones of the bumps of the conductive material (664) on the top electrode (158) of the pillar type-memory devices (101). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Li’s semiconductor structure as modified by Chou, Wang, Kao, and Chiang based on the teachings of Chang – such that an interlayer dielectric material is over the self-leveling dielectric material and between adjacent ones of the semi-spherical-like bumps of the conductive material on the top electrode of the pillar type-memory devices – for the purpose of surround[ing], and embed[ding], each of the top electrodes 158 (e.g., insulating the electrodes). Chang ¶0080.
Regarding claim 9, Li as modified by Chou, Wang, Kao, Chiang, and Chang teaches the array of pillar-type memory devices of claim 8, and Li further teaches further comprising:
a plurality of bottom contacts (405) in a dielectric material (ILD/IMD 403), one bottom contact (405) for each pillar-type memory device (601-606) of the array (1 row, 2 column array) of pillar-type memory devices (601-606), wherein each of the plurality of bottom contacts (405) resides on a portion of a first metal layer (407) {Fig. 4A; ¶0054}; and
each of the semi-spherical-like shaped bump (modified 610) on the top electrode (605/TE) of the pillar-type memory devices in the array of pillar-type memory devices contacts a top electrode contact (614) formed in a second metal layer (614) above the first metal layer (407) {Fig. 6H; ¶0079}.
Regarding claim 10, Li as modified by Chou, Wang, Kao, Chiang, and Chang teaches the array of pillar-type memory devices of claim 9, and Li further teaches wherein the first metal layer (407) is in a selection from the group consisting of: a back end of line metal layer and a middle of line metal layer {¶0060, In the BEOL part of fabrication, stage contacts (e.g., pads), interconnect wires, vias and dielectric structures are formed}.
Regarding claim 11, Li as modified by Chou, Wang, Kao, Chiang, and Chang teaches the array of pillar-type memory devices of claim 8, and Li further teaches wherein the plurality of pillar-type memory devices in the array are of a selection from the group consisting of: a magnetoresistive random-access memory device, a resistive random-access memory, and a phase change random-access memory device {¶0086, An MTJ device as disclosed herein may also be utilized for MRAM fabrication}.
Regarding claim 12, Li as modified by Chou, Wang, Kao, Chiang, and Chang teaches the array of pillar-type memory devices of claim 8, and Li further teaches wherein the semi-spherical-like shaped bump (modified 610) on the top electrode (605/TE) of each of the pillar-type memory devices in the array is wider than the top electrode (605/TE) {Fig. 6H}.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Erwin et al. (US20130026624A1) teaches a solder bump support structure includes an inter-level dielectric (ILD) layer formed over a silicon substrate. The ILD layer has a plurality of conductive vias. The structure further includes a first insulation layer formed on the ILD layer. The solder bump support structure further includes a pedestal member formed on the ILD layer which includes a conductive material formed above the plurality of conductive vias in the ILD layer coaxially surrounded by a second insulation layer. The second insulation layer is thicker than the first insulation layer. The structure further includes a capping under bump metal (UBM) layer formed over, and in electrical contact with, the conductive material and formed over at least a portion of the second insulation layer of the pedestal member.
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891