DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on Jan. 2nd 2026 has been entered.
Response to Amendment
The amendment filed on Nov. 19th 2025 has been entered. Claims 1-14 remain pending in the application. Applicant’s amendments to the Claims have overcome each and every objection previously set forth in the Non-Final Office Action mailed on Oct. 1st 2025. Claims 1-6 are examined in this office action. Claims 7-14 are withdrawn from further consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson et al. (US 20090020764 from IDS) in view of Yamazaki et al. (US 20130200375).
Regarding claim 1, Anderson teaches a field-effect transistor device (field effect transistor; Abstract) formed with a two-dimensional material (fig. 23, planar graphene layer 20; para. 0104), the field-effect transistor device (field effect transistor) comprising:
a channel (channel portion; para. 0104) composed of a first portion (middle portion) of the two-dimensional material (20) on a substrate (silicon carbide substrate 10; para. 0104);
a high-k gate dielectric (gate dielectric 60 has high-k dielectric material; para. 0105) on the channel (channel portion);
a metal gate (gate electrode 70; para. 0107) inside and contacting the high-k gate dielectric (60) over the channel (channel portion); and
a source/drain (contact vias 90 on source and drain regions 42; para. 0108) on a second portion (side portion) of the two-dimensional material (20) on the substrate (10).
Anderson fails to teach the high-k gate dielectric extending directly under a sidewall spacer and along the sidewall spacer;
the high-k gate dielectric is between the metal gate and the sidewall spacer, wherein a bottom-most side of the metal gate and a bottom-most side of the sidewall spacer are at a same level.
However, Yamazaki teaches the high-k gate dielectric (Yamazaki: fig. 5A, insulating layer 411, gate insulating layer 402, which have high-K oxide film; para. 0042, 0043, similar to 60 of Anderson) extending directly under a sidewall spacer (Yamazaki: sidewall insulating layer 412; para. 0042) and along the sidewall spacer (Yamazaki: 412);
the high-k gate dielectric (Yamazaki: 411) is between the metal gate (Yamazaki: gate electrode layer 401; para. 0042, similar to 70 of Anderson) and the sidewall spacer (Yamazaki: 412), wherein a bottom-most side of the metal gate (Yamazaki: bottom-most side of 401) and a bottom-most side of the sidewall spacer (Yamazaki: bottom-most side of 412) are at a same level.
Yamazaki and Anderson are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the gate structure with a sidewall spacer as taught by Yamazaki.
Doing so would realize an insulating layer to suppress entry of water or hydrogen and elimination of oxygen, which leads to an improvement in reliability of the transistor (Yamazaki: para. 0176).
Regarding claim 6, Anderson in view of Yamazaki further teaches the field-effect transistor device of claim 1, wherein the high-k gate dielectric (Anderson: fig. 23, 60) on the channel (Anderson: channel portion) extends under the sidewall spacer (Yamazaki: fig. 5A, 411 under 412) does not go under the source/drain (Anderson: 60 not under 90).
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson in view of Yamazaki as applied to claim 1 above, and further in view of Li et al. (US 20220115541).
Regarding claim 2, Anderson in view of Yamazaki teaches the field-effect transistor device of claim 1, wherein the source/drain (Anderson: fig. 30, 90) on the second portion of the two-dimensional material (Anderson: side portion of 20)
Anderson in view of Yamazaki fails to explicitly teach the source/drain is composed of a bi-layer metal.
However, Li teaches the source/drain (Li: fig. 1K, metal contacts 152, layers 126; para. 0026, 0027, similar to 90 of Anderson) is composed of a bi-layer metal (Li: 152 is metal contacts and 126 is two-dimensional metallic material; para. 0023).
Li, Yamazaki and Anderson are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the bi-layer metal as taught by Li.
Doing so would realize semiconductor-metallic junctions lowering the contact resistance due to a van der Waals gap (Li: para. 0029).
Regarding claim 3, Anderson in view of Yamazaki teaches the field-effect transistor device of claim 1, wherein the source/drain (Anderson: fig. 30, 90) on the second portion of the two-dimensional material (Anderson: side portion of 20).
Anderson in view of Yamazaki fails to explicitly teach the source/drain is composed of a first metal on the second portion of the two-dimensional material with a lower electrical contact resistivity with the two-dimensional material than a second metal that is on the first metal.
However, Li teaches the source/drain (Li: fig. 1K, metal contacts 152, layers 126; para. 0026, 0027, similar to 90 of Anderson) is composed of a first metal (Li: 126 of two-dimensional metallic material; para. 0023) on the second portion of the two-dimensional material (Li: strips 160 of two-dimensional semiconductor material on the side; para. 0026, similar to side portion of 20 of Anderson) with a lower electrical contact resistivity (Li: stack of 126 with 160 lowering the contact resistance; para. 0029) with the two-dimensional material (Li: 160) than a second metal (Li: 152) that is on the first metal (Li: 126).
Li, Yamazaki and Anderson are considered to be analogous to the claimed invention because they are in the same field of transistor devices.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the first metal and the second metal as taught by Li.
Doing so would realize semiconductor-metallic junctions lowering the contact resistance due to a van der Waals gap (Li: para. 0029).
Regarding claim 4, Anderson in view of Yamazaki and Li further teaches the field-effect transistor device of claim 3, wherein the second metal (Li: fig. 1K, 152) has a lower bulk resistivity (Li: 152 has tungsten, which is a well-known metal with low bulk resistivity; para. 0026) than the first metal (Li: 126).
Regarding claim 5, Anderson in view of Yamazaki and Li further teaches the field-effect transistor device of claim 3 including the first metal (Li: fig. 1K, 126).
Anderson in view of Yamazaki and Li as applied to claim 3 above fails to explicitly teach the first metal has a thickness less than two times a thickness of the high-k gate dielectric.
However, Li teaches the first metal (Li: fig. 1K, 126) has a thickness (Li: thickness of a monolayer in 126; para. 0025) less than a thickness of the high-k gate dielectric (Li: thickness of gate dielectric layer 166; para. 0027, similar to 60 of Anderson), which overlaps the ratio range of less than two times.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the thickness ratio range from to less than two times.
Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). Since the applicants have not established the criticality of the thickness range claimed, it would have been obvious to one of ordinary skill in the art to use and modify the value in the device of Li. The specification contains no disclosure of either the critical nature of the claimed thickness range for the conductive layer or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Response to Arguments
Applicant’s arguments with respect to claims 1-6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818