DETAILED ACTION
This Office Action is in response to the application filed on 07/09/2025. Claims 1-20 are pending in this application. Claims 1,12,17 are independent claims. Claims 1-20 are amended.
Response to amendments/arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Contingent limitations
Claim 1 recites “selecting a modification from multiple modifications, by one or more processors, if the simulation activity data exceeds one or more thresholds, wherein the selected modification relates to one or more of improving the IC design or reducing resources needed to simulate the IC design; this entire limitation is considered as contingent limitations requires only those steps that must be performed (i.e. selecting if …exceeds ..thresholds) and does not include steps that are not required to be performed (i.e. claim step is missing if simulation data activity does not exceeded threshold).
SC 112 Rejection
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 4 recites “wherein the extracting comprises” on line 7. There is insufficient antecedent basis for this limitation in the claim.
Claims 13, 14, 15 and 16 recites the limitation "THE INSTRUCTION” in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 8 recites “identifying a signal of the circuit design that is mislabeled as one of a clock signal and a non-clock based on toggle activity of the signal and a signal toggle threshold.” Passage from the specification does not discloses the identifying signal that is mislabeled as claimed.
Specification para [0043] discloses “In an embodiment, the signal events report 402 provides information about operation of signals during a simulation. For example, the signal events report 402 can indicate a number of times a given signal is toggled during simulation. In an embodiment, the signal events report 402 identifies each signal using a suitable identifier (e.g., a key or a unique numbering scheme). [0044] In an embodiment, the process events report 412 provides information about operation of processes during simulation. For example, the process events report 412 can indicate a number of times a given process is triggered during simulation. In an embodiment, the process events report 412 identifies each process using a suitable identifier (e.g., a name or number).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1,2,3,5,7,10,12,13, 14,17,18 and 19 are rejected under 35 USC 102 (a) as anticipated over Yang et al (US2014/0181768).
Regarding claims 1, 12, 17 , Yang teaches a method comprising: identifying, by one or more processors, simulation activity data from results of a circuit simulation an integrated circuit (IC) design (see abstract).
Yang specifically teach, “selecting a modification from multiple modifications, by one or more processors, if the simulation activity data exceeds one or more thresholds”, (see para 0025-0026, performance analysis module 415 calculates the theoretical peak rate, compares it with the measured data and analyzes the difference between them. This includes calculating a theoretical peak rate value (440). Yang also teaches “wherein the selected modification relates to one or more of improving the IC design, by one or more processors. (see 0027 “If the unit did not meet the desired or expected peak rate (448)….analyzing the starve/stall value for each unit (450), analyzing the latency information (452).
Wherein the selected modification relates to one or more improving the IC design or reducing resources needed to simulate the IC design (see para 0032, the automated verification system ..may save 1-3 personnel on the verification work for each project, on para 0033, Yang discloses “Examples of performance pass rule 600 implemented as the compare actual peak rate with theory one 444 and pass 446 as part of the performance evaluation module and pass blocks).
Yang teaches Performing an action based on the selected modification, by the one or more processors, (0033, “The performance test may need to be adjusted and the test rerun (635).)
Regarding claims 2 and 13, yang teaches “selecting modification comprises one or more of: selecting a modification for the IC design; .” (see para 00200 and (0021)). Note claim recites markush group i.e. “modification comprises one or more”, therefore only one of the selecting is required to map from the teaching reference.
Regarding claims 3 and 14, Yang teaches wherein the performing the action comprises one or more: modifying the IC design based on the selected modification ( see para 0042, and claim 15 “the processor configured to check workload balance for each unit; and the processor configured to adjust the performance tests based on an identified bottleneck.”). Again claim contains Markush grouping “comprises one or more, therefor penetrability is given on only one of the action.
Regarding claim 5, Yang teaches the method as recited in claim 1, “identifying a scope record reflecting simulation activity for a HDL scope relating to the IC design, and wherein selecting modification comprises selecting the modification based on the scope record (see [0016], A processor is configured to generate design feature-specific performance tests that could be for a sub-circuit of an integrated circuit design and use the performance tests to generate actual simulation performance results; (Claims 11 and 12) the processor is configured to identify performance measurements from the actual performance results, where the performance measurements include at least one of throughput, execution time, register settings, starve/stall values, workload balance values and latency values; (claim 13 and 14) the processor is further configured to identify a bottleneck performance measurement based on peak rate analysis; ([0016] and [0041]-[0045]) Additionally the processor that generates the design-specific performance tests that could be for a sub-circuit of an integrated circuit design may be manufactured with HDL instructions to implement the embodiments, thus also having a HDL scope relating to the integrated circuit design).
Regarding claim 7, Yang teaches the method as recited in claim 5, wherein the scope record comprises a process record identifying simulation activity for a process of the circuit design, and wherein the selecting the modification comprises selecting the modification based on the process record. (Claim 5, A peak rate value is computed for each performance measurement, ([0015]-[0017]) where the performance measurement can be for example the execution time relating to a design-specific performance test for a sub-circuit or functional portion of an IC design; (Claim 6) A bottleneck performance measurement is identified if the actual peak rate value does not meet the theoretical peak rate value).
Regarding claim 10, Yang teaches the method as recited in claim 1, wherein the selecting the modification comprises: selecting a modification that impacts a process activity of the circuit design, if the process activity meets a threshold (Claim 14, “the processor configured to identify a bottleneck performance measurement if the actual pack rate value does not meet the theoretical peak rate value”. A peak rate value is computed for each performance measurement, ([0015]-[0017]) where the performance measurement can be for example the execution time relating to a design-specific performance test for a sub-circuit or functional portion of an IC design).
Regarding claims 12 and 17, Yang teaches a system, comprising: a processor; and a memory having instructions stored thereon which, when executed on the processor, performs operations comprising: identifying simulation activity for an integrated circuit (IC) design (Claim 1, running, by using a processor, a register transfer level (RTL) simulation using performance tests to generate actual performance results for a unit of an integrated circuit design; (Claim 17) Further, a computer readable non-transitory medium having instructions that are executed by a processing system to also run the RTL simulation and ([0045]) the methods may additionally be implemented on a computer-readable storage medium having a memory);
Yang specifically teach, “selecting a modification from multiple modifications, by one or more processors, if the simulation activity data exceeds one or more thresholds”, (see para 0025-0026, performance analysis module 415 calculates the theoretical peak rate, compares it with the measured data and analyzes the difference between them. This includes calculating a theoretical peak rate value (440). Yang also teaches “wherein the selected modification relates to one or more of improving the IC design, by one or more processors. (see 0027 “If the unit did not meet the desired or expected peak rate (448)….analyzing the starve/stall value for each unit (450), analyzing the latency information (452).
Wherein the selected modification relates to one or more improving the IC design or reducing resources needed to simulate the IC design (see para 0032, the automated verification system ..may save 1-3 personnel on the verification work for each project, on para 0033, Yang discloses “Examples of performance pass rule 600 implemented as the compare actual peak rate with theory one 444 and pass 446 as part of the performance evaluation module and pass blocks).
Regarding claims 13 and 14, computer readable medium, having similar limitations of claim 3 and 3 respectively. Thus, claims 13 are 14are rejected under the similar rationale as cited in the rejection of claims 2 and 3.
Claim 18 contains similar subject matter as in claim 2, therefore is rejected in the similar manner.
Claim 19 contains similar subject matter as in claim 3, therefore is rejected in the similar manner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US PGPub 20140181768) (hereinafter “Yang”) in view of Wang et al. (US PGPub 20030023941) (hereinafter “Wang”).
Regarding claims 11, Yang teaches the method as recited in claim 1. Yang does not specifically teach, however Wang teach identifying a line number in a the hardware descriptive language HDL design file of the circuit design corresponding to the selected modifications; (The modified HDL file of Figure 10(A) shows the improvement placed at a line number within the file). Wang also teaches inserting a comment into the HDL design file at the line number, wherein the comment describes the selected modification (The HDL file of Figure 10(A) includes comments, for example, "Modified by rtlscan clock to fix clock to data input", which is inserted at the location of the improved line of HDL).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to add that an HDL design file corresponding to the IC design is modified to indicate the one or more potential improvements to the simulation, as conceptually seen from the teaching of Wang, into that of Yang. Motivation to do so would have been to allow for the RTL design of the integrated circuit to be compatible with scan-based design-for-test techniques which are aimed at improving the testability of the design (Wang, [0005] and [0118]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to add that modifying the design file comprises identifying the HDL design file corresponding to a first potential improvement to the simulation, identifying a line number corresponding to the first potential improvement, and inserting a comment at the line number that describes the first potential improvement, as conceptually seen from the teaching of Wang, into that of Yang. Motivation to do so would have been to track the changes made to the design files, such that it provides an easy way for a designer to review the modifications as needed.
Claims 4 and 5 are rejected under 35 USC 103 as being unpatentable over Yang in view of Yousuf et al (US 6128757).
Regarding claim 4, Yang teaches the method as recited in claim 1. Yang does not specifically teach, however Yousuf teaches further comprising populating intermediate databases based on the simulation activity data; generating a skeleton databases ….;and generating a design record based on the intermediate databases…; generating a design record based on the skeleton database; wherein the extracting comprises extracting the activity from the design record. (Col 4, lines 1-10, The net list, multiple design libraries of data, and simulation data for an integrated circuit design each may include files, and as a whole the net list, design libraries, and the simulation data may each be considered an intermediate database. The skeleton database may be considered as the combination of the net list, design library, and simulation data databases, where this combination is then used to generate the design database, which may also be considered a design record).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to add that generating the design record using the plurality of intermediate databases comprises generating a skeleton database using the intermediate databases and generating the design record using the skeleton database, as conceptually seen from the teaching of Yousuf, into that of Yang. Motivation to do so would have been to provide a central location where simulation data and other pertinent information can be easily accessed by the performance evaluation module.
Regarding claim 5, Yang teaches method of claim 1 further comprising identifying a scope record reflecting simulation activity for the HDL scope relating to IC design, wherein the selecting the modification comprises selecting the modification based on the scope record (Claim 9 and [0016], A processor is configured to generate design feature-specific performance tests, that could be for a sub-circuit of an integrated circuit design, and use the performance tests to generate actual simulation performance results; (Claims 11 and 12) The processor is configured to identify performance measurements from the actual performance results, where the performance measurements include at least one of throughput, execution time, register settings, starve/stall values, workload balance values and latency values; (Claim 9, [0016] and [0041]-[0045]) Additionally the processor that generates that design-specific performance tests that could be for a sub-circuit of an integrated circuit design may be manufactured with HDL instructions to implement the embodiments, thus also having a HDL scope relating to the integrated circuit design).
Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Wang , and further in view of Lepak et al. (US PGPub 20120017188) (hereinafter “Lepak”).
Regarding claim 6, Yang teaches the method as recited in claim 5. Neither Yang nor Wang specifically teach, however Lepak teaches wherein the scope record comprises a signal record identifying simulation activity for a signal in the IC design, and wherein selecting the modification based on the signal record ([0022]-[0030] and Figure 2, A RTL simulation is run, where the activity of a set of signals is monitored and a weight factor, relating to the power consumed by the signal, is determined for each signal and if the accuracy of the determined weight factor is not within a predetermined threshold, then more signals may be added to the set to attempt to increase the accuracy and the simulation may be performed again).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to add that the scope record comprises a signal record identifying simulation activity for a signal in the IC design, and analyzing the signal record to generate the one or more potential improvements, as conceptually seen from the teaching of Lepak, into that of Yang. Motivation to do so would have been to optimize the performance of the integrated circuit design by accurately determining the power consumed by all or part of the design (Lepak, [0004] and [0021]).
Allowable Subject matter
Claims 8, 9, 15,16 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
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/KAMINI S SHAH/Supervisory Patent Examiner, Art Unit 2115