Prosecution Insights
Prosecution Insights
Technology areas: Computing & Software • Semiconductors, Circuits & Optics
21 pending office actions • 11 art units • 20 examiners • 0 of 21 (0%) have an AI response strategy ready • 139 patents granted in the last 365 days
Synopsys Inc. currently manages 19 pending office actions within the Computing & Software technology area. This portfolio is distributed across 18 distinct examiners, which means that nearly every pending action is handled by a different individual. The presence of 9 distinct art units suggests that the company's intellectual property spans various technical niches within the broader software sector. Practitioners must prepare for a variety of procedural styles given the ratio of 18 examiners to 19 pending matters.
JUAN CARLOS OCHOA is identified as the busiest examiner for this portfolio, currently handling 2 pending actions. Because 18 distinct examiners are involved in the 19 total office actions, the workload is handled by many different individuals. This distribution requires legal teams to adapt to many different examination styles rather than focusing on a few key personnel. The 9 distinct art units involved indicate that the work is not concentrated in one area, necessitating an understanding of various practices within the Computing & Software field to resolve the 2 pending actions of the busiest examiner.
Based on the USPTO statutory response window for each pending office action. 1 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §101 only | 2 (10%) |
| §101 + other | 4 (19%) |
| §103 only | 3 (14%) |
| §102 only | 3 (14%) |
| §112 only | 1 (5%) |
| Double-patenting only | 1 (5%) |
| Multi-statute (no §101) | 5 (24%) |
| No statute on record | 2 (10%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| OCHOA, JUAN CARLOS | 2 | 67.3% | +22.1% |
| ZHANG, HAIDONG | 1 | 81.1% | +12.5% |
| ZHANG, LESHUI | 1 | 77.9% | +35.3% |
| CHERY, MARDOCHEE | 1 | 88.5% | +10.3% |
| PARIHAR, SUCHIN | 1 | 87.8% | +8.9% |
| ALAWDI, ANWER AHMED | 1 | 75.0% | +16.7% |
| SHAMSUZZAMAN, MOHAMMED | 1 | 81.1% | +54.9% |
| MILLER, DANIEL E | 1 | 40.0% | +38.1% |
| TECHANE, MUNA A | 1 | 93.5% | +6.6% |
| AISAKA, BRYCE M | 1 | 87.4% | +10.5% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 19212337 | DISTRIBUTED TEST PATTERN GENERATION AND SYNCHRONIZATION | ZHANG, HAIDONG | — |
| 18510037 | Pointer Information Encoded in Increment Signals | TECHANE, MUNA A | — |
| 18560283 | METAL-INSULATOR-METAL CAPACITOR INSERTION | AISAKA, BRYCE M | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 8 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18941768 | AUTOMATED TRANSLATION OF DESIGN SPECIFICATIONS OF ELECTRONIC CIRCUITS | ZHANG, LESHUI | — |
| 18590646 | POWER PERFORMANCE AREA OPTIMIZATION IN DESIGN TECHNOLOGY CO-OPTIMIZATION FLOWS | PARIHAR, SUCHIN | — |
| 18415501 | ADAPTIVE AND INCREMENTAL CIRCUIT DESIGN IMPLEMENTATION | ALAWDI, ANWER AHMED | — |
| 18415288 | ONE-TIME PROGRAMMABLE BITCELL WITH A FUSE FIELD-EFFECT TRANSISTOR | SHAMSUZZAMAN, MOHAMMED | — |
| 18406476 | HIGH PERFORMANCE MONTE CARLO CIRCUIT SIMULATION | MILLER, DANIEL E | — |
| 18499021 | METRICS FOR INSTANCE RANKING FOR CLASSIFICATION AND REGRESSION | HOUNTON, AWADAGBE GERARD | — |
| 18141251 | ADJUSTMENTS TO SUPERCONDUCTING ELECTRONIC CIRCUIT DESIGNS USING PASSIVE TRANSMISSION LINE MODELING | KIM, EUNHEE | — |
| 18303800 | PEFORMANCE ANALYSIS USING ARCHITECTURE MODEL OF PROCESSOR ARCHITECTURE DESIGN | HOPKINS, DAVID ANDREW | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 8 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 17748987 | PARALLEL AND SCALABLE COMPUTATION OF STRONGLY CONNECTED COMPONENTS IN A CIRCUIT DESIGN | OCHOA, JUAN CARLOS | 15d |
| 19212337 | DISTRIBUTED TEST PATTERN GENERATION AND SYNCHRONIZATION | ZHANG, HAIDONG | — |
| 18941768 | AUTOMATED TRANSLATION OF DESIGN SPECIFICATIONS OF ELECTRONIC CIRCUITS | ZHANG, LESHUI | — |
| 18745454 | VIRTUAL MACHINE EXECUTION WITH HETEROGENOUS HOST AND VIRTUAL MACHINE INSTRUCTION SET ARCHITECTURES | CHERY, MARDOCHEE | — |
| 18415501 | ADAPTIVE AND INCREMENTAL CIRCUIT DESIGN IMPLEMENTATION | ALAWDI, ANWER AHMED | — |
| 18415288 | ONE-TIME PROGRAMMABLE BITCELL WITH A FUSE FIELD-EFFECT TRANSISTOR | SHAMSUZZAMAN, MOHAMMED | — |
| 18406476 | HIGH PERFORMANCE MONTE CARLO CIRCUIT SIMULATION | MILLER, DANIEL E | — |
| 18560283 | METAL-INSULATOR-METAL CAPACITOR INSERTION | AISAKA, BRYCE M | — |
| Art Unit | Apps |
|---|---|
| 2858 | 1 |
| 2133 | 1 |
| 2897 | 1 |
| 2827 | 1 |
| 2126 | 1 |
| 4100 | 1 |
| 2189 | 1 |
| 2818 | 1 |
| 2100 | 1 |
| 2186 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 19212337 | DISTRIBUTED TEST PATTERN GENERATION AND SYNCHRONIZATION | ZHANG, HAIDONG | 2858 | DP | Non-Final OA | — | Pending | May 19, 2025 |
| 18941768 | AUTOMATED TRANSLATION OF DESIGN SPECIFICATIONS OF ELECTRONIC CIRCUITS | ZHANG, LESHUI | — | §103§112 | Non-Final OA | — | Pending | Nov 08, 2024 |
| 18745454 | VIRTUAL MACHINE EXECUTION WITH HETEROGENOUS HOST AND VIRTUAL MACHINE INSTRUCTION SET ARCHITECTURES | CHERY, MARDOCHEE | 2133 | — | Non-Final OA | — | Pending | Jun 17, 2024 |
| 18590646 | POWER PERFORMANCE AREA OPTIMIZATION IN DESIGN TECHNOLOGY CO-OPTIMIZATION FLOWS | PARIHAR, SUCHIN | — | §102§103 | Non-Final OA | — | Pending | Feb 28, 2024 |
| 18415501 | ADAPTIVE AND INCREMENTAL CIRCUIT DESIGN IMPLEMENTATION | ALAWDI, ANWER AHMED | — | §102§103 | Non-Final OA | — | Pending | Jan 17, 2024 |
| 18415288 | ONE-TIME PROGRAMMABLE BITCELL WITH A FUSE FIELD-EFFECT TRANSISTOR | SHAMSUZZAMAN, MOHAMMED | 2897 | §103§112 | Final Rejection | — | Pending | Jan 17, 2024 |
| 18406476 | HIGH PERFORMANCE MONTE CARLO CIRCUIT SIMULATION | MILLER, DANIEL E | — | §102§103§112 | Non-Final OA | — | Pending | Jan 08, 2024 |
| 18510037 | Pointer Information Encoded in Increment Signals | TECHANE, MUNA A | 2827 | §102Other | Final Rejection | — | Pending | Nov 15, 2023 |
| 18560283 | METAL-INSULATOR-METAL CAPACITOR INSERTION | AISAKA, BRYCE M | — | §112 | Non-Final OA | — | Pending | Nov 10, 2023 |
| 18499021 | METRICS FOR INSTANCE RANKING FOR CLASSIFICATION AND REGRESSION | HOUNTON, AWADAGBE GERARD | 2126 | §101§102§103 | Non-Final OA | — | Pending | Oct 31, 2023 |
| 18383355 | INDEPENDENT EMULATION OF SEPARATE PORTIONS OF INTEGRATED CIRCUIT DESIGN | ALAM, MOHAMMED | — | §102 | Non-Final OA | — | Pending | Oct 24, 2023 |
| 18476302 | Custom Layout Recommendation Using Machine Learning | SOUNDRANAYAGAM, RAYAPPU NMN | — | §102 | Non-Final OA | — | Pending | Sep 27, 2023 |
| 18141251 | ADJUSTMENTS TO SUPERCONDUCTING ELECTRONIC CIRCUIT DESIGNS USING PASSIVE TRANSMISSION LINE MODELING | KIM, EUNHEE | — | §101§103§112 | Non-Final OA | — | Pending | Apr 28, 2023 |
| 18303800 | PEFORMANCE ANALYSIS USING ARCHITECTURE MODEL OF PROCESSOR ARCHITECTURE DESIGN | HOPKINS, DAVID ANDREW | — | §101§102§103§112 | Non-Final OA | — | Pending | Apr 20, 2023 |
| 18127376 | DYNAMIC CONTROL OF CIRCUIT DESIGN EMULATION | OCHOA, JUAN CARLOS | — | §103 | Non-Final OA | — | Pending | Mar 28, 2023 |
| 18114933 | MACHINE-LEARNING BASED ANOMALY DETECTION SYSTEM FOR VARIOUS PROTOCOL BUS TRANSACTIONS | MORRIS, JOSEPH PATRICK | 4100 | §101§103§112 | Non-Final OA | — | Pending | Feb 27, 2023 |
| 18102371 | FAST WAVEFORM CAPTURE WITH LOW HARDWARE FOOTPRINT ENABLING FULL VISIBILITY | GEBRESILASSIE, KIBROM K | 2189 | §101 | Non-Final OA | — | Pending | Jan 27, 2023 |
| 17870662 | INPUT/OUTPUT DEVICES THAT ARE COMPATIBLE WITH GATE-ALL-AROUND TECHNOLOGY | SIPLING, KENNETH MARK | 2818 | §103 | Final Rejection | — | Pending | Jul 21, 2022 |
| 17831380 | MACHINE LEARNING MODELS FOR PREDICTING DETAILED ROUTING TOPOLOGY AND TRACK USAGE FOR ACCURATE RESISTANCE AND CAPACITANCE ESTIMATION FOR ELECTRONIC CIRCUIT DESIGNS | MOLL, NITHYA JANAKIRAMAN | 2100 | §101 | Final Rejection | — | Pending | Jun 02, 2022 |
| 17748987 | PARALLEL AND SCALABLE COMPUTATION OF STRONGLY CONNECTED COMPONENTS IN A CIRCUIT DESIGN | OCHOA, JUAN CARLOS | 2186 | — | Non-Final OA | 15d | Pending | May 19, 2022 |
| 17332861 | Engineering Change Order Scenario Compression by Applying Hybrid of Live and Static Timing Views | LIN, ARIC | 2851 | §103 | Non-Final OA | — | Pending | May 27, 2021 |
IP Author helps IP teams respond to office actions faster with AI-generated responses, examiner analytics, and prosecution intelligence.
Start Free Trial