Prosecution Insights
Prosecution Insights
12 pending office actions • 8 art units • 12 examiners • 0 of 12 (0%) have an AI response strategy ready • 140 patents granted in the last 365 days
Based on the USPTO statutory response window for each pending office action. 12 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 12 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §101 only | 2 (17%) |
| §103 only | 9 (75%) |
| §102 only | 1 (8%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| SINHA, SNIGDHA | 1 | 50.0% | +58.3% |
| BLOOMQUIST, KEITH D | 1 | 62.9% | +19.6% |
| HINZE, LEO T | 1 | 52.9% | +10.5% |
| SOUNDRANAYAGAM, RAYAPPU NMN | 1 | — | — |
| AISAKA, BRYCE M | 1 | 87.4% | +10.3% |
| MEMULA, SURESH | 1 | 87.5% | -0.4% |
| LIN, ARIC | 1 | 60.0% | +12.9% |
| HAO, YI | 1 | 34.9% | +43.8% |
| OCHOA, JUAN CARLOS | 1 | 67.7% | +22.0% |
| TSENG, KYLE HWA-KAI | 1 | 55.6% | +66.7% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 1 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18137382 | CONSTANT, EQUAL, OR OPPOSITE REGISTERS OR PORTS DETECTION DURING LOGIC SYNTHESIS | AISAKA, BRYCE M | 16d overdue |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18523596 | INTERACTIVE VISUAL LOGFILE COMPARISON | BLOOMQUIST, KEITH D | 5d overdue |
| 18131795 | DETERMINING THE LOCATION OF SAFETY MECHANISM WITHIN A CIRCUIT DESIGN | MEMULA, SURESH | 16d |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 8 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18137382 | CONSTANT, EQUAL, OR OPPOSITE REGISTERS OR PORTS DETECTION DURING LOGIC SYNTHESIS | AISAKA, BRYCE M | 16d overdue |
| 18429377 | EXTENDED REALITY-BASED VISUALIZATION FOR INFORMATION TECHNOLOGY PLANNING AND INSTALLATION | SINHA, SNIGDHA | 9d overdue |
| 18523596 | INTERACTIVE VISUAL LOGFILE COMPARISON | BLOOMQUIST, KEITH D | 5d overdue |
| 18374898 | SYSTEM FOR AND METHOD OF DETERMINING CORROSION RISKS | HINZE, LEO T | 2d overdue |
| 17748987 | PARALLEL AND SCALABLE COMPUTATION OF STRONGLY CONNECTED COMPONENTS IN A CIRCUIT DESIGN | OCHOA, JUAN CARLOS | 15d |
| 17741335 | AUTOMATED METALENS DESIGN SYSTEM | TSENG, KYLE HWA-KAI | 29d |
| 18071396 | PROCESS TO RELAY KNOWLEDGE AND GUIDE SYNTHESIS ALONGSIDE EARLY DETECTION OF LOGIC OPTIMIZATIONS | LIN, ARIC | 56d |
| 17845403 | SYNCHRONIZING DISTRIBUTED SIMULATIONS OF A CIRCUIT DESIGN | HAO, YI | 72d |
| Art Unit | Apps |
|---|---|
| 2851 | 5 |
| 2619 | 1 |
| 2171 | 1 |
| 2853 | 1 |
| 2187 | 1 |
| 2186 | 1 |
| 2189 | 1 |
| 2115 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18429377 | EXTENDED REALITY-BASED VISUALIZATION FOR INFORMATION TECHNOLOGY PLANNING AND INSTALLATION | SINHA, SNIGDHA | 2619 | §103 | Non-Final OA | 9d overdue | Pending | Jan 31, 2024 |
| 18523596 | INTERACTIVE VISUAL LOGFILE COMPARISON | BLOOMQUIST, KEITH D | 2171 | §101 | Non-Final OA | 5d overdue | Pending | Nov 29, 2023 |
| 18374898 | SYSTEM FOR AND METHOD OF DETERMINING CORROSION RISKS | HINZE, LEO T | 2853 | §103 | Non-Final OA | 2d overdue | Pending | Sep 29, 2023 |
| 18139882 | CIRCUIT DESIGN ADJUSTMENTS USING REDUNDANT NODES | SOUNDRANAYAGAM, RAYAPPU NMN | 2851 | §102 | Non-Final OA | 16d | Pending | Apr 26, 2023 |
| 18137382 | CONSTANT, EQUAL, OR OPPOSITE REGISTERS OR PORTS DETECTION DURING LOGIC SYNTHESIS | AISAKA, BRYCE M | 2851 | §103 | Non-Final OA | 16d overdue | Pending | Apr 20, 2023 |
| 18131795 | DETERMINING THE LOCATION OF SAFETY MECHANISM WITHIN A CIRCUIT DESIGN | MEMULA, SURESH | 2851 | §101 | Non-Final OA | 16d | Pending | Apr 06, 2023 |
| 18071396 | PROCESS TO RELAY KNOWLEDGE AND GUIDE SYNTHESIS ALONGSIDE EARLY DETECTION OF LOGIC OPTIMIZATIONS | LIN, ARIC | 2851 | §103 | Final Rejection | 56d | Pending | Nov 29, 2022 |
| 17845403 | SYNCHRONIZING DISTRIBUTED SIMULATIONS OF A CIRCUIT DESIGN | HAO, YI | 2187 | §103 | Non-Final OA | 72d | Pending | Jun 21, 2022 |
| 17748987 | PARALLEL AND SCALABLE COMPUTATION OF STRONGLY CONNECTED COMPONENTS IN A CIRCUIT DESIGN | OCHOA, JUAN CARLOS | 2186 | §103 | Final Rejection | 15d | Pending | May 19, 2022 |
| 17741335 | AUTOMATED METALENS DESIGN SYSTEM | TSENG, KYLE HWA-KAI | 2189 | §103 | Final Rejection | 29d | Pending | May 10, 2022 |
| 17558952 | BOOLEAN METHODS FOR ENGINEERING CHANGE ORDER (ECO) PATCH IDENTIFICATION | ALAWDI, ANWER AHMED | 2851 | §103 | Final Rejection | 16d | Pending | Dec 22, 2021 |
| 17457187 | IDENTIFYING POTENTIAL IMPROVEMENT OPPORTUNITIES FOR SIMULATION PERFORMANCE OF AN INTEGRATED CIRCUIT DESIGN | SHAH, KAMINI S | 2115 | §103 | Final Rejection | 12d | Pending | Dec 01, 2021 |
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