DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/2/2026 has been entered.
Status of the Application
The Amendment filed on 2/2/2026, responding to the Office action mailed on 12/3/2025, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-20 are pending in this application.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show Claim 7 on page (3 printed on page) line 2 states, “…An interconnect structure comprising: one or more metal lines in direct contact with a top surface of one or more devices…” as described in the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
[0024] states: …when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present.
Figures 1-5 show liner 104 between the underneath device 102 and metal lines 106.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20210098423 A1) in view of Chen et al. (TW 202105611 A, ‘Chen2’ hereafter)
Re Claim 1 Chen teaches an interconnect structure (FIG. 1C) comprising:
one or more metal lines (203) [0027];
one or more top vias (209) [0028] in direct contact with a top surface of the one or more metal lines (203);
and a liner (DL) [0028] having a uniform thickness formed on sidewalls of the one or more top vias (209) and top portions of the one or more metal lines (203), wherein the thickness of the liner (DL) formed on the sidewalls of the one or more top vias (209) is less than a width of the one or more top vias (209).
Chen does not teach a width of the liner formed on the top portions of the one or more metal lines is equal to a width of the one or more metal lines.
Chen2 teaches a width of the liner (250, page 7 par 2) formed on the top portions of the one or more metal lines (231, page 10 last par) is equal to a width of the one or more metal lines (FIG. 2E).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Chen2 into the structure of Chen since Chen2 teaches an interconnect structure.
The ordinary artisan would have been motivated to modify Chen2 in combination with Chen in the above manner for the motivation of optimally integrating the liner with an ideal width to allow for a device to be manufactured that is as small as possible to integrate more integrated circuits to a single body. Page 2 par 4 states, “Advances in semiconductor materials and processing technology have resulted in a reduction in the overall size of integrated circuit components, while increasing the number or density of integrated circuit components on a single body.”
Re Claim 2 Chen in view of Chen2 teaches the interconnect structure of claim 1, wherein the liner (Chen, DL) is not in contact with the sidewalls of the one or more metal lines (203, FIG. 1C).
Re Claim 3 Chen in view of Chen2 teaches the interconnect structure of claim 1, wherein the metal line (Chen, 203) and the top via (209) are composed of a material selected from the group consisting of: ruthenium, cobalt, molybdenum, tungsten, aluminum ([0028] states 209 includes aluminum, [0027] says 203 is the same material as 103, and [0017] says 103 includes aluminum), and rhodium (Chen, FIG. 1C).
Re Claim 4 Chen in view of Chen2 teaches the interconnect structure of claim 1, wherein the liner (Chen, DL) comprises a material selected from the group consisting of: titanium, tungsten, and a dielectric material [0028].
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20210098423 A1) in view of Chen et al. (TW 202105611 A, ‘Chen2’ hereafter) as applied to claim 1 above, and further in view of Kim et al. (TW 202027224 A).
Re Claim 5 Chen in view of Chen2 teaches the interconnect structure of claim 1, but does not teach an ultra-low-k dielectric material in direct contact with the liner and sidewalls of the one or more metal lines.
Kim teaches an ultra-low-k dielectric material (28, page 5 par 4 & 14, page 4 par 3) in direct contact with the liner (24b, page 6 par 5) and sidewalls of the one or more metal lines (12b, page 4 par 3, FIG. 9).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Kim into the structure of Chen in view of Chen2 since Kim teaches an interconnect structure.
The ordinary artisan would have been motivated to modify Kim in combination with Chen in view of Chen2 in the above manner for the motivation of optimally integrating a dielectric around the via and metal lines to provide electrical insulation to the via and metal lines to allow the device to maintain optimal current levels.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20210098423 A1) in view of Chen et al. (TW 202105611 A, ‘Chen2’ hereafter) and Kim et al. (TW 202027224 A) as applied to claims 1 and 5 above, and further in view of Li et al. (CN 108573914 A).
Re Claim 6 Chen in view of Chen2 and Kim teaches the interconnect structure of claim 5, but does not teach one or more air gaps in the ultra-low-k dielectric material positioned between the one or more metal lines.
Li teaches one or more air gaps (201, FIG. 2B) in the ultra-low-k dielectric material (201) positioned between the one or more metal lines (202, page 7 par 1 and page 7 par 6 states, “In order to have low dielectric constant, porosity can be formed is at least 20% of the ultra low-K dielectric layer 201. also can form the ultra low-K dielectric layer with an air gap 201.”)
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Li into the structure of Chen in view of Chen2 and Kim since Li teaches an interconnect structure.
The ordinary artisan would have been motivated to modify Li in combination with Chen in view of Chen2 and Kim in the above manner for the motivation of integrating a high k dielectric material to the device with air gap to improve the delay performance of the device contact resistance. Page 2 par 4 states, “…wherein the interconnect structure formed in the dielectric layer, e.g., low K dielectric layer (Ultra low-k and ULK), the porogen because it has porous property, the K value is2.5 close, can improve the delay performance of the device contact resistance…”
Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20210098423 A1) in view of Ku (US 20200035908 A1) and Chen et al. (TW 202105611 A, ‘Chen2’ hereafter) and Kim et al. (TW 202027224 A).
Re Claim 7 Chen teaches an interconnect structure (FIG. 1C) comprising:
one or more metal lines (203) [0027] in contact (parts are in same chip and therefore in mechanical contact) with a top surface of one or more devices (101) [0014];
one or more top vias (209) [0028] in direct contact with a top surface of the one or more metal lines (203);
a liner (DL) [0028] having a uniform thickness formed on sidewalls of the one or more top vias (209) and top surfaces of the one or more metal lines (203), wherein the thickness of the liner (DL) formed on the sidewalls of the one or more top vias (209) is less than a width of the one or more top vias (209).
Chen does not teach the one or more metal lines in direct contact with a top surface of one or more devices;
an ultra-low-k dielectric material in direct contact with the sidewalls of the one or more metal lines, and the top surface of the one or more devices.
Ku teaches the one or more metal lines (107L) [0030] in direct contact with a top surface of one or more devices (103) [0017];
an ultra-low-k dielectric material (206a) [0060] in direct contact with the sidewalls of the one or more metal lines (107L), and the top surface of the one or more devices (103, FIG. 2A).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Ku into the structure of Chen since Ku teaches an interconnect structure.
The ordinary artisan would have been motivated to modify Ku in combination with Chen in the above manner for the motivation of optimally integrating the metal lines and device with a dielectric layer to optimize device storage capabilities. [0002] states, “Many modern day electronic devices contain electronic memory configured to store data. Electronic memory may be volatile memory or non-volatile memory. Volatile memory stores data while it is powered, while non-volatile memory is able to store data when power is removed. Magnetic random-access memory (MRAM) devices are one promising candidate for a next generation non-volatile memory technology.”
Chen in view of Ku does not teach a width of the liner formed on the top portions of the one or more metal lines is equal to a width of the one or more metal lines.
Chen2 teaches a width of the liner (250, page 7 par 2) formed on the top portions of the one or more metal lines (231, page 7 par 1) is equal to a width of the one or more metal lines (231, FIG. 2E).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Chen2 into the structure of Chen in view of Ku since Chen2 teaches an interconnect structure.
The ordinary artisan would have been motivated to modify Chen2 in combination with Chen in view of Ku in the above manner for the motivation of optimally integrating the metal lines to allow for optimal interconnections in the internal device and outside the device. Page 2 par 3 states, “Interconnects provide electrical connections between various electronic components of an integrated circuit, and form connections between these circuit components and external contact components (such as pins) of the device for connecting This integrated circuit is connected to other circuits.”
Chen in view of Ku and Chen2 does not teach the ultra-low-k dielectric material in direct contact with the liner.
Kim teaches the ultra-low-k dielectric material (28, page 5 par 4 & 14, page 4 par 3) in direct contact with the liner (24b, page 6 par 5, FIG. 9).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Kim into the structure of Chen in view of Ku and Chen2 since Kim teaches an interconnect structure.
The ordinary artisan would have been motivated to modify Kim in combination with Chen in view of Ku and Chen2 in the above manner for the motivation of optimally integrating a dielectric around the via liner to provide electrical insulation to allow the device to maintain optimal current levels.
Re Claim 8 Chen in view of Ku and Chen2 and Kim teaches the interconnect structure of claim 7, wherein the liner (Chen, DL) is not in contact with the sidewalls of the one or more metal lines (203, FIG. 1A).
Re Claim 9 Chen in view of Ku and Chen2 and Kim teaches the interconnect structure of claim 7, wherein the metal line (Chen, 203) and the top via (209) are composed of a material selected from the group consisting of: ruthenium, cobalt, molybdenum, tungsten, aluminum, and rhodium ([0028] states 209 includes aluminum, [0027] says 203 is the same material as 103, and [0017] says 103 includes aluminum, FIG. 1C)
Re Claim 10 Chen in view of Ku and Chen2 and Kim teaches the interconnect structure of claim 7, wherein the liner (Chen, DL) is composed of a material selected from the group consisting of: titanium, tungsten, and a dielectric material [0028].
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20210098423 A1) in view of Ku (US 20200035908 A1) and Chen et al. (TW 202105611 A, ‘Chen2’ hereafter) and Kim et al. (TW 202027224 A) as applied to claim 7 above, and further in view of Li et al. (CN 108573914 A).
Re Claim 11 Chen in view of Ku and Chen2 and Kim teaches the interconnect structure of claim 7, but does not teach one or more air gaps in the ultra-low-k dielectric material positioned between the one or more metal lines.
Li teaches one or more air gaps (201, FIG. 2B) in the ultra-low-k dielectric material (201) positioned between the one or more metal lines (202, page 7 par 1 and page 7 par 6 states, “In order to have low dielectric constant, porosity can be formed is at least 20% of the ultra low-K dielectric layer 201. also can form the ultra low-K dielectric layer with an air gap 201.”)
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Li into the structure of Chen in view of Ku and Chen2 and Kim since Li teaches an interconnect structure.
The ordinary artisan would have been motivated to modify Li in combination with Chen in view of Ku and Chen2 and Kim in the above manner for the motivation of integrating a high k dielectric material to the device with air gap to improve the delay performance of the device contact resistance. Page 2 par 4 states, “…wherein the interconnect structure formed in the dielectric layer, e.g., low K dielectric layer (Ultra low-k and ULK), the porogen because it has porous property, the K value is2.5 close, can improve the delay performance of the device contact resistance…”
Response to Arguments
Applicant’s arguments with respect to claims 1-11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 6/23/26
Prosecution Insights