DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claims 1, 9, and 14 recite “grinding means” which is being interpreted under 112(f) because (A) it recites the term “means”, (B) “grinding” designates a function performed by the means, and (C) no additional structure is specified to support the claimed function of “moving.” Examiner is interpreting “grinding means” to be grindstones based on the discussion of “grinding means” in at least paragraph 0018 of Applicant’s specification.
Claims 1, 9, and 14 recite “laser applying means” which is being interpreted under 112(f) because (A) it recites the term “means”, (B) “laser applying” designates a function performed by the means, and (C) no additional structure is specified to support the claimed function of “laser applying.” Examiner is interpreting “laser applying means” to be a combination of a laser oscillator and beam condenser based on the discussion of “laser applying means” in at least paragraph 0022 of Applicant’s specification.
Claims 1, 9, and 14 recite “belt conveyor unit” which is being interpreted under 112(f) because (A) the term “unit” is a generic placeholder, see above; (B) “delivering” designates a function performed by the unit, and (C) no additional structure is specified to support the claimed function of “delivering.” Examiner is interpreting “belt conveyor unit” to be at least a plurality of forward belt conveyors based on the discussion of “belt conveyor unit” with in at least paragraph 0035 of Applicant’s specification.
Claims 1, 9, and 14 recite “wafer peeling means” which is being interpreted under 112(f) because (A) it recites the term “means”, (B) “wafer peeling” designates a function performed by the means, and (C) no additional structure is specified to support the claimed function of “wafer peeling.” Examiner is interpreting “wafer peeling means” to be a system including a liquid tank with a liquid inside of the tank and a suction member for holding and vertically moving the ingot under suction based on the discussion of “wafer peeling means” in at least paragraphs 0029 and 0031 of Applicant’s specification.
Claims 2, 5, and 15-16 recite “wafer image capturing means” which is being interpreted under 112(f) because (A) it recites the term “means”, (B) “wafer image capturing” designates a function performed by the means, and (C) no additional structure is specified to support the claimed function of “wafer image capturing.” Examiner is interpreting “wafer image capturing means” to be “a line sensor having a linear array of image capturing elements” based on the discussion of “image capturing means” with regards to the wafer in at least paragraph 0067 of Applicant’s specification.
Claims 3-4 and 10-11 recite “ingot image capturing means” which is being interpreted under 112(f) because (A) it recites the term “means”, (B) “ingot image capturing” designates a function performed by the means, and (C) no additional structure is specified to support the claimed function of “ingot image capturing.” Examiner is interpreting “ingot image capturing means” to be “a line sensor having a linear array of image capturing elements” based on the discussion of “image capturing means” with regards to the ingot in at least paragraph 0062 of Applicant’s specification.
Claims 2 and 15 recite “wafer defect detecting means” which is being interpreted under 112(f) because (A) it recites the term “means”, (B) “wafer defect detecting” designates a function performed by the means, and (C) no additional structure is specified to support the claimed function of “wafer defect detecting.” Examiner is interpreting “wafer defect detecting means” to be a generic computer program based on the discussion of “wafer defect detecting means” in at least paragraph 0064 and 0068 of Applicant’s specification.
Claims 3 and 10 recite “ingot defect detecting means” which is being interpreted under 112(f) because (A) it recites the term “means”, (B) “ingot defect detecting” designates a function performed by the means, and (C) no additional structure is specified to support the claimed function of “ingot defect detecting.” Examiner is interpreting “ingot defect detecting means” to be a generic computer program based on the discussion of “ingot defect detecting means” with regards to the ingot in at least paragraph 0064 of Applicant’s specification.
Claims 1, 9, and 18-19 recite “ingot quality inspecting unit” which is being interpreted under 112(f) because (A) the term “unit” is a generic placeholder, see above; (B) “ingot quality inspecting” designates a function performed by the unit, and (C) no additional structure is specified to support the claimed function of “ingot quality inspecting.” Examiner is interpreting “ingot quality inspecting unit” to be at least an illuminating device, an image capturing means, and an ingot defect detecting means based on the discussion of “ingot quality inspecting unit” with in at least paragraph 0061 of Applicant’s specification.
Claims 1, 14, and 18 recite “wafer quality inspecting unit” which is being interpreted under 112(f) because (A) the term “unit” is a generic placeholder, see above; (B) “wafer quality inspecting” designates a function performed by the unit, and (C) no additional structure is specified to support the claimed function of “wafer quality inspecting.” Examiner is interpreting “wafer quality inspecting unit” to be at least an illuminating device, an image capturing means, and a wafer defect detecting means based on the discussion of “wafer quality inspecting unit” with in at least paragraph 0066 of Applicant’s specification.
This application includes one or more claim limitations that use the word “means” or “step” or a generic placeholder but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation(s) is/are:
“ingot grinding unit” in claims 1, 9, 14, and 18-19.
“laser applying unit” in claims 1, 9, and 14.
“wafer peeling unit” in claims 1, 8-9, 13-14, and 18.
“belt conveyor unit” in claims 1, 9, and 14.
“quality inspecting unit” in claims 1, 9, and 14.
“wafer quality inspecting unit” in claims 2 and 15.
“ingot quality inspecting unit” in claims 3 and 10.
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Iizuka et al. (US20190181024), hereinafter Iizuka, in view of Hirata et al. (US20180254223), hereinafter Hirata, as evidenced by Akiyama (JP2004279353), attached as a PDF, and in further view of Ito et al. (US20160098828), hereinafter Ito.
Regarding claim 1, Iizuka discloses a wafer manufacturing apparatus (Fig. 1 element 2) for manufacturing a wafer (Abstract) from a semiconductor ingot (Fig. 3 element 170), comprising: an ingot grinding unit (Fig. 2 element 4) including a first holding table (Fig. 2 element 14) for holding the semiconductor ingot thereon (0044) and grinding means (Fig. 3 element 16 meets the generic term of grinding means and also includes grindstones (Fig. 3 elements 44)) for grinding an upper surface of the semiconductor ingot held on the first holding table to planarize the upper surface of the semiconductor ingot (0045); a laser applying unit (Fig. 4 element 6) including a second holding table (Fig. 4 element 60) for holding the semiconductor ingot thereon (0046) and laser applying means (Fig. 5 element 62 meets the generic term of laser applying means and also includes a laser oscillator (Fig. 5 element 72) and a laser condenser (Fig. 5 element 74)) for applying a laser beam (Fig. 6 element LB) having a wavelength transmittable through the semiconductor ingot while positioning a focused spot of the laser beam at a depth in the ingot (0046), the depth corresponding to a thickness of the wafer to be produced from the semiconductor ingot, from the upper surface of the semiconductor ingot held on the second holding table, thereby forming peel-off layers in the semiconductor ingot (0046); a wafer peeling unit (Fig. 6 element 8) including a third holding table (Fig. 6 element 80) for holding the semiconductor ingot thereon (0051) and wafer peeling means (Fig. element 82 meets the generic term of wafer peeling means and also includes a liquid tank (Fig. 7 element 94) with a liquid (Fig. 7 element 106) inside of the tank and a suction member (Fig. 7 element 112)) for holding the upper surface of the semiconductor ingot held on the third holding table and peeling an ingot portion as the wafer from the ingot at the peel-off layers (0051 and 0053-0054); a tray (Fig. 8 element 9) including an ingot support portion (Fig. 8 element 117) for supporting the semiconductor ingot (0055) and a wafer support portion (Fig. 8 element 118) for supporting the wafer that has been peeled off from the semiconductor ingot (0055); a belt conveyor unit (Fig. 1 element 10) for delivering the semiconductor ingot supported on the tray between the ingot grinding unit, the laser applying unit, and the wafer peeling unit (Fig. 1, 0065).
Iizuka fails to disclose a quality inspecting unit disposed adjacent to the belt conveyor unit; wherein the quality inspecting unit comprises: an ingot quality inspecting unit that is configured to inspect the quality of the semiconductor ingot, while the semiconductor ingot is supported on the ingot support portion of the tray and the tray is supported by the belt conveyor unit, to determine if the upper surface of the ingot has defects that tend to disturb the laser beam, after the upper surface of the semiconductor ingot has been ground by the ingot grinding unit, but before the peel-off layers have been formed in the semiconductor ingot by the laser applying unit; and a wafer quality inspecting unit that is configured to inspect the quality of an upper surface of the wafer after the wafer has been peeled-off from the ingot by the wafer peeling unit, wherein the upper surface of the semiconductor ingot inspected by the ingot quality inspecting unit is the same surface as the upper surface of the wafer inspected by the wafer quality inspecting unit.
Hirata is also concerned with a quality inspecting unit and teaches a quality inspecting unit (Fig. 8 element 55) disposed adjacent to the belt conveyor unit (Fig. 1 element 12), wherein the quality inspecting unit comprises: an ingot quality inspecting unit (Fig. 8 element 55, where the ingot quality inspecting unit is a subset of the quality inspecting unit which encompasses the entirety of the quality inspecting unit) that is configured to inspect the quality of the semiconductor ingot, while the semiconductor ingot is supported on the ingot support portion of the tray (Figs. 1 and 4 element 26 corresponds to a tray and the portion of the tray which the ingot (11) is positioned on corresponds to the ingot support portion of the tray) and the tray is supported by the belt conveyor unit (Fig. 1, 0068), to determine if the upper surface of the ingot has defects that tend to disturb the laser beam (0064-0066, where asperities correspond to defects that tend to disturb the laser beam), after the upper surface of the semiconductor ingot has been ground by the ingot grinding unit, but before the peel-off layers have been formed in the semiconductor ingot by the laser applying unit (Fig. 1, 0068, where the ingot quality inspecting unit is configured to (e.g. capable of) inspect the quality of the semiconductor ingot after the upper surface of the semiconductor ingot has been ground by the ingot grinding unit, but before the peel-off layers have been formed in the semiconductor ingot by the laser applying unit and the ingot quality inspecting unit because the ingot moves along a path between the ingot quality inspecting unit (55) and the area where the peel-off layers are formed (36), which means that the ingot can be moved back and forth between these two positions and that therefore, inspection of the ingot can be performed both before and after the peel-off layers have been formed). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify the wafer manufacturing apparatus of Iizuka to include a quality inspecting unit adjacent to the belt conveyor unit, that is configured to inspect the quality of the semiconductor ingot, while the semiconductor ingot is supported on the ingot support portion of the tray and the tray is supported by the belt conveyor unit, to determine if the upper surface of the ingot has defects that tend to disturb the laser beam, after the upper surface of the semiconductor ingot has been ground by the ingot grinding unit, but before the peel-off layers have been formed in the semiconductor ingot by the laser applying unit, as taught by Hirata, because it is known in the art that detecting asperities (e.g. defects) of an ingot can improve efficiency and productivity of a semiconductor wafer manufacturing process, as evidenced by Akiyama (see the last paragraph on page 4).
Iizuka, as modified, fails to disclose a wafer quality inspecting unit that is configured to inspect the quality of an upper surface of the wafer after the wafer has been peeled-off from the ingot by the wafer peeling unit, wherein the upper surface of the semiconductor ingot inspected by the ingot quality inspecting unit is the same surface as the upper surface of the wafer inspected by the wafer quality inspecting unit.
Ito is also concerned with a quality inspecting unit and teaches a wafer quality inspecting unit (Fig. 3A element 91) that is configured to inspect the quality of an upper surface of the wafer after the wafer has been peeled-off from the ingot by the wafer peeling unit (0038-0039 and 0049, where processed face corresponds to an upper surface of the wafer), the wafer quality inspecting unit (91) inspects individual wafers, which would mean that the wafers would have already had to have been peeled-off from the ingot by the wafer peeling unit). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify the wafer manufacturing apparatus of Iizuka, as modified, to include a wafer quality inspecting unit that is configured to inspect the quality of the wafer after the wafer has been peeled-off from the ingot by the wafer peeling unit, as taught by Ito, because Ito teaches that the wafer quality inspection unit can detect defects on the surface of the wafer (0049).
Modifying Iizuka, as modified, with the teachings of Ito, as described above, then yields the upper surface of the semiconductor ingot inspected by the ingot quality inspecting unit is the same surface as the upper surface of the wafer inspected by the wafer quality inspecting unit (since both the ingot quality inspecting unit and the wafer quality inspecting unit are a part of the same system and there is no teachings brought in that suggest flipping the wafer between the ingot quality inspecting unit and the wafer quality inspecting unit, this means that the upper surface of the semiconductor ingot inspected by the ingot quality inspecting unit is the same surface as the upper surface of the wafer inspected by the wafer quality inspecting unit).
Regarding claim 2, Iizuka, as modified discloses the limitations of claim 1, as described above, and further discloses the wafer quality inspecting unit includes a wafer illuminating device (Ito, 0038, where the portion of the wafer quality inspecting unit (91) which irradiates light corresponds to a wafer illuminating device), a wafer image capturing means (Ito, Fig. 3A element 92, 0038) for detecting reflected light reflected by an upper surface of the wafer that is illuminated by light emitted from the wafer illuminating device (Ito, Fig. 3A, 0038), and a wafer defect detecting means (Ito, Fig. 3A elements 93, 94, and 95, 0050) for processing an image captured by the wafer image capturing means and detecting a defect from the processed image (Ito, 0039 and 0049-0050).
Regarding claim 3, Iizuka, as modified discloses the limitations of claim 1, as described above, and further discloses the ingot quality inspecting unit includes an ingot illuminating device (Hirata, Fig. 8 element 58), an ingot image capturing means (Hirata, Fig. 8 element 60) for detecting reflected light reflected by an upper surface of the semiconductor ingot (Hirata, Fig. 8 element 11a) that is illuminated by light emitted from the ingot illuminating device (Hirata, 0065), and an ingot defect detecting means (Hirata, Fig. 8 element 62) for processing an image captured by the ingot image capturing means and detecting a defect from the processed image (Hirata, 0072-0074 and 0077, where asperities corresponds to defect).
Regarding claim 4, Iizuka, as modified discloses the limitations of claim 1, as described above, and further discloses the ingot illuminating device and the ingot image capturing means are both positioned above the upper surface of the semiconductor ingot (Hirata, Fig. 8).
Regarding claim 5, Iizuka, as modified discloses the limitations of claim 2, as described above, and further discloses the wafer illuminating device and the wafer image capturing means are both positioned above the upper surface of the wafer (Ito, Fig. 3A, 0038).
Regarding claim 6, Iizuka, as modified discloses the limitations of claim 2, as described above, and further discloses the defect being detected includes cracks in the upper surface of the wafer (Ito, 0012 and 0050, where cracks are included in the "and so forth" in paragraph 0050).
Regarding claim 7, Iizuka, as modified discloses the limitations of claim 3, as described above, and further discloses the defect being detected includes marks formed in the upper surface of the semiconductor ingot (Hirata, 0077, where asperities correspond to marks). Examiner notes that "marks" is a broad term which is being interpreted as any discontinuity on the surface condition on the upper surface of the semiconductor ingot.
Regarding claim 8, Iizuka, as modified discloses the limitations of claim 3, as described above, and further discloses the defect being detected includes marks formed in the upper surface of the semiconductor ingot upon peeling off of the wafer from the semiconductor ingot by the wafer peeling unit (Hirata, 0077, where asperities correspond to marks). Examiner notes that "marks" is a broad term which is being interpreted as any discontinuity on the surface condition on the upper surface of the semiconductor ingot.
Regarding the marks having been formed upon peeling off of the wafer from the semiconductor ingot by the wafer peeling unit, in accordance to MPEP 2113, the method of forming the device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given patentable weight. Please note that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product, i.e. an ingot with marks on the surface, does not depend on its method of production, i.e. peeling off a wafer from the ingot by the wafer peeling unit.
Regarding claim 18, Iizuka, as modified discloses the limitations of claim 1, as described above, but fails to disclose the ingot quality inspecting unit is positioned adjacent to the ingot grinding unit; and the wafer quality inspecting unit is positioned adjacent to the wafer peeling unit. Examiner notes that Applicant has not provided any criticality for the relative positioning of these elements in the specification. Iizuka, as modified, fails to disclose the ingot quality inspecting unit is positioned adjacent to the ingot grinding unit; and the wafer quality inspecting unit is positioned adjacent to the wafer peeling unit. However, it has been held that an “obvious to try” rationale when choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is a support for a conclusion of obviousness which is consistent with the proper "functional approach" to the determination of obviousness as laid down in Graham, if the following findings can be established: (1) a finding that at the time of the invention, there had been a recognized problem or need in the art, which may include a design need or market pressure to solve a problem; (2) a finding that there had been a finite number of identified, predictable potential solutions to the recognized need or problem; (3) a finding that one of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success; and (4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness. See MPEP § 2143(I)(E).
In the instant case, and as per (1), one of ordinary skill in the art would recognize that there is a need in the art to provide an ingot quality inspecting unit based at least on the teachings of Hirata (see at least paragraphs 0005-0009) and a wafer quality inspecting unit based at least on the teachings of Hyun (see at least paragraphs 0011-0015). As per (2), one of ordinary skill in the art would recognize that there is a finite number of identifiable, predictable potential solutions for the relative arrangement of the ingot quality inspecting unit and the wafer quality inspecting unit within the wafer manufacturing apparatus. As per (3), one of ordinary skill in the art would recognize that the particular positioning of the ingot quality inspecting unit, specifically having the ingot quality inspecting unit be adjacent to the ingot grinding unit, and the wafer quality inspecting unit, specifically having the wafer quality inspecting unit be adjacent to the wafer peeling unit, could have been pursued with a reasonable expectation of success, since said finite number of potential arrangements would have not yielded unpredictable results, nor would have rendered the prior art inoperable for its intended purpose. That is, the relative positioning of the ingot quality inspecting unit and the wafer quality inspecting unit would have still expectedly have resulted in a wafer manufacturing apparatus which inspects ingots, produces wafers, and inspects wafers. As per (4), based on the above analysis, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have taken the teachings of Iizuka, as modified, and to have modified them by positioning the ingot quality inspecting unit to be adjacent to the ingot grinding unit and positioning the wafer quality inspecting unit to be adjacent to the wafer peeling unit, as a matter of trying a set of obvious, finite and predictable solutions, in order to obtain the best structural arrangement of components that best suits a quality inspecting arrangement, without yielding unpredictable results.
Regarding claim 20, Iizuka, as modified discloses the limitations of claim 1, as described above, and further discloses the defects that tend to disturb the laser beam comprise marks on the upper surface of the ingot created when the wafer is peeled off from the ingot (Hirata, 0077, where asperities correspond to marks). Examiner notes that "marks" is a broad term which is being interpreted as any discontinuity on the surface condition on the upper surface of the semiconductor ingot.
Claims 9-13, 19, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Iizuka et al. (US20190181024), hereinafter Iizuka, in view of Hirata et al. (US20180254223), hereinafter Hirata, as evidenced by Akiyama (JP2004279353), attached as a PDF.
Regarding claim 9, Iizuka discloses a wafer manufacturing apparatus (Fig. 1 element 2) for manufacturing a wafer (Abstract) from a semiconductor ingot (Fig. 3 element 170), comprising: an ingot grinding unit (Fig. 2 element 4) including a first holding table (Fig. 2 element 14) for holding the semiconductor ingot thereon (0044) and grinding means (Fig. 3 element 16 meets the generic term of grinding means and also includes grindstones (Fig. 3 elements 44)) for grinding an upper surface of the semiconductor ingot held on the first holding table to planarize the upper surface of the semiconductor ingot (0045); a laser applying unit (Fig. 4 element 6) including a second holding table (Fig. 4 element 60) for holding the semiconductor ingot thereon (0046) and laser applying means (Fig. 5 element 62 meets the generic term of laser applying means and also includes a laser oscillator (Fig. 5 element 72) and a laser condenser (Fig. 5 element 74)) for applying a laser beam (Fig. 6 element LB) having a wavelength transmittable through the semiconductor ingot while positioning a focused spot of the laser beam at a depth in the ingot (0046), the depth corresponding to a thickness of the wafer to be produced from the semiconductor ingot, from the upper surface of the semiconductor ingot held on the second holding table, thereby forming peel-off layers in the semiconductor ingot (0046); a wafer peeling unit (Fig. 6 element 8) including a third holding table (Fig. 6 element 80) for holding the semiconductor ingot thereon (0051) and wafer peeling means (Fig. element 82 meets the generic term of wafer peeling means and also includes a liquid tank (Fig. 7 element 94) with a liquid (Fig. 7 element 106) inside of the tank and a suction member (Fig. 7 element 112)) for holding the upper surface of the semiconductor ingot held on the third holding table and peeling an ingot portion as the wafer from the ingot at the peel-off layers (0051 and 0053-0054); a tray (Fig. 8 element 9) including an ingot support portion (Fig. 8 element 117) for supporting the semiconductor ingot (0055) and a wafer support portion (Fig. 8 element 118) for supporting the wafer that has been peeled off from the semiconductor ingot (0055); a belt conveyor unit (Fig. 1 element 10) for delivering the semiconductor ingot supported on the tray between the ingot grinding unit, the laser applying unit, and the wafer peeling unit (Fig. 1, 0065).
Iizuka fails to disclose a quality inspecting unit disposed adjacent to the belt conveyor unit; wherein the quality inspecting unit comprises: an ingot quality inspecting unit that is configured to inspect the quality of the semiconductor ingot, while the semiconductor ingot is supported on the ingot support portion of the tray and the tray is supported by the belt conveyor unit, after the upper surface of the semiconductor ingot has been ground by the ingot grinding unit, but before the peel-off layers have been formed in the semiconductor ingot by the laser applying unit.
Hirata is also concerned with a quality inspecting unit and teaches a quality inspecting unit (Fig. 8 element 55) disposed adjacent to the belt conveyor unit (Fig. 1 element 12), wherein the quality inspecting unit comprises: an ingot quality inspecting unit (Fig. 8 element 55, where the ingot quality inspecting unit is a subset of the quality inspecting unit which encompasses the entirety of the quality inspecting unit) that is configured to inspect the quality of the semiconductor ingot, while the semiconductor ingot is supported on the ingot support portion of the tray (Figs. 1 and 4 element 26 corresponds to a tray and the portion of the tray which the ingot (11) is positioned on corresponds to the ingot support portion of the tray) and the tray is supported by the belt conveyor unit (Fig. 1, 0068), to determine if the upper surface of the ingot has defects that tend to disturb the laser beam (0064-0066, where asperities correspond to defects that tend to disturb the laser beam), after the upper surface of the semiconductor ingot has been ground by the ingot grinding unit, but before the peel-off layers have been formed in the semiconductor ingot by the laser applying unit (Fig. 1, 0068, the ingot quality inspecting unit is configured to(e.g. capable of) inspect the quality of the semiconductor ingot after the upper surface of the semiconductor ingot has been ground by the ingot grinding unit, but before the peel-off layers have been formed in the semiconductor ingot by the laser applying unit and the ingot quality inspecting unit because the ingot moves along a path between the ingot quality inspecting unit (55) and the area where the peel-off layers are formed (36), which means that the ingot can be moved back and forth between these two positions and that therefore, inspection of the ingot can be performed both before and after the peel-off layers have been formed). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify the wafer manufacturing apparatus of Iizuka to include a quality inspecting unit adjacent to the belt conveyor unit, that is configured to inspect the quality of the semiconductor ingot, while the semiconductor ingot is supported on the ingot support portion of the tray and the tray is supported by the belt conveyor unit, after the upper surface of the semiconductor ingot has been ground by the ingot grinding unit, but before the peel-off layers have been formed in the semiconductor ingot by the laser applying unit, as taught by Hirata, because it is known in the art that detecting asperities (e.g. defects) of an ingot can improve efficiency and productivity of a semiconductor wafer manufacturing process, as evidenced by Akiyama (see the last paragraph on page 4).
Regarding claim 10, Iizuka, as modified discloses the limitations of claim 9, as described above, and further discloses the ingot quality inspecting unit includes an ingot illuminating device (Hirata, Fig. 8 element 58), an ingot image capturing means (Hirata, Fig. 8 element 60) for detecting reflected light reflected by an upper surface of the semiconductor ingot (Hirata, Fig. 8 element 11a) that is illuminated by light emitted from the ingot illuminating device (Hirata, 0065), and an ingot defect detecting means (Hirata, Fig. 8 element 62) for processing an image captured by the ingot image capturing means and detecting a defect from the processed image (Hirata, 0072-0074 and 0077, where asperities corresponds to defect).
Regarding claim 11, Iizuka, as modified discloses the limitations of claim 10, as described above, and further discloses the ingot illuminating device and the ingot image capturing means are both positioned above the upper surface of the semiconductor ingot (Hirata, Fig. 8).
Regarding claim 12, Iizuka, as modified discloses the limitations of claim 10, as described above, and further discloses the defect being detected includes marks formed in the upper surface of the semiconductor ingot (0077, where asperities correspond to marks). Examiner notes that "marks" is a broad term which is being interpreted as any discontinuity on the surface condition on the upper surface of the semiconductor ingot.
Regarding claim 13, Iizuka, as modified discloses the limitations of claim 10, as described above, and further discloses the defect being detected includes marks formed in the upper surface of the semiconductor ingot upon peeling off of the wafer from the semiconductor ingot by the wafer peeling unit (0077, where asperities correspond to marks). Examiner notes that "marks" is a broad term which is being interpreted as any discontinuity on the surface condition on the upper surface of the semiconductor ingot.
Regarding claim 19, Iizuka, as modified discloses the limitations of claim 9, as described above, but fails to disclose the ingot quality inspecting unit is positioned adjacent to the ingot grinding unit. Examiner notes that Applicant has not provided any criticality for the relative positioning of these elements in the specification. Iizuka, as modified, fails to disclose the ingot quality inspecting unit is positioned adjacent to the ingot grinding unit. However, it has been held that an “obvious to try” rationale when choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is a support for a conclusion of obviousness which is consistent with the proper "functional approach" to the determination of obviousness as laid down in Graham, if the following findings can be established: (1) a finding that at the time of the invention, there had been a recognized problem or need in the art, which may include a design need or market pressure to solve a problem; (2) a finding that there had been a finite number of identified, predictable potential solutions to the recognized need or problem; (3) a finding that one of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success; and (4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness. See MPEP § 2143(I)(E).
In the instant case, and as per (1), one of ordinary skill in the art would recognize that there is a need in the art to provide an ingot quality inspecting unit based at least on the teachings of Hirata (see at least paragraphs 0005-0009). As per (2), one of ordinary skill in the art would recognize that there is a finite number of identifiable, predictable potential solutions for the relative arrangement of the ingot quality inspecting unit within the wafer manufacturing apparatus. As per (3), one of ordinary skill in the art would recognize that the particular positioning of the ingot quality inspecting unit, specifically having the ingot quality inspecting unit be adjacent to the ingot grinding unit, could have been pursued with a reasonable expectation of success, since said finite number of potential arrangements would have not yielded unpredictable results, nor would have rendered the prior art inoperable for its intended purpose. That is, the relative positioning of the ingot quality inspecting unit would have still expectedly have resulted in a wafer manufacturing apparatus which inspects ingots and produces wafers. As per (4), based on the above analysis, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have taken the teachings of Iizuka, as modified, and to have modified them by positioning the ingot quality inspecting unit to be adjacent to the ingot grinding unit, as a matter of trying a set of obvious, finite and predictable solutions, in order to obtain the best structural arrangement of components that best suits a quality inspecting arrangement, without yielding unpredictable results.
Regarding claim 21, Iizuka, as modified discloses the limitations of claim 9, as described above, and further discloses the defects that tend to disturb the laser beam comprise marks on the upper surface of the ingot created when the wafer is peeled off from the ingot (Hirata, 0077, where asperities correspond to marks). Examiner notes that "marks" is a broad term which is being interpreted as any discontinuity on the surface condition on the upper surface of the semiconductor ingot.
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Iizuka et al. (US20190181024), hereinafter Iizuka, in view of Durand et al. (US20050063801), hereinafter Durand, and in further view of Hyun et al. (CN102263160), attached as a PDF in office action mailed 5/20/2025 and hereinafter referred to as Hyun.
Regarding claim 14, Iizuka discloses a wafer manufacturing apparatus (Fig. 1 element 2) for manufacturing a wafer (Abstract) from a semiconductor ingot (Fig. 3 element 170), comprising: an ingot grinding unit (Fig. 2 element 4) including a first holding table (Fig. 2 element 14) for holding the semiconductor ingot thereon (0044) and grinding means (Fig. 3 element 16 meets the generic term of grinding means and also includes grindstones (Fig. 3 elements 44)) for grinding an upper surface of the semiconductor ingot held on the first holding table to planarize the upper surface of the semiconductor ingot (0045); a laser applying unit (Fig. 4 element 6) including a second holding table (Fig. 4 element 60) for holding the semiconductor ingot thereon (0046) and laser applying means (Fig. 5 element 62 meets the generic term of laser applying means and also includes a laser oscillator (Fig. 5 element 72) and a laser condenser (Fig. 5 element 74)) for applying a laser beam (Fig. 6 element LB) having a wavelength transmittable through the semiconductor ingot while positioning a focused spot of the laser beam at a depth in the ingot (0046), the depth corresponding to a thickness of the wafer to be produced from the semiconductor ingot, from the upper surface of the semiconductor ingot held on the second holding table, thereby forming peel-off layers in the semiconductor ingot (0046); a wafer peeling unit (Fig. 6 element 8) including a third holding table (Fig. 6 element 80) for holding the semiconductor ingot thereon (0051) and wafer peeling means (Fig. element 82 meets the generic term of wafer peeling means and also includes a liquid tank (Fig. 7 element 94) with a liquid (Fig. 7 element 106) inside of the tank and a suction member (Fig. 7 element 112)) for holding the upper surface of the semiconductor ingot held on the third holding table and peeling an ingot portion as the wafer from the ingot at the peel-off layers (0051 and 0053-0054); a tray (Fig. 8 element 9) including an ingot support portion (Fig. 8 element 117) for supporting the semiconductor ingot (0055) and a wafer support portion (Fig. 8 element 118) for supporting the wafer that has been peeled off from the semiconductor ingot (0055); a belt conveyor unit (Fig. 1 element 10) for delivering the semiconductor ingot supported on the tray between the ingot grinding unit, the laser applying unit, and the wafer peeling unit (Fig. 1, 0065), an ingot stocker (Fig. 1 element 148) for accommodating the tray supporting the semiconductor ingot (0068); and an ingot transfer unit (Fig. 1 element 12) for transferring the semiconductor ingot supported on the tray to the belt conveyor unit (0070).
Iizuka fails to disclose the ingot stocker includes a first endless belt for moving the tray; the ingot transfer unit includes a least one second endless belt for moving the tray, and further wherein the at least one second endless belt is actuated by a motor; a clutch assembly for transferring a drive force from the motor associated with the at least one second endless belt to a drive force transmitter associated with the first endless belt, such that the first endless belt can be driven by the motor that actuates the at least one second belt; a wafer belt conveyor for moving the wafer, wherein the wafer belt conveyer is positioned adjacent the wafer peeling unit; and a quality inspecting unit disposed adjacent to the belt conveyor unit; wherein the quality inspecting unit comprises: a wafer quality inspecting unit that is configured to inspect the quality of the wafer, while the wafer is supported by the wafer belt conveyor, to determine whether cracks exist on the wafer after the wafer has been peeled-off from the ingot by the wafer peeling unit.
Durand is also concerned with solving the problem of transferring items stored in shelves to another location and teaches the ingot stocker (all elements shown in Fig. 2 except element 11) includes a first endless belt (Fig. 2 element 13) for moving the tray (Fig. 2 element 11 corresponds to a tray; 0076); the ingot transfer unit includes at least one second endless belt (Fig. 8 element 22) for moving the tray (0076), and further wherein the at least one second endless belt is actuated by a motor (Fig. 7 element M1, 0062); a clutch assembly (Fig. 8 elements 38, 39, and 23) for transferring a drive force from the motor associated with the at least one second endless belt to a drive force transmitter associated with the first endless belt (Fig. 9, where the surface of the first endless belt (13) corresponds to a drive force transmitter; 0076), such that the first endless belt can be driven by the motor that actuates the at least one second belt (0076). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify the wafer manufacturing apparatus of Iizuka to a first endless belt on the ingot stocker and at least one second endless belt on the ingot transfer unit, wherein the at least one second endless belt is actuated by a motor; a clutch assembly for transferring a drive force from the motor associated with the at least one second endless belt to a drive force transmitter associated with the first endless belt, such that the first endless belt can be driven by the motor that actuates the at least one second belt, as taught by Durand, because Durand teaches that the claimed structure “makes it possible to stock and dispense fragile or deformable articles” (0020) and also “limits the cost and the complexity of the stocking trays” (0022) where the stocking trays are a subset of the ingot stocker and therefore would also limit the cost and complexity of the ingot stocker.
Iizuka, as modified, fails to disclose a wafer belt conveyor for moving the wafer, wherein the wafer belt conveyer is positioned adjacent the wafer peeling unit; and a quality inspecting unit disposed adjacent to the belt conveyor unit; wherein the quality inspecting unit comprises: a wafer quality inspecting unit that is configured to inspect the quality of the wafer, while the wafer is supported by the wafer belt conveyor, to determine whether cracks exist on the wafer after the wafer has been peeled-off from the ingot by the wafer peeling unit.
Hyun is also concerned with a quality inspecting unit and teaches a wafer belt conveyor (Fig. 6a element 2100) for moving the wafer (0159),; and a quality inspecting unit (Fig. 6a elements 2800a(1), 2800a(2), 2700a, and the structure used to “inspect defects” discussed in 0166); wherein the quality inspecting unit comprises: a wafer quality inspecting unit (Fig. 6a elements 2800a(1), 2800a(2), 2700a, and the structure used to “inspect defects” discussed in 0166; where the wafer quality inspecting unit is a subset of the quality inspecting unit that encompasses the entirety of the quality inspecting unit) that is configured to inspect the quality of the wafer, while the wafer is supported by the wafer belt conveyor, to determine whether cracks exist on the wafer after the wafer has been peeled-off from the ingot by the wafer peeling unit (Fig. 6a, 0159-0160 and 0166-0167, where the wafer quality inspecting unit is configured to inspect the same defects as the first to third visual inspection units, which are contaminants and cracks and the wafer quality inspecting unit inspects individual wafers, which would mean that the wafers would have already had to have been peeled-off from the ingot by the wafer peeling unit). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify the wafer manufacturing apparatus of Iizuka, as modified, to include a wafer belt conveyor for moving the wafer; and a quality inspecting unit; wherein the quality inspecting unit comprises: a wafer quality inspecting unit that is configured to inspect the quality of the wafer, while the wafer is supported by the wafer belt conveyor, to determine whether cracks exist on the wafer after the wafer has been peeled-off from the ingot by the wafer peeling unit, as taught by Hyun, because Hyun teaches that utilizing a wafer quality inspecting unit in conjunction with a wafer belt conveyer reduces the defect rate of semiconductors and achieves cost reduction (0171).
Iizuka, as modified, fails to disclose the wafer belt conveyer is positioned adjacent the wafer peeling unit, and the quality inspecting unit is disposed adjacent to the belt conveyor unit. Examiner notes that A