DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/15/2025 has been entered.
Claim Rejections - 35 USC § 112(d) – Failure to Further Limit
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS. — Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
New Claim 22 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of parent Claims 17-18, upon which it depends.
Specifically, Claim 22 fails to further limit either of parent Claims 17-18 because, for the reasons discussed infra, based on the instant specification one skilled in the art would interpret the “backside layer of… high modulus material [Emphasis Examiner’s]” of parent Claim 17, Line 2 as implicitly requiring the “Young's Modulus greater than approximately 1 GPa” recited in dependent Claim 22.
Initially, the Examiner points out that the “high modulus material” comprises the relative term of degree – “high”. Regarding the use of relative terms of degree in the claims, MPEP § 2173.05(b) states:
The fact that claim language, including terms of degree, may not be precise, does not automatically render the claim indefinite under 35 U.S.C. 112, second paragraph. Seattle Box Co., v. Industrial Crating & Packing, Inc., 731 F.2d 818, 221 USPQ 568 (Fed. Cir. 1984). Acceptability of the claim language depends on whether one of ordinary skill in the art would understand what is claimed, in light of the specification [Emphasis Examiner’s].
MPEP § 2173.05(b) further states:
When a term of degree is presented in a claim, first a determination is to be made as to whether the specification provides some standard for measuring that degree. If it does not, a determination is made as to whether one of ordinary skill in the art, in view of the prior art and the status of the art, would be nevertheless reasonably apprised of the scope of the invention [Emphasis Examiner’s].
In the instant case, Applicant’s Specification does, in fact, provide a standard for measuring the degree of a so-called “high modulus material”, teaching in ¶ [0016] that “[a]s used herein in relation to the layer 208, a high modulus refers to a material having a Young's modulus greater than approximately 1 GPa at room temperature… [such that] the cured layer 208 can be referred to as a high modulus layer [Emphasis Examiner’s].” Consequently, even though Applicant’s parent Claim 17 recites a relative term of degree regarding the limitation of a “high modulus material”, this limitation is not indefinite because, based on ¶ [0016] of Applicant’s disclosure, one skilled in the art would reasonably interpret the “high modulus material” of Claim 17 as requiring a Young's Modulus greater than approximately 1 GPa.
Thus, because one skilled in the art must reasonably interpret the “high modulus material” of Claim 17 as requiring a Young's Modulus greater than approximately 1 GPa in order to avoid any potential indefiniteness engendered by the relative term of degree “high”, it follows that Claim 22 fails to further limit parent Claims 17-18 because Claim 22’s limitation “wherein the cured backside layer has a Young's Modulus greater than approximately 1 GPa” merely reiterates the instant specification’s standard for assessing the degree of a “high modulus material” – without introducing any further patentably distinct subject matter.
Consequently, Claim 22 is rejected for failing to further limit parent Claims 17-18.
Claim Rejections - 35 USC § 103 - Obviousness
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-10, 17-18, 20, & 22 is/are rejected under 35 U.S.C. 103 as obvious over U.S. Pre-Grant Pub. 2011/0156279 to Takamoto et al. (from hereinafter Takamoto; prior art previously of record) in view of U.S. Pre-Grant Pub. 2010/0330780 A1 to Hwang et al. (from hereinafter Hwang; prior art previously of record).
Regarding Claim 1, Takamoto teaches a method (e.g., Figs. 2A-D; see Fig. 2C reproduced below for convenience) of forming a semiconductor apparatus (see Fig. 2D), comprising:
forming a backside layer (e.g., “wafer adhesion layer” 22; see ¶ [0051-53 & 0196]) of an electrically insulating material (e.g., one or more of the various resin materials detailed in ¶ [0084-86, 98-123, & 144-157]) on a backside (e.g., bottom side of 4/5 in Figs. 2A-C, which corresponds to the top side of 5 in Fig. 2D) of a semiconductor wafer (e.g., wafer 4; see ¶ [0206-207]) having a plurality of integrated circuit (IC) dice (e.g., “chips” 5; see Id.), wherein integrated circuits are formed on a front side (e.g., top side of 4/5 in Figs. 2A-C, which corresponds to the bottom side of 5 in Fig. 2D; see ¶ [0159]) of the semiconductor wafer (4) opposite to the backside of the semiconductor wafer (4);
mounting the semiconductor wafer (4) to dicing tape (e.g., dicing tape 3; see ¶ [0053 & 194-196]) with a die attach film (e.g., “laser marking layer” 21, comprising one or more of the various resin materials detailed in ¶ [0073-83, 108-123, & 144-145]) in which the die attach film (21) is between the backside layer (22) and the dicing tape (3); and
cutting the wafer (4) into respective IC dice (5).
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Takamoto may not explicitly teach that the die attach film (21) comprises an adhesive material.
However, Hwang does teach a similar method of forming a semiconductor apparatus (e.g., Figs. 1-11) comprising an analogous die attach film (e.g., “first bonding layer” 105; see ¶ [0058-63 & 80-105]) that does comprise an adhesive material (e.g., “bonding agent”; see ¶ [0083]).
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Therefore, before the instant application was filed it would have been obvious to one of ordinary skill in the art to form the die attach film (21) of Takamoto comprising an adhesive material, because Hwang demonstrates that adhesives constitute art-recognized equivalent materials used for the same purpose as die attach films during semiconductor device fabrication (see MPEP § 2144.06).
Regarding Claim 2, Takamoto teaches the method of claim 1, further comprising:
curing the backside layer (22; see ¶ [0196] teaching “wafer adhesion layer 22 is formed by applying a resin composition that is a forming material for forming the wafer adhesion layer 22 (resin composition for the wafer adhesion layer) onto a release paper so as to have a prescribed thickness after drying and further drying under prescribed conditions (in the case that thermal curing is necessary, performing a heating treatment and drying according to needs) [Emphasis Examiner’s]”) that is applied to the backside of the wafer (4).
Regarding Claim 3, Takamoto teaches the method of claim 2, wherein the cured backside layer (22) has a Young's Modulus greater than approximately 1 GPa (see ¶ [0153] teaching “the film for semiconductor back surface (film for semiconductor back surface having the wafer adhesion layer [22] and the laser marking layer [21], particularly the laser marking layer)… [has an] elastic modulus (tensile storage elastic modulus E') at 23°C [that] is preferably 1 GPa or more, more preferably 2 GPa or more, and further preferably 3 GPa or more” [Emphasis Examiner’s]).
Takamoto further demonstrates in ¶ [0153] that one skilled in the art would have obviously been motivated to utilize a cured backside layer (22) exhibiting such a high Young’s Modulus as claimed to predictably improve peeling off of chips (5) by suppressing attachment to supporting dicing tape (3).
Regarding Claim 4, Takamoto teaches the method of claim 1, wherein cutting the wafer (4) comprises semiconductor wafer sawing (i.e., “cutting”; see ¶ [0207]).
Regarding Claim 5, Takamoto teaches the method of claim 1, wherein cutting the semiconductor wafer (4; as illustrated by Fig. 2C supra) comprises cutting fully through the semiconductor wafer (4), the backside layer (22) and the die attach film (21) to expose the dicing tape (3) in scribe lines (between adjacent chips 5) formed by the cutting.
Regarding Claim 6, Takamoto teaches the method of claim 1, wherein forming the backside layer (22) comprises applying a single layer of the electrically insulating material on the backside of the semiconductor wafer (4; again, as illustrated by Fig. 2C supra).
Regarding Claim 8, Takamoto teaches the method of claim 1, wherein the backside layer (22) has a thickness less than 100 µm (e.g., see ¶ [0237] teaching “a wafer-side resin layer (wafer adhesion layer [22]) having a thickness (average thickness) of 10 µm”).
Regarding Claim 9, Takamoto teaches the method of claim 1, further comprising:
attaching the respective IC dice (5) to a substrate (e.g., “adherend” 6; see Fig. 2D & ¶ [0197-205 & 210-217]; and
encapsulating the IC dice and the substrate (6) within a packaging material (e.g., “encapsulation resin”, not shown; see ¶ [0210 & 215-216]).
Regarding Claim 10, Takamoto teaches the method of claim 9, wherein the substrate (6) comprises a leadframe or a pad (see ¶ [0211]).
Regarding Claim 11, Takamoto teaches the method of claim 1, wherein no tape expansion is performed after cutting the wafer (4; although Takomoto recognizes the conventionality of tape expansion after wafer cutting in ¶ [0208], Takamoto merely identifies it as a possibility that one skilled in the art might utilize in only certain cases, and by no means does Takamoto suggest that tape expansion is necessary to practice their invention; Consequently, based on Takamoto’s qualified and/or conditional assessment of tape expansion, the Examiner submits that before the instant application was filed one skilled in the art would have found it obvious to perform the invention of Claim 11 without performing tape expansion).
Regarding Claim 17, Takamoto teaches a method (see again Figs. 2A-D) of forming a semiconductor apparatus, comprising:
applying a backside layer (22) of an electrically insulating and high modulus material (see again ¶ [0153]) on a backside (e.g., bottom side of 4/5 in Figs. 2A-C, which corresponds to the top side of 5 in Fig. 2D) of a semiconductor wafer (4) having a plurality of integrated circuit (IC) dice (5), wherein integrated circuits are formed on a front side (e.g., top side of 4/5 in Figs. 2A-C, which corresponds to the bottom side of 5 in Fig. 2D; see ¶ [0159]) of the semiconductor wafer (4) opposite to the backside of the semiconductor wafer (4);
mounting the semiconductor wafer (4) to dicing tape (3) with a die attach film (21) in which the die attach film (21) is between the backside layer (22) and the dicing tape (3);
cutting the semiconductor wafer (4) into respective IC dice (5);
attaching a given IC dice (5) to a substrate (6); and
encapsulating the given IC dice (5) and the substrate (6) within a packaging material (e.g., “encapsulation resin”, not shown; see ¶ [0210 & 215-216]).
Takamoto may not explicitly teach that the die attach film (21) comprises an adhesive material.
However, Hwang does teach a similar method of forming a semiconductor apparatus (e.g., Figs. 1-11) comprising an analogous die attach film (e.g., “first bonding layer” 105; see ¶ [0058-63 & 80-105]) that does comprise an adhesive material (e.g., “bonding agent”; see ¶ [0083]).
Therefore, before the instant application was filed it would have been obvious to one of ordinary skill in the art to form the die attach film (21) of Takamoto comprising an adhesive material, because Hwang demonstrates that adhesives constitute art-recognized equivalent materials used for the same purpose as die attach films during semiconductor apparatus fabrication (see MPEP § 2144.06).
Regarding Claim 18, Takamoto teaches the method of claim 17, further comprising:
curing the backside layer (22) that is applied to the backside of the semiconductor wafer (4) prior to the mounting.
For example, see ¶ [0196] of Takamoto teaching:
[W]afer adhesion layer 22 is formed by applying a resin composition that is a forming material for forming the wafer adhesion layer 22 (resin composition for the wafer adhesion layer) onto a release paper so as to have a prescribed thickness after drying and further drying under prescribed conditions (in the case that thermal curing is necessary, performing a heating treatment and drying according to needs)… [and] subsequently, the laser marking layer 21 is formed by applying a resin composition that is a forming material for forming the laser marking layer 21 (resin composition for the laser marking layer) onto the wafer adhesion layer 22 so as to have a prescribed thickness after drying and further drying under prescribed conditions (in the case that thermal curing is necessary, performing a heating treatment and drying according to needs), thereby manufacturing a film 2 for semiconductor back surface having a laminate structure of the laser marking layer 21 and the wafer adhesion layer 22 [Emphasis Examiner’s]”
Regarding Claim 20, Takamoto teaches the method of claim 18, wherein cutting the semiconductor wafer (4) comprises cutting fully through the semiconductor wafer (4; again, as illustrated by Fig. 2C supra), the backside layer (22) and the die attach film (21) to expose the dicing tape (3) in scribe lines (between adjacent dies 5) formed by the cutting.
Regarding Claim 22, Takamoto teaches the method of claim 18, wherein the cured backside layer (22) has a Young's Modulus greater than approximately 1 GPa.
Claims 7 & 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takamoto in view of Hwang as detailed supra, and further in view of U.S. Pre-Grant Pub. 2016/0027694 to Truhitte et al. (from hereinafter Truhitte; prior art previously of record).
Regarding Claim 7, Takamoto and Hwang teach the method of claim 1.
Takamoto and Hwang may not explicitly teach that the forming the backside layer (Takamoto 22) comprises screen printing the electrically insulating layer on the backside of the semiconductor wafer (Takamoto 4).
However, Truhitte does teach a similar method of forming a semiconductor apparatus (e.g., Figs. 1-11) comprising forming an analogous backside/insulating layer (e.g., 30; see ¶ [0090]) by screen printing the electrically insulating layer (30; see ¶ [0090] demonstrating that screen printing is one of multiple different deposition processes that one skilled in the art may implement to form the backside layer 30) on the backside of a semiconductor wafer (2; see ¶ [0086]).
Therefore, before the instant application was filed it would have been obvious to one of ordinary skill in the art to form the backside layer (22) of Takamoto using screen printing, because Truhitte demonstrates that this deposition method is an art-recognized equivalent used for the same purpose of forming insulating backside layers during semiconductor device fabrication (see MPEP § 2144.06).
Regarding Claim 21, Takamoto and Truhitte teach the method of claim 17, wherein the semiconductor apparatus comprises a quad flat no-lead (QFN) package (see Truhitte ¶ [0004]).
Response to Arguments
Applicant’s arguments with respect to the instantly amended Claims 1 & 17 have been considered but are moot in view of the new grounds of rejection necessitated by Applicant’s claim amendments filed 01/15/2025.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E GORDON whose telephone number is (571)270-7432. The examiner can normally be reached on M-F 9 a.m. - 6 a.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thao X Le can be reached on 5712721708. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Matthew E. Gordon/Primary Examiner, Art Unit 2892
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