Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 25th, 2026 has been received. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendments
Acknowledgment is made of the amendment filed 01/30/2026 (“A...”), in which: claim 1 is amended; no new claims are added; no claims are canceled; and the rejection of the claims are traversed. Claims 1 – 5 and 17 – 18, are currently pending an Office Action on the merits as follows.
Response to Arguments
Applicant’s arguments with respect to claims 1 – 5 and 17 – 18 have been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 2, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 6326265 B1), and further in view of Tran et al. (US 20160217864 A1), Chen et al. (US 6091657 A), and Lin et al. (US 5999455 A).
Regarding independent Claim 1, Liu teaches a non-volatile memory system, comprising:
a semiconductor die comprising a p-substrate (col. 8; lines 25 – 26 discloses that p-type substrate 248. See Fig. 7);
a first deep n-well (Fig. 7; N-Well 246) formed in the p-substrate (col. 2; line 66 teaches that the invention is formed on a die);
a first p-well (Fig. 7; P-Well 244) formed within the first deep n-well (Fig. 7 and cols. 7 – 8; lines 66 - 21); …
an array (Fig. 6 and col. 2; line 53) of non-volatile memory cells (Fig. 6; cells 210a and 210b) formed within the first p-well (Fig. 7), each non-volatile memory cell comprising a floating gate (Fig. 7; floating gate 228a) and a plurality of terminals (Fig. 7; plurality of terminals; Also, Fig. 6); …
However, Liu remains silent regarding:
… a second deep n-well formed in the p-substrate, wherein the second deep n-well is separate from the first deep n-well;
a second p-well formed within the second deep n-well;
a third deep n-well formed in the p-substrate, wherein the third deep n-well is separate from the first deep n-well and the second deep n-well;
a third p-well formed within the third deep n-well; …
a row decoder circuit formed within the second p-well;
a high voltage decoder circuit formed within the third p-well; and …
a bias generator to bias the first p-well, the second p-well, and the third p-well to: (i) a voltage of 0 V during a program operation, (ii) a voltage of 0 V during a read operation, and (iii) a negative voltage during an erase operation.
However, in the same field of endeavor, Tran teaches in [0035] that Xdecoder 200 may be used in memory device 50 (Fig. 2). The examiner understands Xdecoder 200 to be a generalization of a row decoder circuit, such that may be applied to Tran’s Xdecoder 54 or decoder 80. Further, Tran teaches in [0036] that Xdecoder 200 may be formed in a p-well formed in a n-well; such that the structure wherein a second deep n-well formed in the p-substrate including a second p-well formed within the second deep n-well, further including a row decoder circuit formed within the second p-well is rendered obvious. Additionally, Tran teaches in [0036] that a p-well would be for N-type devices (NMOS), and a second N-type well would be for P type devices (PMOS). Further, Tran teaches in [0037] a high voltage decoding circuit 300 which includes high voltage (hv) PMOS 321 and 322 and hv NMOS transistor 323. In [0038], Trans discloses that high voltage decoding circuit 400 (a second embodiment to what is described in [0037] for high voltage decoding circuit 300 shown in Fig. 5) for a triple well CMOS may be used in memory device 50 (Fig. 2). Thus, the structure for a triple well CMOS wherein a third deep n-well formed in the p-substrate including a third p-well formed within the third deep n-well, further including a high voltage decoder circuit formed within the third p-well is rendered obvious (Fig. 2). Such peripheral circuitry may be combined with the Liu’s semiconductor die to form the non-volatile memory system including a second deep n-well formed in the p-substrate; a second p-well formed within the second deep n-well; a third deep n-well formed in the p-substrate; a third p-well formed within the third deep n-well; a row decoder circuit formed within the second p-well; and a high voltage decoder circuit formed within the third p-well.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Liu’s non-volatile memory device to include Tran’s disclosed triple well structure with a second p-well and a third p-well including a row decoder circuit formed within the second p-well and a high voltage decoder circuit formed within the third p-well, because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, Liu’s non-volatile memory device as modified by Tran’s disclosed triple well structure with a second p-well and a third p-well including a row decoder circuit formed within the second p-well and a high voltage decoder circuit formed within the third p-well can yield a predictable result of selecting the correct memory cell and providing appropriate power for program, read, and erase operations since that is the known function in the art for row decoders and high voltage decoders in non-volatile memory devices ([0020]). Since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, one of ordinary skill in the art would have recognized that the results of the combination were predictable before the effective filing date of the instant invention.
Further, in the same field of endeavor, Chen teaches a substrate including n-tub 104 and n-tub 111 (Fig. 1); wherein the examiner is considering n-tub 104 and n-tub 111 to be analogous to separate deep n-wells similar to the instant deep n-wells, e.g., the first deep n-well and the second deep n-well. Further, Chen teaches memory devices 100 formed in the n-tub 104 and on-pitch peripheral n-channel devices 101, e.g., a row decoder, formed in the n-tub 111. Examiner asserts that Chen’s connectivity is a known structure in the field of endeavor that may be used to improve devices such as that of Liu, further in view of Tran.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the integrated circuit of Liu, further in view of Tran to include a row decoder circuit or a high voltage decoder circuit formed in a deep n-well separate from the deep n-well in which the memory cell device is formed, as disclosed by Chen, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Chen’s memory devices 100 and on-pitch peripheral n-channel devices 101 are comparable to the memory cell array and row decoder circuit/ high voltage decoder circuit of Liu further in view of Tran, because they are devices that exhibit similar/parallel functionality. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the integrated circuit of Liu, further in view of Tran to include a row decoder circuit or a high voltage decoder circuit formed in a deep n-well separate from the deep n-well in which the memory cell device is formed, as disclosed by Chen, with the predictable result of allowing flexibility for applying different voltages to the separated n-wells or to the p-well within (Chen: col. 2; line 48 – col. 4; line 42).
Additionally, Tran teaches in [0020] that each decoder has an associated negative charge pump included from the charge pump 56. Examiner is considering the charge pump 56 that includes negative charge pump generator, e.g., negative charge pump generator 260, to be analogous to the instant bias generator due to the function of the charge pump to apply a bias voltage. Further, Tran discloses the decoders provides voltage levels for the control gate and the source line as shown in embodiments drawn in Figs. 5 – 7 ([0020]). In view of the semiconductor structure regarding the row decoder circuit formed within the second p-well and the high voltage decoder circuit formed within the third p-well, Tran discloses a bias generator to bias the first p-well, the second p-well, and the third p-well.
Further, in the same field of endeavor, Lin teaches a semiconductor structure wherein a bias voltage is applied to p-wells PWI (col. 14; lines 63 – 67 and col. 15; lines 1 – 11. Also See Table 2 and Figs. 9 and 13). Further, Fig. 13 and Table 2 show the applied voltages:
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132
349
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Greyscale
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135
296
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Greyscale
Examiner’s understanding from the disclosure of Tran, further in view of Lin, is that the bias generator that is configured to apply bias voltages wherein (i) a voltage of 0 V during a program operation, (ii) a voltage of 0 V during a read operation, and (iii) a negative voltage during an erase operation would have been obvious before the effective filing date of the instant invention. Thus, the disclosure of Liu may be modified by Tran, further in view of Lin, to yield the non-volatile memory system wherein a bias generator to bias the first p-well, the second p-well, and the third p-well to: (i) a voltage of 0 V during a program operation, (ii) a voltage of 0 V during a read operation, and (iii) a negative voltage during an erase operation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the non-volatile memory device of Liu and Tran to include a bias generator to bias the first p-well, the second p-well, and the third p-well to: (i) a voltage of 0 V during a program operation, (ii) a voltage of 0 V during a read operation, and (iii) a negative voltage during an erase operation, as disclosed by Tran, further in view of Lin, because such a modification is the result of applying a known technique to a known device ready for improvement to yield predictable results. More specifically, the bias generator of Tran, further in view of Lin, configured to bias the first p-well, the second p-well, and the third p-well to: (i) a voltage of 0 V during a program operation, (ii) a voltage of 0 V during a read operation, and (iii) a negative voltage during an erase operation permits voltages to applied to memory cells to perform program, read, and erase operations; and more specifically, a negative voltage applied to the first through third p-wells of the non-volatile memory device during an erasure operation. This known benefit in Tran, further in view of Lin, is applicable to the non-volatile memory device of Liu and Tran as they both share characteristics and capabilities, namely, they are directed to non-volatile memory devices. Therefore, it would have been recognized that modifying the non-volatile memory device of Liu and Tran to include a bias generator to bias the first p-well, the second p-well, and the third p-well to: (i) a voltage of 0 V during a program operation, (ii) a voltage of 0 V during a read operation, and (iii) a negative voltage during an erase operation, as disclosed by Tran, further in view of Lin, would have yielded predictable results because (i) the level of ordinary skill in the art demonstrated by the references applied shows the ability to incorporate the bias generator of Tran, further in view of Lin, in non-volatile memory devices and (ii) the benefits of such a combination would have been recognized by those of ordinary skill in the art.
Regarding dependent Claim 2, Liu, further in view of Tran, Chen, and Lin, teach the non-volatile memory system of claim 1, wherein the plurality of terminals for each non-volatile memory cell comprises:
a bit line terminal (Liu: Fig. 6; plurality of bit lines, e.g., bit line 214. See col. 7; lines 31 – 56), a source line terminal (Liu teaches source terminal 230 in col. 7; lines 31 – 56), and a word line terminal (Liu: Fig. 6; plurality of word lines, e.g., word line 212a. See col. 7; lines 31 – 56).
See Fig. 4; flash 102 and Fig. 6; plurality of Flash memory cells, e.g., cell 210a of Liu. Also, see col. 7; lines 31 – 56 of Liu’s disclosure.
Regarding dependent Claim 17, Liu, further in view of Tran, Chen, and Lin, teach the non-volatile memory system of claim 1, wherein:
the bias generator applies a voltage of 0 V to word lines of un-selected non-volatile memory cells during read, erase, and programming operations.
In response to applicant's claim of the bias generator applies a voltage of 0 V to word lines of un-selected non-volatile memory cells during read, erase, and programming operations, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Therefore, if the prior art includes the bias generator, capable of applying a voltage of 0 V and coupled to word lines, then the prior art anticipates and/or renders obvious the bias generator applies a voltage of 0 V to word lines of un-selected non-volatile memory cells during read, erase, and programming operations.
Regarding the bias generator, Tran teaches the memory device including a bias generator; such that the bias generator applies a voltage to a memory cell, e.g., to the world line of a memory cell, in the memory cell array. Some examples of the operations of the bias generator may be understood from at least tables 1 – 3 of Tran, which disclose that the bias generator applies a voltage of 0 V to word lines of un-selected non-volatile memory cells during read, erase, and programming operations.
Further, see col. 9; lines 39 – 51 of Liu wherein it is taught during an operation of the memory device the control gate 236b is at ground; such that, through the combination of Liu, Tran, and Lin the bias generator may be responsible for the applied voltages of the world lines of un-selected memory cells.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the non-volatile memory device of Liu, further in view of Tran and Lin, to include Tran’s bias generator configured to apply a voltage of 0 V to word lines of un-selected non-volatile memory cells during read, erase, and programming operations, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Tran’s non-volatile memory device is comparable to Liu’s non-volatile memory device because they are both non-volatile memory devices that include triple well structures. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the non-volatile memory device of Liu, further in view of Tran and Lin, to include Tran’s bias generator with the predictable result of configuring the bias generator to apply a voltage of 0 V to word lines of un-selected non-volatile memory cells during read, erase, and programming operations.
Regarding dependent Claim 18, Liu, further in view of Tran, Chen, and Lin, teach the non-volatile memory system of claim 1, wherein:
the bias generator applies a voltage to word lines of un-selected non-volatile memory cells the voltage selected to reduce stress across gate oxide of the cells during read, erase, and programming operations.
In response to applicant's claim of the bias generator applies a voltage to word lines of un-selected non-volatile memory cells the voltage selected to reduce stress across gate oxide of the cells during read, erase, and programming operations, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Therefore, if the prior art includes the bias generator coupled to word lines, then the prior art anticipates and/or renders obvious the bias generator applies a voltage to word lines of un-selected non-volatile memory cells the voltage selected to reduce stress across gate oxide of the cells during read, erase, and programming operations.
Regarding the bias generator, Tran teaches memory device including a bias generator; such that the bias generator applies a voltage to a memory cell, e.g., to the world line of a memory cell, in the memory cell array. Some examples of the operations of the bias generator may be understood from at least [0021] and [0036], which disclose the connectivity within the device and the capabilities of the bias generator.
Further, see cols. 9 – 10; lines 52 – 24 of Liu regarding preventing acceleration of hot hole trapping in the gate oxide of the cells during cell operation, such that stress is reduced.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the non-volatile memory device of Liu, further in view of Tran and Lin, to include Tran’s bias generator configured to apply applies a voltage to word lines of un-selected non-volatile memory cells the voltage selected to reduce stress across gate oxide of the cells during read, erase, and programming operations, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Tran’s non-volatile memory device is comparable to Liu’s non-volatile memory device because they are both non-volatile memory devices that include triple well structures. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the non-volatile memory device of Liu, further in view of Tran and Lin, to include Tran’s bias generator with the predictable result of configuring the bias generator to apply applies a voltage to word lines of un-selected non-volatile memory cells the voltage selected to reduce stress across gate oxide of the cells during read, erase, and programming operations.
Claims 3 – 5 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 6326265 B1), and further in view of Tran et al. (US 20160217864 A1), Chen et al. (US 6091657 A), Lin et al. (US 5999455 A), and Fan et al. (US 6747310 B2).
Regarding dependent Claim 3, Liu, further in view of Tran, Chen, and Lin, teach the non-volatile memory system of claim 2; however, Liu remains silent wherein the plurality of terminals for each non-volatile memory cell further comprises:
an erase gate terminal
Liu does show in Fig. 7; element 28b, exhibiting the flow of electrons terminating at this element; further the construction of the device resembles that of the prior art submitted by the applicant as “Figure 2 (PRIOR ART)” of the present application).
Figure 2 (Prior Art) presents a configuration credited to Fan who teaches an erase gate terminal in col. 2; line 59 of their disclosure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the memory device of Liu, further in view of Tran and Lin, to include an erase gate terminal, as disclosed by Fan, because such a modification is taught, suggested, or motivated by the art. More specifically, the motivation to modify Liu’s element 28b to include an erase gate terminal, as taught by Fan, is implicitly provided by Fig. 7 of Liu, showing that electrons flow through the p-well terminates at element 28b. The person of ordinary skill in the art would have recognized the benefit of terminal for electrons with energy that exceeds the effective oxide barrier height potential (col. 8; lines 54 - 67 of Liu).
Regarding dependent Claim 4, Liu, further in view of Tran, Chen, Lin, and Fan, teach the non-volatile memory system of claim 3, wherein the plurality of terminals for each non-volatile memory cell further comprises:
a control gate terminal (Liu: Fig. 7; control gate 236a).
Regarding dependent Claim 5, Liu, further in view of Tran, Chen, Lin, and Fan, teach the non-volatile memory system of claim 4, wherein:
the bias generator is configured to apply a negative voltage to a control gate terminal of a selected memory cell during an erase operation.
In response to applicant's claim of the bias generator is configured to apply a negative voltage to a control gate terminal of a selected memory cell during an erase operation, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Therefore, if the prior art includes the bias generator capable of applying a negative voltage and coupled to a control gate terminal, then the prior art anticipates and/or renders obvious the bias generator is configured to apply a negative voltage to a control gate terminal of a selected memory cell during an erase operation.
Regarding the bias generator, Tran teaches the memory device including a bias generator; such that the bias generator applies a voltage to a memory cell, e.g., to the control gate of a memory cell, in the memory cell array. Some examples of the operations of the bias generator may be understood from at least table 3 of Tran, which disclose that the bias generator is configured to apply a negative voltage to a control gate terminal of a selected memory cell during an erase operation.
Further, Liu discloses a table of voltages applied during operation of their semiconductor device in col. 11 of their disclosure. The table is provided below:
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232
533
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The table teaches a negative voltage, (-Vs), applied next to the selected WL during an erase operation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the non-volatile memory device of Liu, further in view of Tran and Lin, to include Tran’s bias generator configured to apply a negative voltage to a control gate terminal of a selected memory cell during an erase operation, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Tran’s non-volatile memory device is comparable to Liu’s non-volatile memory device because they are both non-volatile memory devices that include triple well structures. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the non-volatile memory device of Liu, further in view of Tran and Lin, to include Tran’s bias generator with the predictable result of configuring the bias generator to apply a negative voltage to a control gate terminal of a selected memory cell during an erase operation.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20180240525 A1 previously relied upon.
US 20020182805 A1 teaches a triple well structure of N-well/deep P-well/N-substrate can be replaced with a triple well structure of P-well/deep N-well/ P-substrate ([0044]).
US 20130279251 A1 previously relied upon.
US 20190115077 A1 previously relied upon.
US 6137723 A teaches an erase operation of a semiconductor device that includes an n-well 1412 formed in a substrate 1410, a p-well 1414 formed within the n-well 1412, a floating gate 1424, and contact regions 1426 and 1428. See Figs. 14A – 14D. The erase operation includes reverse-biasing such that a negative voltage is applied to p-well 1414, as discussed in par. 99 – 100, causing a tunneling process, i.e., Fowler-Nordheim tunneling, to erase a cell.
US 20160027504 A1 teaches a column decoder formed in the same p-well 13 as the memory cell array; and the p-well 13 they are formed in is in a same deep n-well 12. See Fig. 3.
US 20130242672 A1 and US 6074916 A teach a similar device to that of the present application.
US 20070097775 A1 teaches a flash memory device with multiple p-well regions and row decoders therein.
US 20030071301 A1, US 6134150 A, US 7554862 B2, US 7696561 B2, and US 20080259690 A1 teach a nonvolatile memory cell formed in a p-well formed in a deep n-well on a p-type substrate.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIO A AUTORE whose telephone number is (571)270-0059. The examiner can normally be reached Monday - Friday, 8 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARIO A. AUTORE JR.
Examiner
Art Unit 2897
/MARIO ANDRES AUTORE JR/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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