Prosecution Insights
Prosecution Insights
Technology areas: Computing & Software • Semiconductors, Circuits & Optics
13 pending office actions • 6 art units • 13 examiners • 0 of 13 (0%) have an AI response strategy ready • 35 patents granted in the last 365 days
Silicon Storage Technology Inc. has 13 pending office actions within the Semiconductors, Circuits & Optics technology area. These actions are distributed across 5 distinct art units, showing a varied technical scope. The prosecution effort involves 12 distinct examiners, which means that nearly every pending action is being reviewed by a different person.
The busiest examiner for this portfolio is BERMUDEZ LOZADA, ALFREDO, who is handling 2 busiest_examiner_pending actions. This represents a portion of the 13 total pending office actions. Because the 13 actions are spread across 5 distinct art units, the company faces a variety of examination environments within the Semiconductors, Circuits & Optics sector.
With 12 distinct examiners managing 13 pending office actions, the company must maintain consistent arguments across a group of patent office staff. The 5 distinct art units involved suggest that the 13 pending actions cover several different sub-specialties. This level of examiner diversity, with 12 individuals involved, requires tracking of individual examiner preferences.
Based on the USPTO statutory response window for each pending office action. 6 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 6 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §101 + other | 1 (8%) |
| §103 only | 5 (38%) |
| §102 only | 1 (8%) |
| Double-patenting only | 1 (8%) |
| Multi-statute (no §101) | 5 (38%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| GIARDINO JR, MARK A | 1 | 84.6% | +2.5% |
| FOX, BRANDON C | 1 | 85.6% | +10.1% |
| CHEN, XIAOCHUN L | 1 | 91.9% | -0.5% |
| HOANG, HUAN | 1 | 93.3% | +5.6% |
| LEBENTRITT, MICHAEL | 1 | 92.2% | +6.2% |
| LEBOEUF, JEROME LARRY | 1 | 85.4% | +6.4% |
| YOHA, CONNIE C | 1 | 93.8% | +0.2% |
| ZENG, WENWEI | 1 | — | — |
| COON, BRADLEY SCOTT | 1 | 94.1% | +14.9% |
| BUI, KENNY KIM | 1 | 63.6% | +48.3% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 6 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18782022 | ARRAY OF MULTI-VALUE NON-VOLATILE MEMORY CELLS | HOANG, HUAN | 39d |
| 18435943 | PROGRAMMABLE LOGIC BLOCK COMPRISING FLASH MEMORY ARRAY TO STORE CONFIGURATION DATA FOR PROGRAMMABLE LOGIC | LEBOEUF, JEROME LARRY | 61d |
| 19181816 | PARAMETER ENHANCED SEQUENTIAL PROGRAMMING METHOD | GIARDINO JR, MARK A | — |
| 18782010 | RESISTIVE RANDOM ACCESS MEMORY CELL ARRAY | CHEN, XIAOCHUN L | — |
| 18637265 | SEMICONDUCTOR DEVICE WITH NON-PLANAR MOSFET DEVICE DIE AND PLANAR MOSFET DEVICE DIE | LEBENTRITT, MICHAEL | — |
| 18227254 | PROGRAMMING OF A SELECTED NON-VOLATILE MEMORY CELL | YOHA, CONNIE C | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 6 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 17893071 | Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network | BERMUDEZ LOZADA, ALFREDO | 28d overdue |
| 17848381 | ARTIFICIAL NEURAL NETWORK COMPRISING REFERENCE ARRAY FOR ARRAY BIAS CONFIGURATION | FEITL, LEAH M | 4d overdue |
| 18135664 | MULTIPLEXORS FOR NEURAL NETWORK ARRAY | COON, BRADLEY SCOTT | 28d |
| 18803363 | METHOD OF FORMING RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELLS | FOX, BRANDON C | — |
| 18218368 | ANALOG COMPUTATION-IN-MEMORY ENGINE AND DIGITAL COMPUTATION-IN-MEMORY ENGINE TO PERFORM OPERATIONS IN A NEURAL NETWORK | ZENG, WENWEI | — |
| 18077993 | OUTPUT CIRCUIT FOR ARTIFICIAL NEURAL NETWORK ARRAY | BUI, KENNY KIM | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18135664 | MULTIPLEXORS FOR NEURAL NETWORK ARRAY | COON, BRADLEY SCOTT | 28d |
| 18803363 | METHOD OF FORMING RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELLS | FOX, BRANDON C | — |
| 18077993 | OUTPUT CIRCUIT FOR ARTIFICIAL NEURAL NETWORK ARRAY | BUI, KENNY KIM | — |
| Art Unit | Apps |
|---|---|
| 2824 | 2 |
| 2827 | 2 |
| 2825 | 2 |
| 2135 | 1 |
| 2182 | 1 |
| 2100 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 19181816 | PARAMETER ENHANCED SEQUENTIAL PROGRAMMING METHOD | GIARDINO JR, MARK A | 2135 | §103 | Final Rejection | — | Pending | Apr 17, 2025 |
| 18803363 | METHOD OF FORMING RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELLS | FOX, BRANDON C | — | §102§103 | Non-Final OA | — | Pending | Aug 13, 2024 |
| 18782010 | RESISTIVE RANDOM ACCESS MEMORY CELL ARRAY | CHEN, XIAOCHUN L | 2824 | §103 | Final Rejection | — | Pending | Jul 23, 2024 |
| 18782022 | ARRAY OF MULTI-VALUE NON-VOLATILE MEMORY CELLS | HOANG, HUAN | 2827 | §103 | Final Rejection | 39d | Pending | Jul 23, 2024 |
| 18637265 | SEMICONDUCTOR DEVICE WITH NON-PLANAR MOSFET DEVICE DIE AND PLANAR MOSFET DEVICE DIE | LEBENTRITT, MICHAEL | — | §102 | Non-Final OA | — | Pending | Apr 16, 2024 |
| 18435943 | PROGRAMMABLE LOGIC BLOCK COMPRISING FLASH MEMORY ARRAY TO STORE CONFIGURATION DATA FOR PROGRAMMABLE LOGIC | LEBOEUF, JEROME LARRY | 2824 | §103 | Non-Final OA | 61d | Pending | Feb 07, 2024 |
| 18227254 | PROGRAMMING OF A SELECTED NON-VOLATILE MEMORY CELL | YOHA, CONNIE C | 2825 | DP | Non-Final OA | — | Pending | Jul 27, 2023 |
| 18218368 | ANALOG COMPUTATION-IN-MEMORY ENGINE AND DIGITAL COMPUTATION-IN-MEMORY ENGINE TO PERFORM OPERATIONS IN A NEURAL NETWORK | ZENG, WENWEI | — | §101§103 | Non-Final OA | — | Pending | Jul 05, 2023 |
| 18135664 | MULTIPLEXORS FOR NEURAL NETWORK ARRAY | COON, BRADLEY SCOTT | 2827 | §103§112 | Final Rejection | 28d | Pending | Apr 17, 2023 |
| 18077993 | OUTPUT CIRCUIT FOR ARTIFICIAL NEURAL NETWORK ARRAY | BUI, KENNY KIM | — | §103§112 | Non-Final OA | — | Pending | Dec 08, 2022 |
| 17893071 | Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network | BERMUDEZ LOZADA, ALFREDO | 2825 | §102§103 | Final Rejection | 28d overdue | Pending | Aug 22, 2022 |
| 17847486 | VECTOR-BY-MATRIX-MULTIPLICATION ARRAY UTILIZING ANALOG INPUTS | DE LA GARZA, CARLOS HEBERTO | 2182 | §103 | Final Rejection | 7d | Pending | Jun 23, 2022 |
| 17848381 | ARTIFICIAL NEURAL NETWORK COMPRISING REFERENCE ARRAY FOR ARRAY BIAS CONFIGURATION | FEITL, LEAH M | 2100 | §103§112 | Non-Final OA | 4d overdue | Pending | Jun 23, 2022 |
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