Prosecution Insights
Last updated: August 17, 2026

Silicon Storage Technology Inc.

12 pending office actions • 8 art units • 11 examiners • 0 of 12 (0%) have an AI response strategy ready • 30 patents granted in the last 365 days

Portfolio Summary

12
Total Pending OAs
9
Non-Final OAs
3
Final Rejections
0
Advisory / Quayle

Response Deadline Pressure

Based on the USPTO statutory response window for each pending office action. 5 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.

2
Overdue
1
Due this week
1
Due this month
0
Due in next 60 days
1
Due later

Deadline Fire Line

Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 5 of the docket's apps have a known mailing date.

-30dToday30d60d90d120d
Overdue (2)Due ≤ 7 days (1)Due ≤ 30 days (1)Due later (1)

Case Difficulty Mix

Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.

4
Hard (33%)
7
Medium (58%)
1
Easy (8%)
0
Unknown (0%)

Rejection Statute Mix

BucketCases
§103 only3 (25%)
§102 only4 (33%)
§112 only1 (8%)
Multi-statute (no §101)4 (33%)

Industry Mix

How the docket's pending cases split across USPTO tech-center bands.

0
Life Sciences
0% of docket
4
Information Tech
33% of docket
0
Communications
0% of docket
6
Semiconductors
50% of docket
0
Mechanical / Eng
0% of docket
2
Business / Other
17% of docket

Time-on-OA Estimate

Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.

120 h
Manual time on pending OAs
24 h
Time saved (low, 20%)
42 h
Time saved (mid, 35%)
1.1 wks
FTE-weeks freed (mid)

Top Examiners on this docket

ExaminerApps on this docketAllow rateInterview lift
BERMUDEZ LOZADA, ALFREDO 2 89.3% +1.9%
NGUYEN, THIEN DANG 1 87.4% +11.7%
CHEN, XIAOCHUN L 1 91.9% -0.5%
LEBENTRITT, MICHAEL 1 92.2% +6.3%
LEBOEUF, JEROME LARRY 1 85.2% +7.2%
COON, BRADLEY SCOTT 1 93.2% +19.4%
HO, HOAI V 1 92.6% +5.5%
BUI, KENNY KIM 1 65.0% +43.4%
DE LA GARZA, CARLOS HEBERTO 1 70.6% +41.7%
FEITL, LEAH M 1 23.6% +5.2%

Quick Wins (5)

Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 5 ordered by deadline are shown.

App #TitleExaminerDue in
18135664 MULTIPLEXORS FOR NEURAL NETWORK ARRAY COON, BRADLEY SCOTT 28d
19033427 GROUPING AND ERROR CORRECTION FOR NON-VOLATILE MEMORY CELLS NGUYEN, THIEN DANG
18991295 BIAS CIRCUIT FOR NON-VOLATILE MEMORY ARRAY IN A NEURAL NETWORK BERMUDEZ LOZADA, ALFREDO
18637265 SEMICONDUCTOR DEVICE WITH NON-PLANAR MOSFET DEVICE DIE AND PLANAR MOSFET DEVICE DIE LEBENTRITT, MICHAEL
18080676 ADJUSTABLE PROGRAMMING CIRCUIT FOR NEURAL NETWORK HO, HOAI V

Hard Cases (4)

Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 4 ordered by deadline are shown.

App #TitleExaminerDue in
17893071 Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network BERMUDEZ LOZADA, ALFREDO 28d overdue
17848381 ARTIFICIAL NEURAL NETWORK COMPRISING REFERENCE ARRAY FOR ARRAY BIAS CONFIGURATION FEITL, LEAH M 4d overdue
18435943 PROGRAMMABLE LOGIC BLOCK COMPRISING FLASH MEMORY ARRAY TO STORE CONFIGURATION DATA FOR PROGRAMMABLE LOGIC LEBOEUF, JEROME LARRY 61d
18782010 RESISTIVE RANDOM ACCESS MEMORY CELL ARRAY CHEN, XIAOCHUN L

Interview Candidates (4)

Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 4 ordered by deadline are shown.

App #TitleExaminerDue in
17847486 VECTOR-BY-MATRIX-MULTIPLICATION ARRAY UTILIZING ANALOG INPUTS DE LA GARZA, CARLOS HEBERTO 7d
18135664 MULTIPLEXORS FOR NEURAL NETWORK ARRAY COON, BRADLEY SCOTT 28d
19033427 GROUPING AND ERROR CORRECTION FOR NON-VOLATILE MEMORY CELLS NGUYEN, THIEN DANG
18077993 OUTPUT CIRCUIT FOR ARTIFICIAL NEURAL NETWORK ARRAY BUI, KENNY KIM

Top Art Units

Art UnitApps
2825 2
2824 2
2111 1
2827 1
2199 1
2182 1
2100 1
2845 1

Pending Office Actions

App #TitleExaminerArt UnitStatutesStatusDue inAIFiled
19033427 GROUPING AND ERROR CORRECTION FOR NON-VOLATILE MEMORY CELLS NGUYEN, THIEN DANG 2111 §103 Non-Final OA Pending Jan 21, 2025
18991295 BIAS CIRCUIT FOR NON-VOLATILE MEMORY ARRAY IN A NEURAL NETWORK BERMUDEZ LOZADA, ALFREDO 2825 §102 Non-Final OA Pending Dec 20, 2024
18782010 RESISTIVE RANDOM ACCESS MEMORY CELL ARRAY CHEN, XIAOCHUN L 2824 §102§103§112 Non-Final OA Pending Jul 23, 2024
18637265 SEMICONDUCTOR DEVICE WITH NON-PLANAR MOSFET DEVICE DIE AND PLANAR MOSFET DEVICE DIE LEBENTRITT, MICHAEL §102 Non-Final OA Pending Apr 16, 2024
18435943 PROGRAMMABLE LOGIC BLOCK COMPRISING FLASH MEMORY ARRAY TO STORE CONFIGURATION DATA FOR PROGRAMMABLE LOGIC LEBOEUF, JEROME LARRY 2824 §103§112 Non-Final OA 61d Pending Feb 07, 2024
18135664 MULTIPLEXORS FOR NEURAL NETWORK ARRAY COON, BRADLEY SCOTT 2827 §112 Final Rejection 28d Pending Apr 17, 2023
18080676 ADJUSTABLE PROGRAMMING CIRCUIT FOR NEURAL NETWORK HO, HOAI V 2199 §102 Non-Final OA Pending Dec 13, 2022
18077993 OUTPUT CIRCUIT FOR ARTIFICIAL NEURAL NETWORK ARRAY BUI, KENNY KIM §103 Non-Final OA Pending Dec 08, 2022
17893071 Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network BERMUDEZ LOZADA, ALFREDO 2825 §102§103 Final Rejection 28d overdue Pending Aug 22, 2022
17847486 VECTOR-BY-MATRIX-MULTIPLICATION ARRAY UTILIZING ANALOG INPUTS DE LA GARZA, CARLOS HEBERTO 2182 §103 Final Rejection 7d Pending Jun 23, 2022
17848381 ARTIFICIAL NEURAL NETWORK COMPRISING REFERENCE ARRAY FOR ARRAY BIAS CONFIGURATION FEITL, LEAH M 2100 §103§112 Non-Final OA 4d overdue Pending Jun 23, 2022
17219352 DIGITAL OUTPUT MECHANISMS FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK MAI, LAM T 2845 §102 Non-Final OA Pending Mar 31, 2021

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