DETAILED ACTION
This action is responsive to the response filed 11 Oct 2023. Claims 1-10 and 21-30 are pending. Claims 1, 8 and 21 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Application Title
In accordance with MPEP 606.01 and MPEP 1302.04(a) to improve the descriptive nature of the application. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
“Programmable Control of Signal Characteristics of Output Pins of Integrated Circuit Memory Chips”
No action is required by the applicant. If an allowance is processed, the Examiner will change the name as part of the Examiner’s Amendment process.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 11 Oct 2023 has been entered.
Response to Arguments
Applicant’s arguments filed on 11 Oct 2023 have been fully considered. Applicant’s arguments are not persuasive in regards to the 35 USC § 102 and 35 USC § 103 rejections as the claim 21 are currently written.
Argument 1: Applicant states: “In at least some embodiments disclosed in the present application, a driver has registers directly connected to the driver to control the operations of the driver”… “Thus, claim 10 and its dependent claims are seen patentable.”
Response 1: Without agreeing with applicant’s argument, the examiner notes that claim 10 is allowed in this office action. The Examiner notes that the claim 10 limitation uses the phrase “connected” instead of the argued “directly connected”. Nearly all circuits of an IC package are considered to be “coupled” and interim pieces of a device that fall along the same conductivity line are typically considered “connected”, as taught by Matsumoto.
Argument 2: Applicant states: “Claim 1 is amended to include features similar to those recited in claim 25.”
Response 2: The Examiner notes that claim1 and dependent claims have been allowed in this office action.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 1-10 and 21-30 is/are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 1, 8 and 21 recite(s) the limitation “signals representative of data” or words to that effect. Claims 1, 8 and 22 later recite the limitation “first signals” or “the first signals”. It is indefinite as to whether these are the same signals, a subset of the signals, or different signals. Additionally, claim 1 uses the limitation of “the first signal” without an antecedent use of “a first signal”.
Claim(s) 2-7, 9-10 and 22-30 depend on rejected claim(s) 1, 8 and 21 and are also rejected under 35 U.S.C. 112(b).
Allowable Subject Matter
Claims 1-10, 23, 25, and 28 have been rejected under 35 USC 112(b) above. After correction of the 112(b) rejection, claims 1-10 would be allowable. Claims 23, 25 and 28 would be objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 21, 22, and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim, et al, U.S. Patent 10,204,670 (“Kim”).
Regarding claim 21, Kim teaches:
(Previously Presented) A method, comprising: connecting, via a set of pins of a device having registers enclosed within an integrated circuit package, (Kim, fig 2, “DQ, DQS_t, DQS_c, DM, CKE, CK_t, CK_c, CS_n, RAS_n, CAS_n, WE_n, AO-A17, BAO, BAl, BGO,BG1 configured to connect 1st circuits to 2nd circuits outside the IC package.”).
first circuits enclosed within the integrated circuit package to second circuits located outside of the integrated circuit package; (Kim, fig 2, 40, “any of the circuits inside MRAM array 12 connected to any of 405, 406, or 407 where 405-407 are “outside” circuits.”).
transmitting, by a driver enclosed within the integrated circuit package and programmable via one or more first settings received from a host system, to a first pin, among the pins, signals representative of data retrieved from memory cells enclosed within the integrated circuit package; and (Kim, fig 2, “driver is 27 of fig 2 is programmable (see arguments from final OA); 11:14-16, 15: 36-41, 17:6-7 describing a mode register, for controlling Command Latency (CL) by “user defined variables”; driver enclosed in IC and transmits to the first pin fig 2, DQ; among the pins, signals of data are retrieved from memory cells (10:52-57 - 11:1-11); while addressing memory cells 2:21 within IC package”).
storing, in the registers, the first settings for the driver based at least in part on signaling received from the host system, (Kim, fig 2, “fig 2: 15 registers; 17:4-8, 17: 38-43, 15: 36-41: describing a mode register set to a specific CL value and setting a mode register by “user defined variables”.”).
wherein the registers are connected to the driver; and operations of the driver are configured to be controlled by contents in the registers. (Kim, fig 13A, “fig 2: 15 registers within IC and programmable to store settings for the driver based on signaling received (17:4-8, 17: 38-43, 15: 36-41): describing a mode register set to a specific CL value and setting a mode register by “user defined variables”.”).
Regarding claim 22, Kim teaches:
(Previously Presented) The method of claim 21, wherein the registers include a first register programmable to store a first parameter; and (Kim, fig 13A, “the registers include a 1st register (fig 13A MR1); programmable to store 1st parameter (19:12-15 (describing “output drive strength”.))”).
the method further comprises: controlling, by the first parameter, a strength of first signals driven by the driver. (Kim, fig 2, “and strength of 1st signal (fig 2: any of n-bit data output from MRAM array 21; 10:52-57, 11:1-11) driven by the driver is controlled by the first the “first parameter”.”).
Regarding claim 26, Kim teaches:
(Currently Amended) The method of claim 22, wherein the registers further include a second register programmable to store a second parameter; and (Kim, fig 13A, “(fig 13A: MR1 and AL as 2nd parameter)”).
the method further comprises: controlling, by the second parameter, a delay between the first signals and a reference signal. (Kim, fig 2, “delay between 1st signals and ref signal (fig 1: CK) are controlled by 2nd parameter (19:30-36 describe how read command latency CL associated with data read from RMAM array 21 of fig 2.”).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of LaBerge, P., U.S. Patent 6,880,094 (“LaBerge”).
Kim teaches (Currently Amended) The method of claim 22.
Kim teaches further comprising: providing, by (Kim, fig 2, “Kim discloses the CAS latency (CL) in a mode register (17:38-40), but does not disclose the output drive strength is controlled by a DAC.”).
Kim does not explicitly teach a digital to analog converter of the device, an output to control the strength of the first signals.
LaBerge teaches a digital to analog converter of the device, an output to control the strength of the first signals. (LaBerge, fig 2, “1:8-9 a technique for selecting CAS latency in a memory device; 1:56-60, 6:26-31: a serial presence detect (SPD) device that stores information and translating the drive signal to a CAS latency by ADC converter.”).
In view of the teachings of LaBerge it would have been obvious for a person of ordinary skill in the art to apply the teachings of LaBerge to Kim before the effective filing date of the claimed invention in order to teach signaling between devices. The teachings of LaBerge, in the same or in a similar field of endeavor with Kim, can combine LaBerge’s more explicit signaling with an DAC with Kim’s less explicit signaling. The signaling with either method merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claims 27, 29, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Matsumoto, et al, U.S. Patent 6,714,461 (“Matsumoto”).
Regarding claim 27, Kim teaches (Previously Presented) The method of claim 26.
Kim teaches wherein the registers further include a third register programmable to store a third parameter; and (Kim, fig 2, “27 of fig 2; 11:14-16, 15: 36-41, 17:6-7 describing a mode register, for controlling CL by “user defined variables”; first pin fig 2, DQ, 10:52-57 - 11:1-11.”).
Kim does not explicitly teach the method further comprises: controlling, by the third parameter, a slew rate of the first signals.
Matsumoto teaches the method further comprises: controlling, by the third parameter, a slew rate of the first signals. (Matsumoto, fig 1, 2, “3:1-5, 6:25-29 A mode register for storing slew rate from the slew rate switching circuit 7 which sets SLWM to either slow rate or normal rate.”).
In view of the teachings of Matsumoto it would have been obvious for a person of ordinary skill in the art to apply the teachings of Matsumoto to Kim before the effective filing date of the claimed invention in order to teach signaling between devices. The teachings of Matsumoto, in the same or in a similar field of endeavor with Kim, can combine Matsumoto’s more explicit signaling with slew rate to set an optimum for the environment with Kim’s less explicit signaling. The signaling with either method merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 29, Kim, as modified by Matsumoto, teaches (Previously Presented) The method of claim 27.
Kim further teaches further comprising: storing, in second registers, second settings for a receiver connected to a second pin, among the pins. (Kim, fig 2, 17A, “a receiver (fig 2: 35) connected to more than 2 pins (DM pin) and second registers (fig 17A: MR5, fig 2: 36) which are programmable to store second settings for the receiver.”).
Regarding claim 30, Kim, as modified by Matsumoto, teaches (Previously Presented) The method of claim 29.
Kim further teaches further comprising: controlling, by the second settings, data detection based on characteristics of second signals received in the second pin, the characteristics including strength, delay, or slew rate, or any combination thereof. (Kim, fig 2, “second settings to control data detection (27:7-8) based on second signal characteristics received in second pin (29:66-30:4) describing logic “0” or “1” on A10 bit; the characteristics including at least strength, delay, slew rate, or combinations of these; 30: 8-19 describes DM latency.”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
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