DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-4, 7-11, 13, 15-18, 20, 22-25, 27 and 36-37 are pending in this office action and presented for examination. Claims 1, 4, 8, 11, 15, 18, 20, 22, and 25 are newly amended; claims 5-6, 12, 14, 19, 21, 26, 28 are newly cancelled; and claims 36-37 are withdrawn by the response received May 14, 2026.
Examiner notes that in claim 25, line 3, a space appears to have been inadvertently deleted between “for” and “a”.
Examiner notes that in claim 25, line 4, a space appears to have been inadvertently deleted between “for” and “a”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-11, 13, 15-18, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation “the execution circuitry” in line 15 (with a following previously-recited limitation “hardware” newly deleted). However, there is insufficient antecedent basis for this limitation in the claims, and it is further indefinite as to whether this execution circuitry is the same as, or different from, “execution circuitry hardware” in claim 8, lines 9-10.
Claims 9-11 and 13 are rejected for failing to alleviate the rejection of claim 8 above.
Claim 15 recites the limitation “execution circuitry that comprises logical AND circuitry and logical OR circuitry” in lines 18-19. However, it is indefinite as to whether this execution circuitry is the same as, or different from, “execution circuitry” as recited in claim 15, line 11.
Claims 16-18 and 20 are rejected for failing to alleviate the rejection of claim 15 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7-11, 13, 15-18, 20, 22-25, and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bradbury et al. (Bradbury) (US 20140208077 A1) in view of Abali et al. (Abali) (US 20160085721 A1) in view of Pasca et al. (Pasca) (US 20190042193 A1).
Consider claim 1, Bradbury discloses an apparatus (for example, [0215], line 7, host system; [0215], line 6, processor; [0224], line 2, processor; [0217], line 3, system 520; [0217], line 4, base computer system 5021) comprising: decode circuitry hardware to decode ([0227], line 4, dispatch unit decodes the instruction(s)) an instance of a single instruction ([0067], lines 2-3, Vector Floating Point Test Data Class Immediate (VFTCI) instruction)) into a decoded instruction ([0227], line 4, dispatch unit decodes the instruction(s)), the instance of the single instruction to include one or more fields for an opcode ([0067], lines 4-8, the Vector Floating Point Test Data Class Immediate instruction 400 includes opcode fields 402a (e.g., bits 0-7), 402b (e.g., bits 40-47) indicating a Vector Floating Point Test Data Class Immediate operation), one or more fields for an identification of a location of a packed data source operand ([0067], lines 9-11, a second vector register field 406 (e.g., bits 12-15) used to designate a second vector register (V.sub.2); [0092], lines 3-5, the value in element Ei, which in this case is element 0, is extracted from the second operand of the instruction (e.g., from the operand stored in the register designated by V.sub.2)), an immediate ([0067], lines 11-12, an immediate field (I.sub.3) 408 (e.g., bits 16-27) to include a bitmask) to bit-wise indicate one or more classification checks to perform ([0069], lines 4-6, I.sub.3 408 includes a bit mask having a plurality of bits, and each bit is used to represent a binary floating point element class and a sign (positive or negative); [0074], lines 1-10, as indicated herein, the 12 bits of the third operand, bits 16-27 of the instruction text, are used to specify 12 combinations of BFP data class and sign. In one example, as shown in FIG. 4B, BFP operand elements are divided into six classes 430: zero, normal number, subnormal number, infinity, quiet NaN (Not-a-Number), and signaling NaN, and each class has a sign 432 (either positive or negative) associated therewith. Thus, for instance, bit 0 of I.sub.3 specifies a zero class with a positive sign, and bit 1 specifies a zero class with a negative sign, etc.; [0073], lines 1-11, in execution of one embodiment of the Vector Floating Point Test Data Class Immediate instruction, the class and sign of the floating point element or elements of the second operand are examined to select one or more bits from the third operand. If a selected bit is set, all bit positions of the corresponding element in the first operand are set to ones; otherwise, they are set to zero. That is, if the class/sign of the floating point number contained in an element of the second operand matches a set bit (i.e., a bit set to, e.g., one) in the third operand, then an element of the first operand corresponding to the element of the second operand is set to ones), and one or more fields for an identification of a packed data destination operand ([0067], lines 8-9, a first vector register field 404 (e.g., bits 8-11) used to designate a first vector register (V.sub.1); [0073], lines 1-11, in execution of one embodiment of the Vector Floating Point Test Data Class Immediate instruction, the class and sign of the floating point element or elements of the second operand are examined to select one or more bits from the third operand. If a selected bit is set, all bit positions of the corresponding element in the first operand are set to ones; otherwise, they are set to zero. That is, if the class/sign of the floating point number contained in an element of the second operand matches a set bit (i.e., a bit set to, e.g., one) in the third operand, then an element of the first operand corresponding to the element of the second operand is set to ones), wherein the opcode is to indicate that execution circuitry hardware is to perform ([0227], lines 6-10, an execution unit 5057 will typically receive information about decoded arithmetic instructions from the instruction fetch unit 5055 and will perform arithmetic operations on operands according to the opcode of the instruction), for each data element position of the packed data source operand ([0071], lines 6-7, if bit 0 is set to zero, the operation occurs on all elements in the vector), a classification of a data element according to the indicated one or more classification checks and a logical OR of each classification check result to generate a result ([0073], lines 1-11, in execution of one embodiment of the Vector Floating Point Test Data Class Immediate instruction, the class and sign of the floating point element or elements of the second operand are examined to select one or more bits from the third operand. If a selected bit is set, all bit positions of the corresponding element in the first operand are set to ones; otherwise, they are set to zero. That is, if the class/sign of the floating point number contained in an element of the second operand matches a set bit (i.e., a bit set to, e.g., one) in the third operand, then an element of the first operand corresponding to the element of the second operand is set to ones), and store the result of the classification in a corresponding data element position of the packed data destination operand ([0073], lines 1-11, in execution of one embodiment of the Vector Floating Point Test Data Class Immediate instruction, the class and sign of the floating point element or elements of the second operand are examined to select one or more bits from the third operand. If a selected bit is set, all bit positions of the corresponding element in the first operand are set to ones; otherwise, they are set to zero. That is, if the class/sign of the floating point number contained in an element of the second operand matches a set bit (i.e., a bit set to, e.g., one) in the third operand, then an element of the first operand corresponding to the element of the second operand is set to ones); and the execution circuitry hardware, the execution circuitry hardware to execute the decoded instruction according to the opcode ([0227], lines 6-10, an execution unit 5057 will typically receive information about decoded arithmetic instructions from the instruction fetch unit 5055 and will perform arithmetic operations on operands according to the opcode of the instruction), wherein the execution circuitry hardware comprises logical AND circuitry and logical OR circuitry ([0228], lines 9-12, the ALU performs arithmetic operations such as add, subtract, multiply and divide as well as logical function such as and, or and exclusive-or (XOR), rotate and shift; [0230], lines 4-8, the execution unit preferably utilizes an Arithmetic Logic Unit (ALU) 5066 that is capable of performing a variety of logical functions such as Shift, Rotate, And, Or and XOR as well as a variety of algebraic functions including any of add, subtract, multiply, divide).
To any extent to which it may be argued that Bradbury does not explicitly or implicitly disclose a “logical OR” being performed via the disclosure at paragraph [0073], lines 1-11, Examiner nevertheless cites, for the purposes of compact prosecution, Abali, which explicitly discloses using a logical OR to determine a result based on whether any given intermediate result of multiple intermediate results has met a criterion ([0075], lines 12-19). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Abali with the invention of Bradbury in order to efficiently implement the cited behavior of Bradbury. Alternatively, this modification merely entails combining prior art elements (the prior art elements of Bradbury as cited above, and the teaching of Abali as cited above) according to known methods (Examiner submits that the behavior and use of a logical OR is known, as reflected by the teaching of Abali) to yield predictable results (the invention of Bradbury, implemented using a logical OR), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
However, the combination thus far does not entail the data element being a BF16 data element in particular.
On the other hand, Pasca discloses a data element being a BF16 data element in particular ([0003], line 4, bfloat16 format).
Pasca’s teaching is beneficial in machine learning applications (Pasca, [0003], lines 11-14).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Pasca with the combination of Bradbury and Abali in view of its benefits in machine learning applications. Alternatively, this modification merely entails combining prior art elements (the prior art elements of the combination of Bradbury and Abali as cited above, and the teaching of Pasca as cited above) according to known methods (as Pasca notes in [0003], lines 1-2, integrated circuits may represent variables according to a number of different formats) to yield predictable results (the combination of Bradbury and Abali, wherein the data element is a BF16 data element in particular), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 2, the overall combination entails the apparatus of claim 1 (see above), wherein the one or more fields for the identification of the location of the packed data source operand is to identify a vector register (Bradbury, [0067], lines 9-11, a second vector register field 406 (e.g., bits 12-15) used to designate a second vector register (V.sub.2); [0092], lines 3-5, the value in element Ei, which in this case is element 0, is extracted from the second operand of the instruction (e.g., from the operand stored in the register designated by V.sub.2)).
Consider claim 3, the overall combination entails the apparatus of claim 1 (see above), wherein the one or more fields for the identification of the location of the packed data source operand is to identify a memory location (Bradbury, [0067], lines 9-11, a second vector register field 406 (e.g., bits 12-15) used to designate a second vector register (V.sub.2); [0092], lines 3-5, the value in element Ei, which in this case is element 0, is extracted from the second operand of the instruction (e.g., from the operand stored in the register designated by V.sub.2); alternatively, [0188], lines 1-6, additionally, in further embodiments, contents of one or more fields of an instruction may be provided in a general purpose register, in memory, in an element of a vector register (differing per element) or from an address computation, as examples. They may be included as an explicit operand of the instruction or as an implied operand or input; Examiner notes that, to any extent to which Bradbury does not disclose the limitation via the aforementioned citations, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the one or more fields to identify a memory location in order to increase the capability and flexibility of the instruction; Examiner further notes that such a modification merely entails combining prior art elements (the instruction of Bradbury, and the identification of a memory location of Bradbury) according to known methods (Examiner submits that identifying a memory location that holds input data is known, as reflected by Bradbury) to yield predictable results (the combination of Bradbury and Abali, wherein the one or more fields is to identify a memory location), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143).
Consider claim 4, the overall combination entails the apparatus of claim 1 (see above), wherein the one or more classification checks is one or more of a check for a quiet not-a-number (QNAN) value, a check for a signaling not-a-number (SNAN) value, a check for a positive zero value, a check for a negative zero value, a check for a positive infinity value, a check for a negative infinity value, a check for a denormal value, or a check for a finite negative value (Bradbury, [0074], lines 1-10, as indicated herein, the 12 bits of the third operand, bits 16-27 of the instruction text, are used to specify 12 combinations of BFP data class and sign. In one example, as shown in FIG. 4B, BFP operand elements are divided into six classes 430: zero, normal number, subnormal number, infinity, quiet NaN (Not-a-Number), and signaling NaN, and each class has a sign 432 (either positive or negative) associated therewith. Thus, for instance, bit 0 of I.sub.3 specifies a zero class with a positive sign, and bit 1 specifies a zero class with a negative sign, etc.).
Consider claim 7, the overall combination entails the apparatus of claim 1 (see above), wherein the instance of the single instruction is to further include one or more fields for a writemask (Bradbury, [0067], lines 12-14, a first mask field (M.sub.5) 410 (e.g., bits 28-31); a second mask field (M.sub.4) 412 (e.g., bits 32-35)) register (Bradbury, [0188], lines 1-6, additionally, in further embodiments, contents of one or more fields of an instruction may be provided in a general purpose register, in memory, in an element of a vector register (differing per element) or from an address computation, as examples. They may be included as an explicit operand of the instruction or as an implied operand or input; Examiner notes that, to any extent to which Bradbury does not disclose the limitation via the aforementioned citations, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the one or more fields to be for a writemask register in order to free up instruction space otherwise dedicated to writemask data and to enable dynamic writemasks; Examiner further notes that such a modification merely entails combining prior art elements (the instruction of Bradbury, and the identification of a register of Bradbury) according to known methods (Examiner submits that identifying a register that holds input data is known, as reflected by Bradbury) to yield predictable results (the combination of Bradbury and Abali, wherein the one or more fields is to identify a writemask register), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143).
Claims 8-11 and 13 are directed to a system embodiment that is analogous to the apparatus embodiment of claims 1-4 and 7 respectively; however, claim 8 (and claims 9-11 and 13 by dependency) further recite a memory to store the instance of the single instruction. However, Bradbury further discloses a memory to store the instance of the single instruction ([0207], lines 22-24, an instruction is fetched from memory 5002 by an instruction fetch unit 5004 via a cache 5009). Aside from this further limitation that is taught by the primary reference, the remaining limitations of claims 8-11 and 13 are disclosed or rendered obvious in an analogous manner as in claims 1-4 and 7 above.
Claims 15-18 and 20 are directed to “[a] non-transitory machine-readable medium storing at least an instance of a particular single instruction, wherein the instance of the particular single instruction is to be processed by a processor by performing a method comprising” that is analogous to the apparatus embodiment of claims 1-4 and 7 respectively; however, Bradbury further discloses such a non-transitory machine-readable ([0207], lines 22-24, an instruction is fetched from memory 5002 by an instruction fetch unit 5004 via a cache 5009; [0216], lines 4-17, Program code is normally paged from storage media device 5011 to the relatively higher-speed computer storage 5002 where it is available for processing by processor 5001. The techniques and methods for embodying software program code in memory, on physical media, and/or distributing software code via networks are well known and will not be further discussed herein. Program code, when created and stored on a tangible medium (including but not limited to electronic memory modules (RAM), flash memory, Compact Discs (CDs), DVDs, Magnetic Tape and the like is often referred to as a "computer program product". The computer program product medium is typically readable by a processing circuit preferably in a computer system for execution by the processing circuit) and processor ([0224], line 2, processor). Aside from this further limitation that is taught by the primary reference, the remaining limitations of claims 15-18 and 20 are disclosed or rendered obvious in an analogous manner as in claims 1-4 and 7 above.
Claims 22-25 and 27 are directed to a non-transitory machine-readable medium embodiment that is analogous to the non-transitory machine-readable medium embodiment of claims 15-18 and 20 respectively (except that claim 22 does not recite circuitry that comprises logical AND circuitry and logical OR circuitry, as claim 15 does); however, claim 22 (and claims 23-25 and 27 by dependency) further recite translating the particular single instruction from a first instruction set architecture to one or more instructions of a second, different instruction set architecture for decoding and executing. However, Bradbury further discloses translating the particular single instruction from a first instruction set architecture to one or more instructions of a second, different instruction set architecture for decoding and executing ([0052], lines 1-7, in one example, a guest instruction 250 that is obtained, translated and executed is an instruction described herein. The instruction, which is of one architecture (e.g., the z/Architecture) is fetched from memory, translated and represented as a sequence of native instructions 256 of another architecture (e.g., PowerPC, pSeries, xSeries, Intel, etc.). These native instructions are then executed; [0048], lines 13-19, it also includes an instruction translation routine 254 to determine the type of guest instruction that has been obtained and to translate the guest instruction into one or more corresponding native instructions 256. This translation includes, for instance, identifying the function to be performed by the guest instruction and choosing the native instruction(s) to perform that function). Aside from this further limitation that is taught by the primary reference, the remaining limitations of claims 22-25 and 27 are disclosed or rendered obvious in an analogous manner as in claims 15-18 and 20 above.
Response to Arguments
Applicant on page 10 argues: “The Examiner objected to claims 4, 11, and 25. Applicant has amended these claims.”
In view of the aforementioned amendments, the associated previously presented objections are withdrawn.
Applicant on page 10 argues: ‘Claims 8-14 stand rejected under 35 U.S.C. § 101 because the claimed invention is allegedly directed to non-statutory subject matter. Applicant has added "hardware" although a PHOSITA would not understand RTL, etc. to be circuitry.’
In view of the aforementioned amendment, the associated previously presented rejection under 35 U.S.C. § 101 is withdrawn.
Applicant on page 10 argues: “With respect to claims 1, 8, 15, and 22, support for the non-opcode classification checks can be at least found in FIG. 4 and IMM8.”
In view of various amendments (e.g., the deletion of “one or more” language), the associated previously presented written description rejections are withdrawn.
Applicant on page 10 argues: “Applicant has amended several claims.”
In view of the aforementioned amendments, most previously presented indefinite rejections are withdrawn. However, two indefinite rejections do not appear to be wholly overcome — see the Claim Rejections - 35 USC § 112 section above.
Applicant across pages 11-12 argues that the previously presented prior art combination does not describe amended claim 1.
In view of the amendments to the independent claims, Examiner is newly relying upon additional prior art — see the Claim Rejections - 35 USC § 103 section above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KEITH E VICARY/ Primary Examiner, Art Unit 2183
Prosecution Insights