DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 30, 2025, has been entered.
Claims 1-28 and 36-37 are pending in this office action and presented for examination. Claims 1-4, 8-11, 15-18, and 22-25 are newly amended; claims 29-35 are newly cancelled; and claims 36-37 are newly added by the RCE received June 30, 2025.
Election/Restrictions
Newly submitted claims 36-37 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
The invention of claim 36 (directed to a VGETMANNEPBF16 instruction; see FIG. 9-11) and the invention of claims 1-28 (directed to a FPCLASSNEPBF16 instruction; see FIG. 2-4) are related as subcombinations disclosed as usable together in a single combination. The subcombinations are distinct if they do not overlap in scope and are not obvious variants, and if it is shown that at least one subcombination is separately usable. In the instant case, the invention of claim 36 can be used without also using the invention of claims 1-28, and the invention of claims 1-28 can be used without also using the invention of claim 36. See MPEP § 806.05(d).
The invention of claim 37 (directed to a VGETEXPNEPBF16 instruction; see FIG. 5-8) and the invention of claims 1-28 (directed to a FPCLASSNEPBF16 instruction; see FIG. 2-4) are related as subcombinations disclosed as usable together in a single combination. The subcombinations are distinct if they do not overlap in scope and are not obvious variants, and if it is shown that at least one subcombination is separately usable. In the instant case, the invention of claim 37 can be used without also using the invention of claims 1-28, and the invention of claims 1-28 can be used without also using the invention of claim 37. See MPEP § 806.05(d).
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 36-37 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Specification
The disclosure is objected to because of the following informalities. Appropriate correction is required.
In paragraph [0050] as amended on January 10, 2025, the deletion of “extract” in conjunction with the addition of “that” causes the last sentence of the paragraph to have no grammatical predicate. Examiner recommends further amending the paragraph to delete “that”.
Claim Objections
Claims 4, 11, and 25 are objected to because of the following informalities. Appropriate correction is required.
In claim 4, line 4, “a check for negative infinity value” should be “a check for a negative infinity value” for grammatical clarity.
In claim 11, line 4, “a check for negative infinity value” should be “a check for a negative infinity value” for grammatical clarity.
In claim 25, line 4, “a check for negative infinity value” should be “a check for a negative infinity value” for grammatical clarity.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-28 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitation “the instance of the single instruction to include … one or more non-opcode fields for an indication of one or more classification checks to perform” in lines 3-6. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0034]) does not appear to provide support for the instance of the single instruction including “one or more” non-opcode fields for an indication of one or more classification checks to perform.
Claims 2-7 are rejected for failing to alleviate the rejection of claim 1 above.
Claim 8 recites the limitation “the instance of the single instruction to include … one or more non-opcode fields for an indication of one or more classification checks to perform” in lines 4-7. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0034]) does not appear to provide support for the instance of the single instruction including “one or more” non-opcode fields for an indication of one or more classification checks to perform.
Claims 9-14 are rejected for failing to alleviate the rejection of claim 8 above.
Claim 15 recites the limitation “the instance of the particular single instruction to include … one or more non-opcode fields for an indication of one or more classification checks to perform” in lines 4-8. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0034]) does not appear to provide support for the instance of the single instruction including “one or more” non-opcode fields for an indication of one or more classification checks to perform.
Claims 16-21 are rejected for failing to alleviate the rejection of claim 15 above.
Claim 22 recites the limitation “the particular single instruction to include … one or more non-opcode fields for an indication of one or more classification checks to perform” in lines 5-9. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0034]) does not appear to provide support for the particular single instruction including “one or more” non-opcode fields for an indication of one or more classification checks to perform.
Claims 23-28 are rejected for failing to alleviate the rejection of claim 22 above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the execution circuitry hardware to execute the decoded instruction according to the opcode” in lines 13-14. However, there is insufficient antecedent basis for this limitation in the claims. For the purposes of prior art analysis, Examiner is interpreting this limitation as “the execution circuitry hardware, the execution circuitry hardware to execute the decoded instruction according to the opcode”.
Claim 1 recites the limitation “execution circuitry hardware is” in lines 7-8. Claim 1 further recites the limitation “execution circuitry hardware comprise” in line 14. Therefore, it is indefinite as to whether execution circuitry hardware is to be interpreted as a singular noun or a plural noun.
Claims 2-7 are rejected for failing to alleviate the rejections of claim 1 above.
Claim 8 recites the limitation “the execution circuitry to execute the decoded instruction according to the opcode” in line 15. However, there is insufficient antecedent basis for this limitation in the claims. For the purposes of prior art analysis, Examiner is interpreting this limitation as “the execution circuitry, the execution circuitry to execute the decoded instruction according to the opcode”.
Claim 8 recites the limitation “the execution circuitry hardware” in lines 13-14. However, there is insufficient antecedent basis for this limitation in the claims, and it is further indefinite as to whether the execution circuitry of this limitation is the same as, or different from, “execution circuitry” as recited in claim 8, lines 8-9 and 15. Examiner also notes that the claim as recites does not appear to necessitate that the recited system comprises the execution circuitry hardware.
Claim 8 recites the limitation “execution circuitry is” in lines 8-9. Claim 8 further recites the limitation “execution circuitry hardware comprise” in lines 13-14. Therefore, it is indefinite as to whether execution circuitry hardware is to be interpreted as a singular noun or a plural noun.
Claims 9-14 are rejected for failing to alleviate the rejections of claim 8 above.
Claim 15 recites the limitation “the decoded instructions of the of the particular single instruction” in line 15. However, there is insufficient antecedent basis for this limitation in the claims. In addition, it is unclear as to whether there is an entity missing between the two instances of “of the”.
Claim 15 recites the limitation “circuitry” in line 16. However, it is indefinite as to whether this circuitry is the same as, or different from, “execution circuitry” as recited in claim 15, lines 9-10.
Claims 16-21 are rejected for failing to alleviate the rejections of claim 15 above.
Claim 18 recites the limitation “the one or more classification checks to perform is one or more of quiet not-a-number (QNAN), signaling not-a-number (SNAN), positive zero, negative zero, positive infinity, negative infinity, denormal, or finite negative” in lines 1-4. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to how a classification check itself can be one or more of quiet non-a-number (QNAN), signaling not-a-number (SNAN), positive zero, negative zero, positive infinity, negative infinity, denormal, or finite negative. For example, claim 15, line 8, in conjunction with claim 18 appears to convey “‘one or more of quiet non-a-number (QNAN), signaling not-a-number (SNAN), positive zero, negative zero, positive infinity, negative infinity, denormal, or finite negative’ to perform”, and it is indefinite as to what it means to “perform” a positive infinity, for example.
Claim 20 recites the limitation “the instance of the single instruction” in line 2. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 20 recites the limitation “the single instruction” in line 2. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 22 recites the limitation “a second, different instruction set architecture” in lines 18-19. However, it is indefinite as to whether this second, different instruction set architecture is the same as or different from “a second, different instruction set architecture” as recited in claim 22, line 5. For the purposes of prior art analysis, Examiner is interpreting this limitation as “the second, different instruction set architecture”.
Claims 23-28 are rejected for failing to alleviate the rejection of claim 22 above.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 8-14 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claim(s) can be interpreted as software per se and thus can be made without an actual hardware apparatus. While the claim(s) do recite circuitry, paragraph [00160] discloses: “Accordingly, embodiments of the disclosure may also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.” In addition, paragraph [00157] discloses “Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches”. As such, Examiner recommends inserting the limitation “hardware” in an appropriate part of the claim and all relevant places in further dependent claims (e.g., replacing the limitation “decode circuitry” with the limitation “hardware decode circuitry”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 8-11, and 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zbiciak et al. (Zbiciak) (US 20200371794 A1) in view of Moudgill et al. (Moudgill) (US 20160224512 A1) in view of Moyer et al. (Moyer) (US 20080040591 A1) in view of Pasca et al. (Pasca) (US 20190042193 A1).
Consider claim 1, Zbiciak discloses an apparatus comprising: decode circuitry hardware to decode ([0028], lines 1-2, instruction decode unit 113 decodes each instruction) an instance of a single instruction ([0094], line 1, vector floating-point classification instruction) into a decoded instruction ([0028], lines 1-2, instruction decode unit 113 decodes each instruction), the instance of the single instruction to include one or more fields for an opcode ([0094], line 5, opcode field), one or more fields for an identification of a location of a packed data source operand ([0094], lines 1-4, a vector floating-point classification instruction contains fields that specify the source register 1402, 1422 and the destination register 1404, 1424 (e.g., in the global vector register file 231); [0089], lines 6-7, the source register 1402 and the destination; [0090], line 1, register 1404 are 512-bit vector registers), and one or more fields for an identification of a packed data destination operand ([0094], lines 1-4, a vector floating-point classification instruction contains fields that specify the source register 1402, 1422 and the destination register 1404, 1424 (e.g., in the global vector register file 231); [0089], lines 6-7, the source register 1402 and the destination; [0090], line 1, register 1404 are 512-bit vector registers), wherein the opcode is to indicate that execution circuitry hardware ([0030], lines 9-10, plural functional units; [0109], lines 13-14, which in this case is the L1 unit 221 or the S1 unit 222) is to perform, for each data element position of the packed data source operand, a classification of a data element according to one or more classification checks and store a result of the classification in a corresponding data element position of the packed data destination operand ([0095], lines 1-9, in response to executing the vector floating-point classification instruction, the DSP 100 classifies each floating-point value in the various lanes (either single precision or double precision) of the source register 1402, 1422. As a result of the classification of floating-point values in the lanes of the source register 1402, 1422, the DSP 100 identifies type of the floating-point value and stores a value indicative of the identified type in a corresponding lane of the destination register 1404, 1424); and the execution circuitry hardware to execute the decoded instruction according to the opcode ([0028], lines 10-13, the result of this decoding is signals for control of the target functional unit to perform the data processing operation specified by the corresponding instruction on the specified data), wherein the execution circuitry hardware comprise logical AND circuitry ([0050], lines 16-17, AND a bitwise AND of data) and logical OR circuitry ([0050], lines 18-19, OR a bitwise OR of data).
However, Zbiciak does not disclose that the single instruction includes one or more non-opcode fields for an indication of the aforementioned one or more classification checks to perform, and performing a logical OR of each classification check result to generate the result. Zbiciak also does not disclose that the data element is a BF16 data element.
On the other hand, Moudgill discloses an instruction including one or more fields for an indication of one or more classification checks to perform ([0297], lines 1-6, embodiments may also include an instruction, vclassf_class$n0,$m1,$v2 that tests the floating point class of each element of the vector $v2, and sets the corresponding in $m1 based on whether it is a member of the class(es) specified by the class field in the instruction), and performing a logical OR of each classification check result to generate a result ([0303], lines 1-3, the class instruction modifier can allow the instruction to test for combinations of classes, as well, such as Normal+Zero, Normal+Zero+Subnormal, etc; [0410], lines 1-2, Vector mask registers, written as $mN, which contain vectors of single bits; Examiner submits that one of ordinary skill in the art before the effective filing date of the claimed invention would understand the instruction to entail a logical OR, since, for example, an AND of a Normal and a Subnormal would always result in a zero given that an element cannot be both normal and subnormal, and therefore would convey no classification information about the input data. Examiner also generally notes that a logical OR is a basic building block used when it is desired to determine when any of various inputs is true). (Moudgill also discloses logical AND circuitry and logical OR circuitry in paragraphs [0166]-[0167].)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Moudgill with the invention of Zbiciak in order to increase customizability and capability. Alternatively, this modification merely entails combining prior art elements (the prior art elements of Zbiciak as cited above, and the teaching of Moudgill as cited above) according to known methods (Moudgill teaches including one or more fields for an indication of one or more functions to perform in the particular field of classification checks for floating point elements; as such, the application of Moudgill’s teaching into the analogous environment of Zbiciak is known. Examiner also submits that a logical OR is a known method) to yield predictable results (for example, the invention of Zbiciak, wherein the instruction includes one or more fields for an indication of the aforementioned one or more classification checks to perform, and performing a logical OR of each classification check result to generate a result), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Moreover, to any extent to which Moudgill does not disclose that the one or more fields for an indication of one or more classification checks to perform are one or more non-opcode fields in particular, via Moudgill’s disclosure in paragraph [0297], line 5, of “class field in the instruction”), Moyer discloses the well-known concept of implementing two different instruction behaviors using a particular opcode and a behavior specifier in a non-opcode field rather than two separate opcodes ([0026], last 11 lines; FIG. 3, which shows the specifier 50 being distinct from the opcode 42).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Moyer with the combination of Zbiciak and Moudgill in order to save opcode space. Alternatively, this modification merely entails combining prior art elements (the prior art elements of the combination of Zbiciak and Moudgill, and Moyer’s prior art element of using a non-opcode field to specify behavior) according to known methods (Moyer as cited explicitly teaches the method, and Examiner further generally submits that use of non-opcode fields to specify behavior of an instruction is known) to yield predictable results (the combination of Zbiciak and Moudgill, wherein the one or more fields for an indication of one or more classification checks to perform are one or more non-opcode fields in particular), which is an example of a rationale that may support a conclusion of obviousness, as set forth in MPEP 2143.
However, the combination thus far does not entail the data element being a BF16 data element in particular.
On the other hand, Pasca discloses a data element being a BF16 data element in particular ([0003], line 4, bfloat16 format).
Pasca’s teaching is beneficial in machine learning applications (Pasca, [0003], lines 11-14).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Pasca with the combination of Zbiciak, Moudgill, and Moyer in view of its benefits in machine learning applications. Alternatively, this modification merely entails combining prior art elements (the prior art elements of Zbiciak, Moudgill, and Moyer as cited above, and the teaching of Pasca as cited above) according to known methods (As Pasca notes in [0003], lines 1-2, integrated circuits may represent variables according to a number of different formats) to yield predictable results (the combination of Zbiciak, Moudgill, and Moyer, wherein the data element is a BF16 data element in particular), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 2, the overall combination entails the apparatus of claim 1 (see above), wherein the one or more fields for the identification of the location of the packed data source operand is to identify a vector register (Zbiciak, [0094], lines 1-4, a vector floating-point classification instruction contains fields that specify the source register 1402, 1422 and the destination register 1404, 1424 (e.g., in the global vector register file 231; Moudgill, [0297], line 2, $v2).
Consider claim 3, the overall combination entails the apparatus of claim 1 (see above), wherein the one or more fields for the identification of the location of the packed data source operand is to identify a memory location (Zbiciak, [0094], lines 1-4, a vector floating-point classification instruction contains fields that specify the source register 1402, 1422 and the destination register 1404, 1424 (e.g., in the global vector register file 231; Moudgill, [0297], line 2, $v2).
Consider claim 4, the overall combination entails the apparatus of claim 1, wherein the one or more classification checks is one or more of a check for a quiet not-a-number (QNAN) value, a check for a signaling not-a-number (SNAN) value, a check for a positive zero value, a check for a negative zero value, a check for a positive infinity value, a check for negative infinity value, a check for a denormal value, or a check for a finite negative value (Zbiciak, [0096], lines 1-4, floating-point values may be classified as a zero value, a subnormal value, a normal value, an infinity value, or a NaN value (being either a QNaN or SNaN); Moudgill, [0298], lines 1-2, Not-a-Number (NaN); this can be further divided into quiet NaNs (qNaN) or signaling NaNs (sNaN); [0299], line 1, Infinity; [0300], line 1, Zero; [0301], line 1, Subnormal).
Claims 8-11 are directed to a system embodiment that is analogous to the apparatus embodiment of claims 1-4 respectively; however, claim 8 (and claims 9-11 by dependency) further recite a memory to store the instance of the single instruction. However, Zbiciak further discloses a memory to store the instance of the single instruction ([0024], lines 3-4, level one instruction cache). Aside from this further limitation that is taught by the primary reference, the remaining limitations of claims 8-11 are disclosed or rendered obvious in an analogous manner as in claims 1-4 above.
Claims 15-18 are directed to “[a] non-transitory machine-readable medium storing at least an instance of a particular single instruction, wherein the instance of the particular single instruction is to be processed by a processor by performing a method comprising” that is analogous to the apparatus embodiment of claims 1-4 respectively; however, Zbiciak further discloses such a non-transitory machine-readable embodiment ([0024], lines 3-4, level one instruction cache) and processor ([0024], line 3, processor). Aside from this further limitation that is taught by the primary reference, the remaining limitations of claims 15-18 are disclosed or rendered obvious in an analogous manner as in claims 1-4 above.
Claim(s) 5-6, 12, 14, 19, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zbiciak, Moudgill, Moyer, and Pasca as applied to claims 1, 8, and 15 above, and further in view of Uhler et al. (Uhler) (US 5500947).
Consider claim 5, the combination thus far entails the apparatus of claim 1 (see above). In addition, to any extent to which the combination thus far does not entail the one or more classification checks to perform is to be provided by an immediate, Uhler explicitly discloses specifying an operand by an immediate (col. 3, lines 5-8, the simplest method of specifying an operand in a machine-level instruction is immediate or literal addressing, in which the value of the operand is included in the machine-level instruction itself). Uhler’s teaching results in simplicity (Uhler, col. 3, line 5) and forgoes the need for main memory access (Uhler, col. 3, lines 10-11). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Uhler with the combination of Zbiciak, Moudgill, Moyer, and Pasca in order to result in simplicity and forgo the need for main memory access.
Consider claim 6, the combination thus far entails the apparatus of claim 1 (see above). In addition, to any extent to which the combination thus far does not entail the one or more classification checks to perform is to be provided by an identified register, Uhler explicitly discloses specifying an operand by an identified register (col. 3, lines 11-14, a register addressing mode requires no main memory accesses, since the operand is stored in a CPU register which is specified in the machine-level instruction). Uhler’s teaching forgoes the need for main memory access (Uhler, col. 3, lines 11-14). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Uhler with the combination of Zbiciak, Moudgill, Moyer, and Pasca in order to forgo the need for main memory access.
Claims 12 and 14 are rejected for the same reasons as claims 5-6 above, respectively.
Claims 19 and 21 are rejected for the same reasons as claims 5-6 above, respectively.
Claim(s) 7, 13, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zbiciak, Moudgill, Moyer, and Pasca as applied to claims 1, 8, and 15 above, and further in view of Brown et al. (Brown) (US 20180004514 A1).
Consider claim 7, the combination thus far entails the apparatus of claim 1 (see above), but does not disclose the instance of the single instruction is to further include one or more fields for a writemask register.
On the other hand, Brown discloses an instance of a single instruction is to further include one or more fields for a writemask register ([0053], line 2, writemask register operand).
Brown’s teaching is used to conditionally control per-element operations and updating of results (Brown, [0053], lines 2-4), which increases processor capability.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Brown with the combination of Zbiciak, Moudgill, Moyer, and Pasca in order to increase processor capability. Alternatively, this modification merely entails combining prior art elements (the prior art elements of Zbiciak, Moudgill, Moyer, and Pasca as cited above, and the teaching of Brown as cited above) according to known methods (Examiner submits that masking is well-known; for example, the CPC area G06F9/30038 is directed to such masking) to yield predictable results (the combination of Zbiciak, Moudgill, Moyer, and Pasca, further supporting writemasking), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Claim 13 is rejected for the same reason as claim 7 above.
Claim 20 is rejected for the same reason as claim 7 above.
Claim(s) 22-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zbiciak et al. (Zbiciak) (US 20200371794 A1) in view of Moudgill et al. (Moudgill) (US 20160224512 A1) in view of Moyer et al. (Moyer) (US 20080040591 A1) in view of Pasca et al. (Pasca) (US 20190042193 A1) in view of Dang et al. (Dang) (US 20190114173 A1).
Claims 22-25 are directed to a non-transitory machine-readable medium embodiment that is analogous to the non-transitory machine-readable medium embodiment of claims 15-18 respectively (except that claim 22 does not recite circuitry that comprises logical AND circuitry and logical OR circuitry, as claim 15 does); however, claims 22-25 further recite translating the particular single instruction from a first instruction set architecture to one or more instructions of a second, different instruction set architecture. On the other hand, Dang discloses translating the particular single instruction from a first instruction set architecture to one or more instructions of a second, different instruction set architecture ([0016], lines 10-12, a translator may translate the first hardware instructions of the first ISA to compatible second hardware instructions of the second ISA). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Dang with the combination of Zbiciak, Moudgill, Moyer, and Pasca, in view of the desirability of executing an application that was compiled for processors having a first ISA on a processor having a second ISA (Dang, [0016], lines 1-3). Aside from this further limitation that is rendered obvious by Dang, the remaining limitations of claims 22-25 are disclosed or rendered obvious in an analogous manner as in claims 15-18 above.
Claim(s) 26 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zbiciak, Moudgill, Moyer, Pasca, and Dang as applied to claim 22 above, and further in view of Uhler et al. (Uhler) (US 5500947).
Claims 26 and 28 are rejected for the same reasons as claims 19 and 21 above, respectively.
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zbiciak, Moudgill, Moyer, Pasca, and Dang as applied to claim 22 above, and further in view of Brown et al. (Brown) (US 20180004514 A1).
Claim 27 is rejected for the same reasons as claim 20 above, respectively.
Response to Arguments
Applicant on page 9 argues: ‘Applicant respectfully submits that the amendment to paragraph [0050] is grammatically correct and still leaves "extracts" after "that."’
Examiner has reviewed the relevant issue but submits that the objection remains applicable. Examiner submits that the relevant sentence entails a subject (“execution circuitry 509 such as exponent extraction circuitry 511 that extracts biased exponents from BF16 data elements in the source operand 501”) but not a predicate.
Applicant on page 9 argues: “The attached drawings include changes to FIGS. 2 and 9.”
In view of the aforementioned changes, the previously presented objections to the drawings are withdrawn.
Applicant on page 9 argues: “The Applicant amends claims 4, 11, and 25. Accordingly, the Applicant requests withdrawal of the objections to claims 4, 11, and 25.”
In view of the aforementioned amendments, the previously presented objections to the claims are withdrawn.
Applicant on page 9 argues: “Applicant has added the unnecessary word hardware because a PHOSITA looking at the specification would understand that an HDL is not circuitry (even if it describes circuitry) as a PHOSITA would be familiar with HDL and how it works.”
In view of the aforementioned addition, the previously presented rejections of claims 1-7 under 35 USC 101 are withdrawn. However, the previously presented rejections of claims 8-14 under 35 USC 101 appear to remain applicable, as claim 8 does not recite that the system comprises the execution circuitry hardware.
Applicant on page 10 argues: ‘With respect to claim 1 and the language "one or more non-opcode fields," it has explicit support. See, e.g., FIG. 4 and the "imm8" which is not an opcode field. With respect to claim 8 and the language "one or more non-opcode fields," it has explicit support. See, e.g., FIG. 4 and the "imm8" which is not an opcode field. With respect to claim 15 and the language "one or more non-opcode fields," it has explicit support. See, e.g., FIG. 4 and the "imm8" which is not an opcode field. With respect to claim 22 and the language "one or more non-opcode fields," it has explicit support. See, e.g., FIG. 4 and the "imm8" which is not an opcode field.’
However, while Applicant’s citations may provide support for the instance of the single instruction including one non-opcode field — imm8 — for an indication of one or more classification checks to perform, the original disclosure does not appear to provide support for the instance of the single instruction including one “or more” non-opcode fields for an indication of one or more classification checks to perform.
Applicant across pages 10-11 argues: ‘With respect to claim 1, there is clear antecedent basis for "the execution circuitry." To assist with showing the basis, Applicant has bolded and underlined the first instance of execution circuit below for the Office. … Note the above applies to claim 8 too.’
However, while the claim previously recited “execution circuitry” as noted by Applicant, the claim did not previously recite that the aforementioned execution circuitry was to execute the decoded instruction according to the opcode. Therefore, the limitation “the execution circuitry to execute the decoded instruction according to the opcode”, in the grammatical context in which the limitation appears in the claim (as a second element included within the recited apparatus), does not have antecedent basis.
Applicant on page 11 argues: “With respect to claim 2, Applicant has amended the claim. Claims 9, 16, and 23 have been similarly amended.”
In view of the aforementioned amendments, the associated previously presented indefinite rejections are withdrawn.
Applicant on page 11 argues: “With respect to claim 3, Applicant has amended the claim. Claims 10, 17, and 24 have been similarly amended.”
In view of the aforementioned amendments, the associated previously presented indefinite rejections are withdrawn.
Applicant on page 11 argues: “With respect to claim 4, Applicant has amended the claim. Claims 11, and 25 have been similarly amended.”
In view of the aforementioned amendments, the associated previously presented indefinite rejections are withdrawn.
Applicant on page 11 argues: ‘With respect to claim 15, Applicant has been amened the language to say "particular."’
In view of the aforementioned amendments, most facets of the associated previously presented indefinite rejection is withdrawn. However, the language in claim 20, line 2, does not appear to have been amended.
Applicant on page 11 argues: “With respect to claim 18, Applicant has amended the language.”
However, the associated previously presented indefinite rejection appears to remain applicable — see the Claim Rejections - 35 USC § 112 section above.
Applicant on page 11 argues: “With respect to claim 22, Applicant has amended the language.”
However, one of the two previously presented indefinite rejections appears to remain applicable — see the Claim Rejections - 35 USC § 112 section above.
Applicant on page 12 argues: “Zbiciak is admitted as not having a field to indicate what classification check to perform.”
Examiner generally notes for clarity of the record that the Office Action did not convey that Zbiciak did not teach having a field to indicate what classification check to perform. Rather, the Office action conveyed that Zbiciak does not disclose that the single instruction includes one or more “non-opcode” fields for an indication of the aforementioned one or more classification checks to perform.
Applicant on page 12 argues: ‘Moudgill is cited for as allegedly describing this. In particular, the "vclass_class" instruction is cited. An attempt to describe this instruction is found in paragraphs [0297]-[0303], but several things are not clear. For example, the text says "vclassfclass$n0" but does not describe what $n0 is doing there. It is never used in the rest of the discussion. Further, the text says there is a "class field in the instruction" but never states what a "class field" is anywhere in the text of Moudgill. Applicant still respectfully submits that the "class field" is not a separate field from the opcode. If it was, there would be no reason for Moudgill to use the underscore. For example, see the use of the _ in paragraph [0121] which notes that "vaddfs adds vectors of single-precision floating-point values" and referes to "_b" as a suffix.’
Examiner submits that the disclosure of a “class field” (and not, for example, an “opcode and class field”, or an “opcode field”) indicates that the class field may be reasonably considered to be a non-opcode field.
Applicant on page 12 argues: “Applicant appreciates that the Office has attempted to find a different citation given the deficiencies of Moudgill. However, Applicant respectfully disagrees that Moyer describes using a field to indicate what classification check to perform. All the cited sections appear to describe is the extremely common and well-known use of a condition code register (CCR 33) to determine when to conditionally branch. There is no discussion of the any branching instruction, or other instruction, that includes an indication of a check to perform other than, again, the extremely common usage of an opcode.”
Examiner notes that the Office Action did not rely upon Moyer to teach using a field to indicate what classification check to perform. Rather, the Office Action relied upon Moyer to disclose the well-known concept of implementing two different instruction behaviors using a particular opcode and a behavior specifier in a non-opcode field rather than two separate opcodes, and relied upon a combination of prior art references (including Moyer) to teach the overall relevant claim limitation.
Applicant on page 12 argues: “The combination also does not appear to describe the specific logical OR and logical AND circuitry being execution circuitry hardware.”
However, Examiner submits that Zbiciak and Moudgill teach this subject matter.
Applicant across pages 12-13 argues further claims for the same rationale given with respect to claim 1.
Examiner’s responses to arguments with respect to claim 1 are likewise applicable to the arguments directed to the aforementioned further claims.
Conclusion
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/KEITH E VICARY/Primary Examiner, Art Unit 2182