Prosecution Insights
Last updated: April 19, 2026
Application No. 17/463,398

BFLOAT16 ARITHMETIC INSTRUCTIONS

Non-Final OA §103§112
Filed
Aug 31, 2021
Examiner
DOMAN, SHAWN
Art Unit
2183
Tech Center
2100 — Computer Architecture & Software
Assignee
Intel Corporation
OA Round
3 (Non-Final)
66%
Grant Probability
Favorable
3-4
OA Rounds
2y 9m
To Grant
90%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allow Rate
183 granted / 275 resolved
+11.5% vs TC avg
Strong +23% interview lift
Without
With
+23.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
47 currently pending
Career history
322
Total Applications
across all art units

Statute-Specific Performance

§101
2.8%
-37.2% vs TC avg
§103
47.2%
+7.2% vs TC avg
§102
18.0%
-22.0% vs TC avg
§112
26.3%
-13.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 275 resolved cases

Office Action

§103 §112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1, 8, and 15 have been amended. Claims 1-20 have been examined. The drawing objections in the previous Office Action have been addressed and are withdrawn. Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 19, 2025 has been entered. Claim Objections Claims 1-20 are objected to because of the following informalities. Claim 1 recites, at lines 8-9, “data elements in that data element position in as BF16 data elements.” This appears to be a typographical error. Applicant may have intended, “data elements in that data element position [[in]] as BF16 data elements.” Claims 8 and 15 include similar language and are similarly objected to. Claims 2-7, 9-14, and 16-20 are objected to as depending from objected to base claims and failing to remedy the deficiencies of those claims. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the Applicant regards as the invention. Claim 1 recites, at lines 7-8, “the identified packed data source operands.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “the first and second packed data source operands.” Claims 8 and 15 include similar language and are similarly rejected. Claim 1 recites, at line 11, “the identified packed data destination operand.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this limitation is interpreted as, “the packed data destination operand.” Claims 8 and 15 include similar language and are similarly rejected. Claim 2 recites, at lines 1-2, “the field for the identification of the first source operand.” This limitation lacks proper antecedent basis in two places. For purposes of examination, this limitation is interpreted as, “the field for the identification of the location of the first packed data source operand.” Claims 3, 9, and 10 include similar language and are similarly rejected. Claims 2-7, 9-14, and 16-20 are rejected as depending from rejected base claims and failing to cure the indefiniteness of those base claims. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 5, 8-10, 12, 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2019/0079767 by Heinecke et al. (hereinafter referred to as “Heinecke”). Regarding claims 1, 8, and 15, taking claim 1 as representative, Heinecke discloses: an apparatus comprising: decode circuitry to decode an instance of a single instruction, the single instruction to include fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of location of a packed data destination operand, wherein the opcode is to indicate an arithmetic operation execution circuitry is to perform, for each data element position of the identified packed data source operands, the arithmetic operation on BF16 data elements in that data element position in as BF16 data elements and store a result of each arithmetic operation… into a corresponding data element position of the identified packed data destination operand (Heinecke discloses, at Figure 1, decode and execution circuitry. Heinecke also discloses, at Figure 2, an instruction that includes fields for an opcode, first packed data source location, second packed data source location, and packed data destination location, where the opcode specifies an arithmetic operation to be performed on BF16 source elements, with the result stored in the destination.); and the execution circuitry to execute the decoded instruction according to the opcode (Heinecke discloses, at Figure 1, decode and execution circuitry.). Heinecke does not explicitly disclose storing the results as BF16. Instead, Heinecke discloses storing the result as a 32-bit number. See, e.g., ¶ [0040]. However, Heinecke discloses using bfloat16 elements as the sources. Id. Heinecke also discloses using various sizes and formats of FP numbers as sources and destinations. See, e.g., ¶ [0131]. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Heinecke to use the disclosed bfloat16 elements as destination elements because bfloat16 elements improve performance by reducing the amount of storage needed to store values. Regarding claims 2 and 9, taking claim 2 as representative, Heinecke discloses the elements of claim 1, as discussed above. Heinecke also discloses: wherein the field for the identification of the first source operand is to identify a vector register (Heinecke discloses, at ¶ [0040], the operands can be in vector registers or memory.). Regarding claims 3 and 10, taking claim 3 as representative, Heinecke discloses the elements of claim 1, as discussed above. Heinecke also discloses: wherein the field for the identification of the first source operand is to identify a memory location (Heinecke discloses, at ¶ [0040], the operands can be in vector registers or memory.). Regarding claims 5, 12, and 17, taking claim 5 as representative, Heinecke discloses the elements of claim 1, as discussed above. Heinecke also discloses: wherein the arithmetic operation is multiplication (Heinecke discloses, at Figure 2, the arithmetic operation is a dot product operation, which encompasses multiplication.). Claims 4, 7, 11, 14, 16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Heinecke. Regarding claims 4, 11, and 16, taking claim 4 as representative, Heinecke does not explicitly disclose the aforementioned arithmetic operation is addition. However, Heinecke discloses, at ¶ [0131], performing addition. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Heinecke’s single instruction to perform addition because doing so increases the available functionality and utility. Regarding claims 7, 14, and 19 taking claim 7 as representative, Heinecke discloses the elements of claim 1, as discussed above. Heinecke does not explicitly disclose the aforementioned arithmetic operation is subtraction. However, Heinecke discloses, at ¶ [0131], performing subtraction. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Heinecke’s single instruction to perform subtraction because doing so increases the available functionality and utility. Claims 6, 13, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Heinecke in view of US Publication 20190042244 by Henry et al. (hereinafter referred to as “Henry”). Regarding claims 6, 13, and 18, taking claim 6 as representative, Heinecke discloses the elements of claim 1, as discussed above. Heinecke does not explicitly disclose wherein the aforementioned arithmetic operation is division However, in the same field of endeavor (e.g., instruction processing) Henry discloses: performing division (Henry discloses, at ¶ [0057], performing division.). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Heinecke’s single instruction to perform division, as taught by Henry, because doing so increases the available functionality and utility. Regarding claim 20, Heinecke discloses the elements of claim 15, as discussed above. Heinecke does not explicitly disclose translating the single instruction to one or more instructions of a different instruction set architecture, wherein the executing the decoded instruction according to the opcode comprises executing the one or more instructions of the different instruction set architecture. However, in the same field of endeavor (e.g., instruction processing) Henry discloses: translating instructions between ISAs and executing the translated instructions (Henry discloses, at ¶ [0171], translating instructions between ISAs. Executing the translated instructions is implicit.). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Heinecke to include instruction translation, as taught by Henry, because doing so increases the available functionality and utility. Response to Arguments On page 2 of the response filed August 19. 2025 (“response”), the Applicant argues, “The Office Action cites Fig. 2 for the previous variant of this clause. This illustration is for VDPBF16PS which stores a PS, or 32- bit, floating point result. The amended claim stores BF16 data elements.”_ These remarks have been fully considered and, in light of the claim amendments presented in the response, are deemed persuasive. Please see above for new grounds of rejection of the amended claims. It would have been obvious to utilize the BF16 format for results as well as for inputs in order to save storage space. Conclusion The following prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure. US 20220075598 by Werner discloses BF16 results. US 20240289092 by Zhang discloses BF16 results. US 20210182465 by Langhammer discloses bfloat16 results. US 20190042244 by Henry discloses bfloat16 operations. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAWN DOMAN/Primary Examiner, Art Unit 2183
Read full office action

Prosecution Timeline

Aug 31, 2021
Application Filed
Feb 25, 2022
Response after Non-Final Action
Sep 23, 2024
Non-Final Rejection — §103, §112
Jan 22, 2025
Response Filed
Feb 13, 2025
Final Rejection — §103, §112
Aug 19, 2025
Request for Continued Examination
Aug 26, 2025
Response after Non-Final Action
Oct 16, 2025
Non-Final Rejection — §103, §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
66%
Grant Probability
90%
With Interview (+23.4%)
2y 9m
Median Time to Grant
High
PTA Risk
Based on 275 resolved cases by this examiner. Grant probability derived from career allow rate.

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