DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-6, 14-21 are presented for the examination. Applicant's election without traverse of the invention of group I ( claims 1-6, 14-21). Application requested to cancel claims 7-13 and 22-36.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claim 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over
RHU(US 20210034957 A1) in view of Kim(US 20220206068 A1).
As to claim 1, RHU teaches cause two or more different types of accelerator processing cores to perform an inferencing operation using one or more neural networks( the dedicated processor 300 may process the reduced embedding, based on the neural network. That is, the dedicated processor 300 may perform the inference and training operation, para[0049], ln 5-11/ The dedicated processor 300 may perform the inference and training operation, based on various neural network algorithms, para[0042], ln 1-3/ dedicated processor may include at least one of a graphic processing device[accelerator processing cores] and a neural network processing device[accelerator processing cores], para[0021]/ It is described that the neural processing unit 3300 in FIG. 8 performs the inference and training operation, but the inventive concept is not limited thereto. For example, FIG. 8 performs the inference and training operation, but the inventive concept is not limited thereto. For example, the neural network acceleration system 3000 may include a graphics processing device instead of the neural processing unit 3300. In this case, the graphics processing device may perform the inference and training operation, based on the neural network, para[0096]).
Kim teaches circuitry one or more circuits to cause two or more different types of accelerator processing cores to perform an inferencing operation using one or more neural networks( The neural processing unit 100 may be a semiconductor device implemented by an electric/electronic circuit. The electric/electronic circuit may refer to a circuit including a large number of electronic elements (transistors, capacitors, etc.). The neural processing unit 100 includes a processing element (PE) array 110 (shown in FIG. 1 to have PE1 through PE12, but not limited hereto), an NPU internal memory 120, an NPU scheduler 130, and an NPU interface 140, para[0098], ln 1-10/ The UPU may include: one or more central processing units (CPUs); one or more graphic processing units (GPUs); and one or more neural processing units (NPUs) configured to perform operations for an artificial neural network (ANN) model[[an inferencing operation] para[0022]/ The exemplary artificial neural network model 110a of FIG. 4 may be an artificial neural network which is trained in the neural processing unit 100 or trained in a separate machine learning device. The artificial neural network model 110a may be an artificial neural network which is trained to perform various inference functions[an inferencing operation] such as object recognition or voice recognition, para[0189]/ When the MAC operation of the eighth processing element PE8 is completed, the inference operation of the artificial neural network model 110a may be finished. That is, the artificial neural network model 110a may determine that the inference operation of one frame is completed. If the neural processing unit 100 infers moving image data in real time, image data of a subsequent frame may be input to the input nodes x1 and x2 of the input layer 110a-1. At this time, the NPU scheduler 130 may store image data of a subsequent frame in a memory address in which input data of the input layer 110a-1 is stored. When this process is repeated at every frame, the neural processing unit 100 may process the inference operation in real time. Further, a memory address which has been set may be reused, para[0249]) .
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of RHU with Kim to incorporate the above feature because this provide intelligence for recognition, classification, inference, prediction, control/decision making.
3. Claim(s) 2, 3, 14 are rejected under 35 U.S.C. 103 as being unpatentable RHU(US 20210034957 A1) in view of Kim(US 20220206068 A1) and further in view of APPU( US 20230377209 A1).
As to claim 2, APPU teaches the two or more different types of processing cores comprise one or more deep learning accelerators (DLAs) and one or more parallel processing unit (PPU) cores(The processor 2702 and the GPGPU 2720 can be any of the processors and GPGPU/parallel processors as described herein, Para[0374], ln 5-9/ The general-purpose processing unit (GPGPU) 700 may be configured to provide support for hardware acceleration of primitives provided by a machine learning framework to accelerate the processing the type of computational workloads associated with training deep neural networks. Additionally, the GPGPU 700 can be linked directly to other instances of the GPGPU to create a multi-GPU cluster to improve training speed for particularly deep neural networks. Primitives are also supported to accelerate inference operations for deployed neural networks, para[0185]/ the inferencing configuration of the GPGPU 700 can support inferencing specific instructions. For example, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions, which are commonly used during inferencing operations for deployed neural networks, para[0190], ln 10-16/ he GPGPU 1306 can include compute clusters such as a low power configuration of the processing clusters 706A-706H within general-purpose graphics processing unit 700. The compute clusters within the GPGPU 1306 can support instruction that are specifically optimized to perform inferencing computations on a trained neural network, para[0233], ln 1-7).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of RHU and Kim with APPU to incorporate the above feature because this provides groups of parallel threads attempt to execute program instructions synchronously together as often as possible to increase processing efficiency and enables such processors to support a wider variety of operations for processing vertex and fragment data.
As to claim 3, APPU teaches the one or more PPU cores are graphics processing unit (GPU) cores( para[0061], ln 1-3) for the same reason as to claim 2 above.
As to claim 14, it is rejected for the same reason as to claim 1 above. In additional, APPU teaches A machine-readable medium having stored thereon one or more instructions, which if performed by one or more processors( Operations of the method can be implemented via instructions stored in a non-transitory machine readable medium, para[0432], ln 10-13/ the one or more processors 1402 may include one or more processor cores 1407 to process instructions which, when executed, perform operations for system or user software. The least one of the one or more processor cores 1407 may be configured to process a specific instruction set 1409( para[0237], ln 1-6).
4. Claim(s) 15, 16, 17 are rejected under 35 U.S.C. 103 as being unpatentable RHU(US 20210034957 A1) in view of Kim(US 20220206068 A1) and further in view of ZHOU(US 20220092386 A1)
As to claim 15, Zhou teaches the two or more different types of processing cores comprise at least one or more parallel processing unit (PPU) cores and one or more deep learning accelerators (DLAs) ( the two or more different types of processing cores comprise at least one or more parallel processing unit (PPU) cores and one or more deep learning accelerators (DLAs).para[0233], ln 1-7/ para[0190], ln 10-16/ Para[0374], ln 5-9/ para[0185]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of RHU and Kim with Zhou to incorporate the above feature because this facilitates the expansion of deep learning accelerators from a single-core architecture to a multi-core architecture in the cost of relatively small overhead, and offers a highly-efficient splitting method for a given network and an underlying accelerator.
As to claim 16, Zhou teaches the one or more PPU cores are graphics processing unit (GPU) cores( ( para[0061], ln 1-3).
As to claim 17, Zhou teaches the two or more different types of processing cores are to perform an execution graph, the execution graph comprising a first kernel to perform a first part of the inferencing operation and a second kernel to perform a second part of the inferencing operation( para[0083], ln 1-10/ para[0074], ln 1-12/ para[0073], ln 6-11).
5. Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over RHU(US 20210034957 A1) in view of Kim(US 20220206068 A1) and further in view of SHAH( US 20200167098 A1).
As to claim 4, RHU teaches one or more software programs comprise instructions to cause the two or more different types of processing cores to perform the inferencing operation( para[0096]).
Shah teaches the one or more software programs comprising a first set of instructions to be performed by a first of the two or more different types of processing cores and a second set of instructions to be performed by a second of the two or more different types of processing cores( For example, processing system 504 can use inference engine 510 to perform inference operations, para[0020], ln 2-5/ Compute engine 514 can use a neural network to perform inferences or analysis. A neural network can be implemented using any or a combination of: one or more hardware components or as program code instructions that are executed on one or more central processing unit (CPU) or cores or graphics processing unit (GPU) processing cores. Inner layers of a neural network can be viewed as layers of neurons that each receive weighted outputs from the neurons of other (e.g., preceding) layer(s) of neurons in a mesh-like interconnection structure between layers, para[0023], ln 1-10).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of RHU and KIM with SHAH to incorporate the above feature because this provides the need for an additional inference server to run these non-critical compute tasks.
6. Claim 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over RHU(US 20210034957 A1) in view of Kim(US 20220206068 A1) and further in view of KOKER ALTUG( WO 2020190797 A1).
As to claim 5, KOKER teaches the inferencing operation is to be performed as a result of one or more function calls to a parallel processing library, the parallel processing library comprising instructions to perform a first portion of the inferencing operation on a first of the two or more different types of processing cores and a second portion of the inferencing operation on a second of the two or more different types of processing cores( the GPGPU cores 262 can include hardware logic that may otherwise reside within the tensor and/or ray-tracing cores 263. The GPGPU cores 262 can be similar in architecture or can differ in architecture. For example and in one embodiment, a first portion of the GPGPU cores 262 include a single precision FPU and an integer ALU while a second portion of the GPGPU cores include a double precision FPU, para[0078], ln 4-11/ the inferencing configuration of the GPGPU 700 can support inferencing specific instructions. For example, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions, which are commonly used during inferencing operations for deployed neural networks, para[01175], ln 10-15/ The architecture described above can be applied to perform training and inference operations using machine learning models, para[0162],ln 1-3/ Multi-purpose execution logic (e.g., execution units) within the graphics core(s) 1715A-1714B of the graphic core array 1714 includes support for various 3D API shader languages and can execute multiple simultaneous execution threads associated with multiple shaders. [0260] The graphics core array 1714 may include execution logic to perform media functions, such as video and/or image processing. The execution units may include general- purpose logic that is programmable to perform parallel general-purpose computational operations, in addition to graphics processing operations. The general-purpose logic can perform processing operations in parallel or in conjunction with general-purpose logic within the processor core(s) 1407 of FIG. 14 or core 1502A-1502N as in FIG. 15A,para[0259], ln 8-24).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of RHU and Kim with KOKER to incorporate the above feature because this provides the need for an additional inference server to run these non-critical compute tasks.
7. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over RHU(US 20210034957 A1) in view of Kim(US 20220206068 A1) in view of KOKER ALTUG( WO 2020190797 A1) and further in view of Sankaralingam( US 20160041856 A1).
As to claim 6, it is rejected for the same reason as to claim 5 above. In additional, Koker teaches indicate the one or more neural networks( para[0156]/para[0162]/ para[0043], ln 1-15/ para[0305], ln 2-7/ para[0237], ln 17-24 ) for the same reason as to claim 5 above.
Sankralingam teaches the parallel processing library providing shared pointer addressing to the two or more different types of processing cores( The host processor 32 may communicate remote procedure calls to the memory processing controller 40, and the memory processing controller 40 may route the procedure calls directly or indirectly to the memory processing cores 28 (such as through the memory system controller 38 and the communication logic 30). The memory processing controller 40 routes the procedure calls to the appropriate memory processing cores 28 based on target addresses of the procedure calls corresponding to memory vaults 26 of the respective memory processing cores 28. In turn, the memory processing cores 28 respond to the procedure calls by efficiently processing data stored in their respective memory vaults 26 and providing a result to the host processor 32, para[0039]/ a memory processing core 28, upon receiving a procedure call from the host processor 32 routed by the memory processing controller 40, may respond to the procedure call by processing the partitioned data stored in its respective memory vault 26 and providing a processed result back to the host processor 32. With memory vaults 26 advantageously including multiple memory processing cores 28, each memory vault 26 can allow multiple computations to proceed in parallel. In addition, computations in different memory vaults 26 can proceed concurrently, para[0043]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of RHU, Kim and KOKER with Sankralingam to incorporate the above feature because this exists to provide an improved architecture capable of meeting increasing performance demands while improving access latencies with minimized power consumptions.
8. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over RHU(US 20210034957 A1) in view of Kim(US 20220206068 A1) in view of Rivard(US 20210001810 A1) in view of APPU( US 20230377209 A1) and further in view of SHAH( US 20200167098 A1).
As to claim 18, Rivard teaches one or more software programs comprise instructions to cause the two or more different types of processing cores to perform the inferencing operation( para[0087], ln 18-25) for the same reason as to claim 1 above
Shah teaches the one or more software programs comprising a first set of instructions to be performed by a first of the two or more different types of processing cores and a second set of instructions to be performed by a second of the two or more different types of processing cores( For example, processing system 504 can use inference engine 510 to perform inference operations, para[0020], ln 2-5/ Compute engine 514 can use a neural network to perform inferences or analysis. A neural network can be implemented using any or a combination of: one or more hardware components or as program code instructions that are executed on one or more central processing unit (CPU) or cores or graphics processing unit (GPU) processing cores. Inner layers of a neural network can be viewed as layers of neurons that each receive weighted outputs from the neurons of other (e.g., preceding) layer(s) of neurons in a mesh-like interconnection structure between layers, para[0023], ln 1-10).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Zhou, Rivard and APPU with SHAH to incorporate the above feature because this provides the need for an additional inference server to run these non-critical compute tasks.
9. Claims 19, 20, 21 are rejected under 35 U.S.C. 103 as being unpatentable over RHU(US 20210034957 A1) in view of Kim(US 20220206068 A1) in view of APPU( US 20230377209 A1) and further in view of KOKER ALTUG( WO 2020190797 A1).
As to claim 19, KOKER teaches receive the one or more neural networks as a result of one or more function calls to a parallel processing library, the parallel processing library comprising a first set of instructions to cause a first part of the inferencing operation to be performed by a first of the two or more different types of processing cores and a second set of instructions to cause a second part of the inferencing operation to be performed by a second of the two or more different types of processing cores ( An exemplary type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network may be implemented as an acyclic graph in which the nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer that are separated by at least one hidden layer. The hidden layer transforms input received by the input layer into a representation that is useful for generating output in the output layer. The network nodes are fully connected via edges to the nodes in adjacent layers, but there are no edges between nodes within each layer. Data received at the nodes of an input layer of a feedforward network are propagated (i.e.,“fed forward”) to the nodes of the output layer via an activation function that calculates the states of the nodes of each successive layer in the network based on coefficients (“weights”) respectively associated with each of the edges connecting the layers. Depending on the specific model being represented by the algorithm being executed, the output from the neural network algorithm can take various forms, para[0164]/ A first instance of a primitive assembler 506 receives vertex attributes from the vertex processing unit 504. The primitive assembler 506 readings stored vertex attributes as needed and constructs graphics primitives for processing by tessellation control processing unit 508. The graphics primitives include triangles, line segments, points, patches, and so forth, as supported by various graphics processing application programming interfaces (APIs), para[0156]/ Fig. 5/the GPGPU cores 262 can include hardware logic that may otherwise reside within the tensor and/or ray-tracing cores 263. The GPGPU cores 262 can be similar in architecture or can differ in architecture. For example and in one embodiment, a first portion of the GPGPU cores 262 include a single precision FPU and an integer ALU while a second portion of the GPGPU cores include a double precision FPU, para[0078], ln 4-11/ the inferencing configuration of the GPGPU 700 can support inferencing specific instructions. For example, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions, which are commonly used during inferencing operations for deployed neural networks, para[01175], ln 10-15/ The architecture described above can be applied to perform training and inference operations using machine learning models, para[0162],ln 1-3/ Multi-purpose execution logic (e.g., execution units) within the graphics core(s) 1715A-1714B of the graphic core array 1714 includes support for various 3D API shader languages and can execute multiple simultaneous execution threads associated with multiple shaders. [0260] The graphics core array 1714 may include execution logic to perform media functions, such as video and/or image processing. The execution units may include general- purpose logic that is programmable to perform parallel general-purpose computational operations, in addition to graphics processing operations. The general-purpose logic can perform processing operations in parallel or in conjunction with general-purpose logic within the processor core(s) 1407 of FIG. 14 or core 1502A-1502N as in FIG. 15A,para[0259], ln 8-24/ para[0259], ln 8-24).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of RHU, Kim and APPU with KOKER to incorporate the above feature because this provides the need for an additional inference server to run these non-critical compute tasks.
As to claim 20, KOKER teaches instructions that, when performed by the one or more processors, cause the two or more different types of processing cores to perform the inferencing operation as a result of one or more function calls to a parallel processing library(para[0078], ln 4-11/ para[01175], ln 10-15/ para[0162],ln 1-3).
As to claim 21, KOKER teaches one or more function calls to an application programming interface (API) provided by the parallel processing library are to indicate the one or more neural network( para[0156]/para[0162]/ para[0043], ln 1-15/ para[0305], ln 2-7/ para[0237], ln 17-24 ) for the same reason as to claim 5 above.
Response to the argument:
10. Applicant amendment filed on 01/22/2026 has been considered but they are not persuasive: Applicant argued in substance that :
(1) “ , Zhou does not disclose or suggest that the claimed circuitry is to "cause two or more different types of accelerator processing cores to perform an inferencing operation using one or more neural networks." Zhou merely describes parallel execution of neural network computations across identical processing cores. Zhou [0068], [0070]. For example, the architecture in Zhou is limited to replicating the same neural network computation across multiple identical cores to process different data in parallel. Id. Therefore, nothing in the cited portions of Zhou discloses or suggests any "circuitry to cause two or more different types of accelerator processing cores to perform an inferencing operation using one or more neural networks" as recited in amended claim 1.”
11. Examiner respectfully disagreed with Applicant's remarks:
As to the point (1), RHU teaches cause two or more different types of accelerator processing cores to perform an inferencing operation using one or more neural networks( the dedicated processor 300 may process the reduced embedding, based on the neural network. That is, the dedicated processor 300 may perform the inference and training operation, para[0049], ln 5-11/ The dedicated processor 300 may perform the inference and training operation, based on various neural network algorithms, para[0042], ln 1-3/ dedicated processor may include at least one of a graphic processing device[accelerator processing cores] and a neural network processing device[accelerator processing cores], para[0021]/ It is described that the neural processing unit 3300 in FIG. 8 performs the inference and training operation, but the inventive concept is not limited thereto. For example, FIG. 8 performs the inference and training operation, but the inventive concept is not limited thereto. For example, the neural network acceleration system 3000 may include a graphics processing device instead of the neural processing unit 3300. In this case, the graphics processing device may perform the inference and training operation, based on the neural network, para[0096]).
Kim teaches circuitry one or more circuits to cause two or more different types of accelerator processing cores to perform an inferencing operation using one or more neural networks( The neural processing unit 100 may be a semiconductor device implemented by an electric/electronic circuit. The electric/electronic circuit may refer to a circuit including a large number of electronic elements (transistors, capacitors, etc.). The neural processing unit 100 includes a processing element (PE) array 110 (shown in FIG. 1 to have PE1 through PE12, but not limited hereto), an NPU internal memory 120, an NPU scheduler 130, and an NPU interface 140, para[0098], ln 1-10/ The UPU may include: one or more central processing units (CPUs); one or more graphic processing units (GPUs); and one or more neural processing units (NPUs) configured to perform operations for an artificial neural network (ANN) model[[an inferencing operation] para[0022]/ The exemplary artificial neural network model 110a of FIG. 4 may be an artificial neural network which is trained in the neural processing unit 100 or trained in a separate machine learning device. The artificial neural network model 110a may be an artificial neural network which is trained to perform various inference functions[an inferencing operation] such as object recognition or voice recognition, para[0189]/ When the MAC operation of the eighth processing element PE8 is completed, the inference operation of the artificial neural network model 110a may be finished. That is, the artificial neural network model 110a may determine that the inference operation of one frame is completed. If the neural processing unit 100 infers moving image data in real time, image data of a subsequent frame may be input to the input nodes x1 and x2 of the input layer 110a-1. At this time, the NPU scheduler 130 may store image data of a subsequent frame in a memory address in which input data of the input layer 110a-1 is stored. When this process is repeated at every frame, the neural processing unit 100 may process the inference operation in real time. Further, a memory address which has been set may be reused, para[0249]) .
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
conclusion
US 20210034957 A1 teaches the dedicated processor 300 may be implemented as one of operation devices that perform neural network-based operations, such as a graphics processing unit (GPU) or a neural processing unit (NPU).
US 20220206068 A1 teaches When the MAC operation of the eighth processing element PE8 is completed, the inference operation of the artificial neural network model 110a may be finished. That is, the artificial neural network model 110a may determine that the inference operation of one frame is completed. If the neural processing unit 100 infers moving image data in real time, image data of a subsequent frame may be input to the input nodes x1 and x2 of the input layer 110
US 20210125042 A1 teaches The disclosed embodiments can be implemented as compute tiles in a neural processing unit, processing units (e.g., GPUs, CPUs or the like) in a multi-processor system, or combinations of neural processing units or multi-processor systems connected into a distributed system. The disclosed embodiments can be configured to support multi-tasking, enabling simultaneous execution of inference and training or transfer-learning tasks.
US 20210182676 A1teaches In both GPU and CPU architectures, the neural network's weights and inputs may be represented as tensors or matrices, and the computation of the network (e.g. the inference or run-time operation) may include a sequence of convolutional calculations of these tensors or matrices.
US 20210089807 A1 teaches if the device includes a processor and memory, the convolutional neural network may be stored in the memory and the processor may perform the forward propagation (or inference) operation on input data as configured by the parameters. In some devices the processor may be, or may include, a graphics processing unit (GPU) or neural processing unit (NPU) may be used to accelerate the performance of inference operations, where the processor may store the convolutional neural network (e.g., its layers, connections, and parameters).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LECHI TRUONG whose telephone number is (571)272-3767. The examiner can normally be reached 10-8 PM.
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/LECHI TRUONG/ Primary Examiner, Art Unit 2194
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