DETAILED ACTION
Claims 1-9 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The supplemental reply filed on June 16, 2026, was not entered because supplemental replies are not entered as a matter of right except as provided in 37 CFR 1.111(a)(2)(ii). The supplemental reply is not entered because it does not clearly (A) cancel a claim; (B) adopt an examiner’s suggestion; (C) place the application in condition of allowance; (D) reply to an Office requirement made after the first reply was filed; (E) correct informalities (e.g., typographical errors); or (F) simplify issues for appeal.
Applicant requests entry because the new apparatus claims share the same inventive concept as the existing method claims (p.1 of applicant’s supplemental response). As seen above, this is not a reason for entry. However, even if it was, the apparatus claims do not fully correspond to the method claims. The new claims additionally require that the one or more software parameters be pushed onto the first stack in response to invocation of a call operation in software. They also additionally require a processor arithmetic unit and processor control logic, both of which would invoke 112(f) and be limited to structure in the specification, should any exist.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections/Recommendations
Claim 1 is objected to because of the following informalities:
Applicant twice recites “wherein the first processor stack control comprises a hardware base register and a hardware limit register” (one in part b and again in part c. Including this twice is redundant. Please remove one of the two instances.
In part d, line 2, delete “processor” from before “contents” to match language in part c, line 1.
In part e, lines 2 and 5, delete “processor” from before “contents” to match language in part c, line 1.
In part e, lines 2 and 5, replace “processor second” with --second processor-- to match part c, line 1.
In part f, replace “processor second” with --second processor--.
In part f, remove “processor” from before each of the two instances of “contents”.
In claim 1, part f, the examiner recommends deleting “all of” since it seems unnecessary.
Claim 2 is objected to because of the following informalities:
The examiner asserts that it is not the hardware result register per se that is pushed onto the stack, but the result data in the result register (from claim 1, part e). Hardware isn’t stored; data is stored. Please amend to clarify this.
In claim 3, lines 1 and 5, the examiner recommends inserting --software-- after each instance of “more” to match claim 1, parts b and d.
Claim 3 is objected to because of the following informalities:
In line 2, “onto to” is grammatically incorrect. Please delete “to”.
In claim 3, line 3, the examiner recommends inserting --processor-- after “second” to match claim 1.
In claim 3, the examiner recommends replacing each instance of “is directly” with the correct one of --comprises pushing directly-- and --comprises popping directly--.
In claim 3, 4th to last line, the examiner recommends deleting “all of” since it seems unnecessary.
Claim 6 is objected to because of the following informalities:
Please remove the last two lines of claim 6, which are not actually part of the claim.
In claim 8, the examiner recommends inserting commas after “wherein” and after “g)”.
Appropriate correction is required.
Claim Interpretation
Claim 6 recites that the first and second stacks are in substantially simultaneous operation. From paragraphs [0060] and [0099], “substantially simultaneously” in this context is interpreted to mean that there is at least some overlap in time of the operation of the first and second stacks.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Referring to claim 1, parts b-c set forth that each stack has its own processor control and processor registers. The control is claimed to include a respective base register and a respective limit register. Thus, applicant is claiming that each stack has its own base register (first register), limit register (second register), and processor registers (at least two more registers). Thus, each stack is claimed to have at least four registers. However, FIG.10 shows only three registers per stack. Each stack has a base register and limit register, but does not contain other plural registers. Even if the plural registers were taken to be processor working registers, i.e., the plurality of processor registers, this interpretation would appear to be incompatible with the portion of the claim that requires that the processor registers of the second stack be independent of the processor registers of the first stack (part c, lines 2-4). Specifically, the contents of a plurality of registers are pushed onto the second stack (part (c), lines 1-3), and then these very same registers are used to hold popped data from the first stack (part d). As such, since the same processor registers are being used for the two stacks, the first and second stacks do not have independent processor registers. Thus, claiming that each stack has multiple processor registers in addition to its control including base and limit registers is deemed to be new matter not supported by the original disclosure. Applicant can either amend or point the examiner to the relevant support.
All dependent claims are rejected due to their dependence on a claim lacking adequate written description.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Takayama et al., U.S. Patent No. 6,212,630, in view of McAuley, U.S. Patent No. 5,187,799, Tremblay et al., U.S. Patent No. 6,138,210, and the examiner’s taking of Official Notice. Furthermore, Venners (“Inside the Java Virtual Machine”) is cited as extrinsic evidence showing how various stack portions would be used in Tremblay.
Referring to claim 1, Takayama has taught a processor method comprising:
a) invoking a call operation in software (see FIG.11, instruction 121, where the main function calls function f);
c) pushing contents of a plurality of processor registers onto a second processor stack (see FIG.11, instruction 122, which stores/pushes contents of registers R2 and R3 to a stack (see the stm- instruction in FIG.6)) the second processor stack having its own unique processor control and processor register (see FIGs.5 and 11 and note the stack pointer (SP) register, which points to the top of the stack to indicate where to push to (or pop from). The unique control would include at least instructions that indicate SP so as to uniquely address this stack, as well as signals to the hardware itself);
e) performing processor-register-to-processor-register operations on the plurality of processor registers whose processor contents were pushed onto the processor second stack, and storing a result of the processor-register-to-processor-register operations in a processor result register (see FIG.11 and note the add instructions, in code block 125, that are processor-register-to-processor-register operations involving registers R2 and R3, whose contents were pushed to the stack by instruction 122. A result of the operations is stored in result register R0 by the last add instruction block 125);
f) popping off the processor second stack the processor contents of all of the plurality of processor registers whose processor contents were pushed onto the second processor stack in step c) into their respective processor registers from which they came (see FIG.11, instruction 128. R2 and R3 are restored with the previously-pushed contents of R2 and R3. Note the description of the ldm instruction in FIG.7); and
g) returning processor control to an instruction following the call operation in software (see FIG.11, instruction 129. Note the description of this return instruction in FIG.6, which returns to the instruction following the call (located at PC+4, which was stored in the link register (LR)) (FIG.6 and column 1, lines 45-49)).
Takayama has not taught the second stack having its own processor registers (plural), wherein the second processor stack control comprises a hardware base register and a hardware limit register. As stated above, only one register (stack pointer (SP)) is taught. However, McAuley has taught a base register (TB) and a limit register (TT) and that these two registers can be used to set the top and bottom boundaries of a stack so as to detect underflow and overflow errors when an access outside of the boundaries occurs (see column 9, lines 15-32, and FIG.8). As a result, in order to detect and handle faults (and potential security concerns) resulting from popping and pushing data outside of defined stack boundaries, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Takayama such that the second processor stack control comprises a hardware base register and a hardware limit register. After modification, a stack will have its own processor registers (e.g. base register, a limit register, and a stack pointer register).
Takayama has also not taught b) pushing one or more software parameters onto a first processor stack, the first processor stack having its own unique processor control and processor registers, wherein the first processor stack control comprises a hardware base register and a hardware limit register, where the second processor stack control and processor registers are independent of the first processor stack control and processor registers. However, the examiner first notes that one of ordinary skill in the art understands that different code can be written to accomplish the same task. If you ask many programmers to separately write a program to accomplish task X, many different programs could reasonably be expected. For example, FIG.11 of Takayama shows performing some work (including obtaining values from memory at global addresses i0, i1, i2, and i3) in function f. However, this work could alternatively be shifted into the main function and then the main function could pass the values to function f to realize the same final result as original FIG.11. Such would be recognized by one of ordinary skill in the art as substitutable with predictable results, i.e., function f still adds four values together as originally intended (it is simply a matter of which function obtains the values). Furthermore, this would be recognized as a mere re-arrangement of software parts (shifting functionality from one function to another) without modifying the system’s realization of the desired end result. Such re-arrangement is deemed a routine expedient and not a patentable distinction, particularly absent some demonstration of criticality of the re-arrangement (see MPEP 2144.04, including section (VI)(C)). As a result, it would have first been obvious to modify Takayama to re-arrange parts of the code such that the retrieval of values at addresses i0, i1, i2, and i3, is moved from function f to the main function.
Given this modification, there needs to be a way to send the retrieved results from the main function to function f. Tremblay has taught passing parameters to a function via a stack (e.g. stack 310, in portion 432 of Tremblay’s FIG.4B) that is separate from the operand stack (e.g. stack 320, in portion 434 of FIG.4B), which is used during processing of the function. See the abstract and FIGs.4A-B and their descriptions, for instance. Note, from column 2, lines 15-18, this is explained in the context of JAVA, and Venners (see attached) explains the different types of stack portions for JAVA, with the operand stack being the workspace for the function (see pp.4-5). As a result, in order to pass parameters from the main function to function f for an obvious re-arrangement of Takayama’s code in FIG.11, and in a manner that allows for simultaneous access to multiple frames in different stacks (see the first paragraph in the detailed description of Tremblay), which may speed up access and, therefore, execution, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Takayama for b) pushing one or more software parameters onto a first processor stack separate from the second stack that is used to store values in R2, R3, and LR by the function.
Furthermore, since the first stack and second stack are different stacks, the first stack would also require its own unique stack pointer register (to track the next entry at which to push/pop a value in only the first stack) and, for reasoning given above, it is also obvious for the first stack’s control to comprise its own base register and limit register (separate from the second stack’s control) to track the stack boundaries for underflow and overflow. Thus, for these reasons, the unique control and registers of each stack would be independent of one another.
To summarize the proposed combination, Takayama’s FIG.11 code would be modified so that the retrieval of values, which is performed by the alternating ld/st sequence at the beginning of block 125 is instead performed by the main function. The following code is an example of what the FIG.11 code could be modified to in order to utilize two stacks (with their respective stack pointers):
main:
…
ld (i0), R0 //obtain 1st parameter from memory address in i0
st R0, (SP_first_stack) //push the obtained value to the first stack
ld (i1), R0 //obtain 2nd parameter from memory address in i1
st R0, (4, SP_first_stack) //push the obtained value to the first stack
ld (i2), R0
st R0, (8, SP_first_stack)
ld (i3), R0
st R0, (12, SP_first_stack)
call- f //this call would adjust SP_second_stack
…
f:
stm- [R2, R3] //push values in R2 and R3 to second stack
st LR //push return address to second stack
ld (SP_first_stack), R0 //pop 1st parameter from first stack into R0
ld (4, SP_first_stack), R1 //pop 2nd parameter from first stack into R1
ld (8, SP_first_stack), R2
ld (12, SP_first_stack), R3
add R1, R0
add R2, R0
add R3, R0
call- g
ld+ LR //pop return address from second stack
ldm [R2, R3] //pop R2 and R3 values from second stack
rts+ //return to instruction after call- f
Takayama, as modified, has further taught the first stack located in processor memory and the second stack located elsewhere in processor memory (the first and second stacks in the combination are different stacks; thus, they cannot physically be in the same memory locations. As such, they are separate in memory. This is also why they require different base, limit, and stack pointer registers);
Takayama, as modified, has further taught wherein the first processor stack control and the second processor stack control are physically different entities from each other (again, in the combination, there are two stacks, each with its own control (including its own base and limit registers) and its own stack pointer register. Thus, they are physically different controls);
With respect to the limitation of the two stack controls being physically different entities “allowing parallel operations on each stack at an exact same time”, this is not patentable for multiple reasons;
First, allowing parallel operation does not mean that the parallel operation actually occurs. Since the proposed combination of prior art implements different, separately-controllable stacks, access to both at the same time is allowed/possible, i.e., the stacks are capable of being operated in parallel because their independence means control of one does not exclude control of the other (this is supported by the first paragraph in the detailed description of Tremblay, which states “In one embodiment of the invention, the conventional stack of the stack-based computing system is divided into multiple stacks to provide simultaneous access to multiple frame components, such as the operand stack and the arguments and local variable area of the current method frame.”
Alternatively, if this limitation were narrow enough to require that parallel operations on each stack actually occur, Takayama, as modified, has not taught this limitation. However, Official Notice is taken that parallelizing independent operations was well known in the art before applicant’s invention. Also well-known is memory with multiple ports and control lines so as to perform multiple memory operations at the same time. One of ordinary skill in the art would have recognized in Takayama, as modified, that there are ways to speed up execution by parallelizing instructions. This can be done, for instance, with a superscalar architecture with multiple load/store units and/or multiple threads. As an example, in the examiner’s modified code example above, the stm- instruction, which stores R2 and R3 to the second stack, could be at least partially performed at the same time as one of the loads into R0 and R1 from the second stack. This would allow for a speed-up in execution, as opposed to executing all instruction serially. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Takayama such that parallel operations are performed on each stack at an exact same time.
Takayama, as modified, has further taught d) popping off the first processor stack at least one of the one or more software parameters into at least one of the plurality of processor registers whose processor contents were pushed onto the second processor stack (as, modified, Takayama would pop two values from the first stack into R2 and R3, whose values were previously pushed to the stack in the modified main function);
Takayama has also not taught the processor result register being one of the plurality of processor registers whose processor contents were pushed onto the processor second stack. Instead, R0 was chosen to be the result register (see the last add instruction in code 125). However, one of ordinary skill in the art would have recognized that any register could store the destination, including register R2 and R3, because the contents of either of these is not needed again in function f. The examiner again notes that there are many different ways to write software to accomplish the same task. Official Notice is also taken that a destructive write which writes to a register that is used as an input operand was well known in the art before applicant’s invention. For instance, the three add instructions could instead have been programmed destructively as add R0, R1 (R1 = R0+R1); add R1, R2 (R2 = R1+R2, where R1 = R0+R1 from the first add); and add R2, R3 (R3 = R2+R3, where R2 = R1+R2 from the second add). This sequence performs the exact calculation as the three add instructions in block 125 with the only difference being the result is in R2 instead of R0. One of ordinary skill in the art would clearly recognize the substitutability of these options while receiving the same results. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Takayama such that the processor result register being one of the plurality of processor registers whose processor contents were pushed onto the processor second stack.
Referring to claim 2, Takayama, as modified, has taught the processor method of claim 1, but has not taught between e) and f) pushing the processor result register onto the processor first stack. Instead, Takayama stores the result to memory at address j (see last st instruction in code 125), which occurs between the add instructions (step e) and the popping of R2 and R3 (instruction 128) (step f). However, Official Notice is taken that pushing a result to a stack for access by the calling function was well-known in the art before applicant’s invention (and is supported by Venners, e.g. p.8, 2nd to last paragraph, and also FIG.5-12 and the description thereof). Again, these teachings would have been recognized by one of ordinary skill in the art as substitutable with predictable results, i.e., the result is still obtainable (either through the stack or through address j). As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Takayama for, between e) and f), pushing the processor result register onto the processor first stack.
Referring to claim 3, Takayama, as modified, has taught the processor method of claim 1 wherein the pushing one or more parameters onto the first processor stack is directly onto the first processor stack; wherein the pushing contents of the plurality of processor registers onto the second stack is directly from the plurality of processor registers to the second processor stack; wherein the popping off the first processor stack at least one of the one or more parameters into at least one of the plurality of processor registers whose contents were pushed onto the second processor stack is directly from the first processor stack to the at least one of the plurality of processor registers whose contents were pushed onto the second processor stack; and wherein the popping off the second processor stack the processor contents of all of the plurality of processor registers whose processor contents were pushed on the second processor stack in step c) into their respective processor registers from which they came is directly from the second processor stack to the processor registers from which they came (from FIGs.6-7 the modified operation of FIG.11, stores/pushes and loads/pops occur directly to and from stacks and registers).
Referring to claim 4, Takayama, as modified, has taught the processor method of claim 1 but has not taught wherein the processor-register-to-processor-register operations are performed in a set of parallel processor operations. However, Official Notice is taken that parallelizing operations to increase speed was well-known in the art before applicant’s invention. One of ordinary skill in the art would have recognized that you can also add four numbers together (like Takayama does in FIG.11) by performing R1 = R0+R1 and R3 = R2+R3 in parallel (at the same time, because they are completely independent operations that share no operands/destinations), and then following that with R3 = R1+R3. This would save one instruction cycle since each add in FIG.11 takes one cycle (see FIG.2 and column 1, lines 40-44), thereby causing the adds in block 125 to take as many as three cycles. However, with a set of parallel operations, two instructions execute in one cycle and the third instruction in a second cycle. As a result, in order to increase speed, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Takayama to include multiple ALUs (FIG.5, 14) such that the processor-register-to-processor-register operations are performed in a set of parallel processor operations.
Referring to claim 5, Takayama, as modified, has taught the processor method of claim 1 but has not taught wherein the processor-register-to-processor-register operations are performed in a plurality of serial processor operations not overlapping in time and in a set of parallel processor operations. However, for similar reasons as set forth for claim 4, it is obvious to parallelize where possible. In addition, while FIG.11 shows an example of adding four numbers, any function could be performed. For instance, the function could add five numbers where necessary. When five numbers need to be added, one of ordinary skill in the art would have recognized the system could perform A = V+W and B = X+Y in parallel. This would then be followed, serially, by C = A+B, which would then be followed, serially, by D = C+Z. Thus, there would be a set of parallel operations at the beginning followed by multiple serial operations. As a result, in order to add five numbers in an efficient manner using the system of Takayama, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Takayama to include two ALUs (FIG.5, 14) such that the processor-register-to-processor-register operations are performed in a plurality of serial processor operations not overlapping in time and in a set of parallel processor operations.
Referring to claim 6, Takayama, as modified, has taught the processor method of claim 1 wherein the first processor stack and the second processor stack are in substantially simultaneous operation (again, see the rejection of claim 1 (2nd bullet). Furthermore, since the stacks are in memory and memory is powered up during processing, the stacks can be said to be in simultaneous operation, i.e., they are both powered on).
Referring to claim 7, Takayama, as modified, has taught the processor method of claim 1 but has not explicitly taught wherein the processor-register-to-processor-register operations are performed in a set of one or more serial processor operations, the one or more serial processor operations not overlapping in time. However, note the three adds in block 125 and also FIG.5 and note the single ALU. Official Notice is taken that an execution resource accommodating only a single instruction at a time (i.e., serial execution) was well known in the art before applicant’s invention. While this is slower, the hardware design is simplified because extra buses/ports are not required to handle multiple instructions at once. Dependency checking could also be reduced between ALU instructions since there is no worry about improper results if an instruction executes before a previous instruction finishes. As a result, in order to reduce hardware, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Takayama such that the processor-register-to-processor-register operations are performed in a set of one or more processor serial operations, the one or more serial processor operations not overlapping in time.
Referring to claim 8, Takayama, as modified, has taught the processor method of claim 1 wherein at any step b) through g) another step a) of claim 1 is performed (see FIG.11. Between claimed steps e) and f) another call operation (step a)) is performed (see “call- g”). This is the call to g() in FIG.10).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Takayama in view of McAuley, Tremblay, the examiner’s taking of Official Notice, and Poplingher, U.S. Patent No. 6,170,054.
Referring to claim 9, Takayama, as modified, has taught the processor method of claim 8 but has not taught wherein the another step a) of claim 1 is performed as long as there remains processor stack space on both the first processor stack and the second processor stack. However, Poplingher has taught allowing nested calls until a stack runs out of room. When the stack is full, if any other nested call were allowed to proceed, the stack would overflow and complicated recovery procedure would need to be performed. See column 1, line 65, to column 2, line 4. As a result, in order to eliminate complicated processing due to overflow, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Takayama such that the another step a) of claim 1 is performed as long as there remains processor stack space on both the first processor stack and the second processor stack.
Response to Arguments
Regarding argument II(B)(1) on pp.7-8 of applicant’s response (hereafter “the response”), the argument is not persuasive because, assuming arguendo, that the processor registers include “the processor working registers - the plurality of processor registers (e.g. R2, R3) whose contents are pushed onto and popped…”, the claim requires the processor registers of each stack to be independent while simultaneously requiring that contents of the registers be both stored to the second stack and popped/restored from the first stack. As explained in the 112 rejection above, if the same registers are being used by each stack, then each stack, while having its own independent control, does not have its own independent processor registers. Thus, the 112 rejection is maintained.
Argument III(B) on p.9 of the response is persuasive and the 112(b) rejections have been overcome.
On p.10 of the response, applicant’s argument C(1) asserts that Tremblay has not taught hardware stacks with dedicated stack pointer, base, or limit registers, and that Venners is dispositive on this point because Venners discloses that JVM has not registers (which means the stacks have no registers).
The examiner respectfully disagrees. Venners is not dispositive on the point made by applicant. The last paragraph on p.4 of Venners states that there are no registers to store operands for instructions because the operands are stored on the stack instead. This doesn’t mean a stack doesn’t or can’t include control registers defining the boundaries of the stack and where the topmost data is currently stored in the stack. Applicant is also arguing the references separately. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Takayama and McAuley together teach defining any given stack using control registers, as each stack will have a beginning (base register), end (limit register), and current data level (stack pointer register). This could be applied to any stack, including a stack in Tremblay/Venners, for reasons set forth in the rejection. Nothing in Tremblay/Venners precludes these registers from being implemented for a given stack. Also, the examiner disagrees with applicant’s characterization that Tremblay has taught a software stack and not a hardware stack. Any stack implemented include hardware memory locations to store data. Thus, they are all hardware stacks. Nothing in applicant’s claims distinguish from this teaching.
On pp.11-12 of applicant’s response, applicant’s argument C(2) asserts that the use of underlying hardware does not mean that Tremblay discloses dedicated hardware registers controlling those stacks.
Again, the examiner asserts that applicant is arguing the references separately. It is obvious, based on the totality of prior to define each stack based on the taught registers. Every stack occupies a different place in memory. And, every stack must track where to next write data to the stack as it is being filled. Registers to track this information are at least obvious (e.g. a top-of-stack point is ubiquitous in the art).
On pp.11-12, applicant argues that “Patent law does not treat a reference as disclosing hardware components that it silently depends upon but never describes, claims, or teaches.”
Aside from the fact that Tremblay/Venners need not teach everything claimed because the examiner is relying on a combination of prior art, the examiner disagrees with the argument. A reference may be silent on an aspect but still teach that aspect, for instance, if that aspect is inherent.
Regarding argument C(3) on p.12 of the response, which assert that Tremblay and Takayama are incompatible, the examiner respectfully disagrees. In simple terms, Takayama is missing a first stack to store parameters used by a called function. The examiner’s position is that an obvious alternative to the code in FIG.11 of Takayama is one in which parameters determined by the main function are passed to the called function, and that these parameters may be passed via a parameter stack, while the called function will use a different stack to perform its operations.
Argument D on pp.12-13 of the response is not persuasive. McAuley only teaches TT and TB for one stack because McCauley is concerned with only one stack. Tremblay is used to bring a second stack into the overall system and the second stack would then obviously have its own TT and TB registers. Each stack occupies its own place in RAM. Thus, the boundaries of each must be known so as to know which stack to write data to.
Argument E(1) on p.13 of the response asserts that the examiner has used hindsight to reject the claim.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971). The examiner has stated that different programming can be implemented to perform the same task, just as different words may be written to convey the same meaning to a reader. The examiner has explained that passing parameters to a function and determining the parameters in the function itself are two ways to realize the same end result. Thus, one could be substituted for another with predictable results. The examiner is not relying on applicant’s application in a vacuum to make a modification to Takayama; instead, the examiner is referencing a known technique in the art (passing parameters via stack to a called function). Thus, the rejection is maintained.
On p.13 of the response, applicant argues in argument E(2) that there is no reason to combine.
The examiner notes that the conclusion of obviousness is based on at least one KSR rational set forth in MPEP 2143 (for instance, rational B (simple substitution). Further, established case law supports the modification (MPEP 2144.04).
Regarding the first two paragraphs on p.14 of the response, the examiner directs applicant’s attention to the position(s) taken above. These paragraphs have already been substantially addressed.
Regarding the argument for claim 6 on p.14 of the response, applicant has not addressed the actual rejection, e.g., that it is obvious to parallelize operations thereon to speed up execution. In addition, the rejection addresses a broader interpretation of the claim where the stacks are simply powered on at the same time, e.g. as a result of applying power to memory which includes the stacks. Applicant has not addressed this rejection either. Thus, the claim 6 rejection is maintained.
Regarding the argument for claim 9 on pp.14-15 of the response, the argument is not persuasive. The combination prior to Poplingher already includes two stacks. The teachings of Poplingher would then apply to any stack in the system. That is, if there is no room on at least one of the stacks, then the system cannot store data as required and thus further nesting must be halted to avoid error (e.g. overwriting data already on the stack that is still needed, or exceeding the upper limit on the stack, etc.).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
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