DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/23/2025 has been entered.
Response to Amendment
Applicant's arguments filed 09/23/2025 regarding the rejection under 35 USC 112(b) have been fully considered but they are not persuasive.
The 112(b) rejection is rendered moot in light of claims 1, 11, and 17 limitations being amended.
Applicant's arguments filed 09/23/2025 regarding the rejection under 35 USC 101 have been fully considered but they are not persuasive.
Applicant argues, see especially page 6, “Applicant respectfully submits that claims, as amended, provide improvements in the way the circuit operates—reduced memory (e.g., no path history), fixed per-level work (e.g., one compare), and predictable, depth-bounded latency via a registered datapath. Additionally, the amended limitations a flip-flop clocked every cycle, a counter-indexed LUT, and a three-input adder generating translated memory addresses that drive subsequent memory reads—cycle- accurate hardware behavior that a person cannot practically perform in real time.” Examiner respectfully disagrees. The claims do not recite any details in the claim language that precludes the actions from being done in the human mind. The amended claim limitations merely recite extra solution of mere data storage, and generally linking the use of the judicial exception to a particular technological environment or field of use. While there is a statement made saying that the invention is directed to an improvement, there is no technical explanation of the improvements to the computer operations stated. This is nothing more than stating the intended purpose of the invention with no further explanation on how it improves over the prior art (MPEP 2106.04(d)(1))
The rejection under 35 USC 101 is maintained.
Applicant's arguments filed 05/22/2025 regarding the rejection under 35 USC 103 have been fully considered but they are not persuasive.
Applicant’s arguments with respect to claim(s) 1-8 and 10-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The rejection und 35 USC 103 is maintained.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 11, and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1, 11, and 17 recites the limitation store the translated memory address in a flip-flop as a next node address. This is indefinite because a flip flop is not well defined in the spec and the common definition of a flip flop states that it can only store one bit of data making it impossible for a flip flop to store an address pointer. However multiple flip flops can be used in a group to store more than one bit and a group of flip flops is commonly known as a register so this is how the claim will be interpreted henceforth.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Regarding claim 1, in Step 1 of the 101 analyses set forth in MPEP 2106, the claim recites an apparatus that process a multiple decision tree architecture. An apparatus is one of the four statutory categories.
In Step 2a Prong 1 of the 101 analyses set forth in the MPEP 2106, the examiner has determined that the following limitations recite a process that, under the broadest reasonable interpretation, covers a mental process but for recitation of generic computer components:
“determine a first result from processing a first node of a first decision tree of the multiple decision tree architecture based on a node value from the memory and a feature threshold; and” (a person can mentally process a decision tree node by simply evaluating the node features and the threshold value then making a judgment (MPEP 2106)).
“compute an address of a second node of the first decision tree based on the first result, a current node address, and a number of nodes in a level of the decision tree to which the current node address belongs” (a person can mentally compute the address of a second node by simply evaluating the equation to find the next node (MPEP 2106)).
increment a level counter by one each cycle, and reset the level counter and the current node address to a root node address when the level counter exceeds a preset total number of levels, (a person can mentally a person can mentally increment and reset a node counter and node addresses by a process of simply evaluating the node counter and address and making a judgement on what the node should be. (MPEP 2106)).
If claim limitations, under their broadest reasonable interpretation, covers performance of the limitations as a mental process but for the recitation of generic computer components, then it falls within the mental process grouping of abstract ideas. According, the claim “recites” an abstract idea.
In Step 2a Prong 2 of the 101 analyses set forth in MPEP 2106, the examiner has determined that the following additional elements do not integrate this judicial exception into a practical application:
“An apparatus comprising: a circuit for processing a multiple decision tree architecture the circuit couplable to a memory and configured to:” (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
“by an adder circuit configured to receive a current level value from a counter circuit, to produce a translated memory address for a next node; and” (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
store the translated memory address in a flip-flop as a next node address, (Adding insignificant extra-solution activity (mere data storage) to the judicial exception (MPEP 2106.05(g))).
the circuit performing a single comparison per level without storing a traversal path history. (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
Since the claim does not contain any other additional elements that are indicative of integration into a practical application, the claim is “directed” to an abstract idea.
In Step 2b of the 101 analyses set forth in the 2019 PEG, the examiner has determined that the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
“An apparatus comprising: a circuit for processing a multiple decision tree architecture the circuit couplable to a memory and configured to:” (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)) Furthermore, the additional element is directed to generally linking the use of the judicial exception to a particular technological environment or field of use, which is not indicative of significantly more.).
“by an adder circuit configured to receive a current level value from a counter circuit, to produce a translated memory address for a next node; and” (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)) Furthermore, the additional element is directed to generally linking the use of the judicial exception to a particular technological environment or field of use, which is not indicative of significantly more.).
store the translated memory address in a flip-flop as a next node address, (Adding insignificant extra-solution activity (mere data storage) to the judicial exception (MPEP 2106.05(g)) Furthermore, the additional element is directed to receiving or transmitting data over a network / performing repetitive calculations / electronic recordkeeping / storing and retrieving information in memory / electronically scanning or extracting data from a physical document, which the courts have recognized as well‐understood, routine, and conventional when they are claimed in a generic manner. See MPEP § 2106.05(d)(II).).
the circuit performing a single comparison per level without storing a traversal path history. (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)) Furthermore, the additional element is directed to generally linking the use of the judicial exception to a particular technological environment or field of use, which is not indicative of significantly more.).
Regarding Claim 2, it is dependent upon claim 1 and thereby incorporates the limitations of, and corresponding analysis applied to claim 2. “comprising the circuit further configured to process multiple nodes from different decision trees in parallel to obtain a decision from each decision tree of the multiple decision tree architecture. (In step 2A, Prong 2, and step 2B recites mere instructions to “apply” a computer product (machine learning algorithm) as a tool to implement the judicial exception. In step 2B, merely applying a computer tool is not indicative of significantly more)” Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible.
Regarding claim 3, it is dependent upon claim 2 and thereby incorporates the limitations of, and corresponding analysis applied to claim 2. Further claim 3 recites “comprising the circuit further configured to determine a final decision based on whether the multiple decision tree architecture is configured to process either a classification task or a regression task, (in step 2A, prong 1, this recites a mental process without significantly more. A determination is simply evaluating the classification or regression task and making a judgement.) where the multiple decision tree architecture is selectable to process both a classification task and a regression task.”(In step 2A, Prong 2, and step 2B this recites Generally linking the use of the judicial exception to a particular technological environment or field of use.) Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible.
Regarding claim 4, it is dependent upon claim 1 and thereby incorporates the limitations of, and corresponding analysis applied to claim 1. Further claim 4 recites “further comprising the memory and an interface configured (In step 2A, Prong 2, and step 2B this recites Generally linking the use of the judicial exception to a particular technological environment or field of use.) to allow· storage of node specific data for the multiple decision tree architecture to be stored to the memory, (In step 2A, Prong 2, this recites insignificant extra solution activity of mere data storage which is not indicative of integration into a practical application. In step 2B, this recites a step that stores and retrieves information in memory, which has been determined by the courts to recite a well understood, routine and conventional activity which is not indicative of significantly more (See MPEP 2106.05(d)(II)) the node specific data representing values for each node of the multiple decision tree architecture .(In step 2A, Prong 2, and Step 2B this recites Generally linking the use of the judicial exception to a particular technological environment or field of use)” Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible.
Regarding claim 5, it is dependent upon claim 4 and thereby incorporates the limitations of, and corresponding analysis applied to claim 5. Further claim 4 recites “comprising the node specific data determined (in step 2A, prong 1, this recites a mental process without significantly more. A determination is simply evaluating the data and making a judgement.) via an external data processing system (In step 2A, Prong 2, and step 2B this recites a generic computer tool used to perform the abstract idea) and each node specific data indicates a feature and a feature threshold”. (In step 2A, Prong 2, and step 2B this recites Generally linking the use of the judicial exception to a particular technological environment or field of use). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible.
Regarding claim 6, it is dependent upon claim 1 and thereby incorporates the limitations of, and corresponding analysis applied to claim 1. Further claim 6 recites “… determine a number of nodes at each depth level of the multiple decision tree architecture …”(in step 2A, prong 1, this recites a mental process without significantly more. A determination is simply evaluating the data and making a judgement.) “further comprising the circuit including a memory storing a lookup table (LUT) to … (In step 2A, Prong 2, and step 2Bthis recites Generally linking the use of the judicial exception to a particular technological environment or field of use) …, where an input to the LUT is a counter that represents a depth level of the first decision tree the circuit is actively processing. (In step 2A, Prong 2, and step 2B this recites Generally linking the use of the judicial exception to a particular technological environment or field of use). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible.
Regarding claim 7, it is dependent upon claim 6 and thereby incorporates the limitations of, and corresponding analysis applied to claim 6. Further claim 7 recites “…determine if a value of a selected node is greater than the feature threshold.” (in step 2A, prong 1, this recites a mental process without significantly more. A comparison is simply evaluating two things and making a judgment as to which is greater.) further comprising the circuit including a comparator circuit to… (In step 2A, Prong 2, this recites Generally linking the use of the judicial exception to a particular technological environment or field of use.) Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible.
Regarding claim 8, it is dependent upon claim 7 and thereby incorporates the limitations of, and corresponding analysis applied to claim 7. Further claim 8 recites “…add a result of the comparator circuit, the number of nodes in a current depth level, and a current node address to compute a next node address. (in step 2A, prong 1, this recites a mental process without significantly more. Addition is simply evaluating an equation)”. “further comprising the circuit including an adder circuit configured to… (In step 2A, Prong 2, this recites Generally linking the use of the judicial exception to a particular technological environment or field of use)”. Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible.
Claim 9 – Canceled
Regarding Claim 10, it is dependent upon claim 1 and thereby incorporates the limitations of, and corresponding analysis applied to claim 2. “further comprising multiple of the circuit configured to operate in parallel to process multiple decision trees simultaneously (In step 2A, Prong 2, recites mere instructions to “apply” a computer product (machine learning algorithm) as a tool to implement the judicial exception. In step 2B, merely applying a computer tool is not indicative of significantly more).” Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible.
Regarding claim 11, in Step 1 of the 101 analyses set forth in MPEP 2106, the claim recites A circuit. A circuit is a machine which is one of the four statutory categories.
In Step 2a Pong 1 of the 101 analyses set forth in the MPEP 2106, the examiner has determined that the following limitations recite a process that, under the broadest reasonable interpretation, covers a mental process but for recitation of generic computer components:
“compare the data and the threshold to determine an output;” (a person can mentally compare data to a threshold by a process of simply evaluating the data and threshold and making a judgement on if the threshold is met by the data (MPEP 2106)).
“calculate a next node address based on the output, the current node address, and the number of nodes at the current depth level, where the next node address is a next selected node to be processed by the comparator circuit” (a person can mentally do calculations by a process of simply evaluating the variables and make a judgement on the solution of the calculation (MPEP 2106)).
increment a level counter by one each cycle, and reset the level counter and the current node address to a root node address when the level counter exceeds a preset total number of levels, (a person can mentally a person can mentally increment and reset a node counter and node addresses by a process of simply evaluating the node counter and address and making a judgement on what the node should be. (MPEP 2106)).
If claim limitations, under their broadest reasonable interpretation, covers performance of the limitations as a mental process but for the recitation of generic computer components, then it falls within the mental process grouping of abstract ideas. According, the claim “recites” an abstract idea.
In Step 2a Prong 2 of the 101 analyses set forth in MPEP 2106, the examiner has determined that the following additional elements do not integrate this judicial exception into a practical application:
“a memory storing data representing node values of a decision tree; a comparator circuit configured to:” (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
“receive data from the memory for a selected node of the decision tree and receive a threshold;” (Adding insignificant extra-solution activity (mere data gathering) to the judicial exception (MPEP 2106.05(g))).
“and an adder circuit configured to” (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
“receive the output, a current node address, and a number of nodes at a current depth level of the decision tree; and” (Adding insignificant extra-solution activity (mere data gathering) to the judicial exception (MPEP 2106.05(g))).
And store a translated memory address associated with the next node in a flip-flop as a next node address, (Adding insignificant extra-solution activity (mere data storage) to the judicial exception (MPEP 2106.05(g))).
the circuit performing a single comparison per level without storing a traversal path history; (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
“wherein the adder circuit is coupled to a counter circuit to receive a current level value. (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
Since the claim does not contain any other additional elements that are indicative of integration into a practical application, the claim is “directed” to an abstract idea.
In Step 2b of the 101 analyses set forth in the 2019 PEG, the examiner has determined that the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
“a memory storing data representing node values of a decision tree; a comparator circuit configured to:” (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
“receive data from the memory for a selected node of the decision tree and receive a threshold;” (Adding insignificant extra-solution activity (mere data gathering) to the judicial exception (MPEP 2106.05(g)) Furthermore, the additional element is directed to generally linking the use of the judicial exception to a particular technological environment or field of use, which is not indicative of significantly more.).
“and an adder circuit configured to” (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)) Furthermore, the additional element is directed to generally linking the use of the judicial exception to a particular technological environment or field of use, which is not indicative of significantly more.).
“receive the output, a current node address, and a number of nodes at a current depth level of the decision tree; and” (Adding insignificant extra-solution activity (mere data gathering) to the judicial exception (MPEP 2106.05(g)) Furthermore, the additional element is directed to receiving or transmitting data over a network / performing repetitive calculations / electronic recordkeeping / storing and retrieving information in memory / electronically scanning or extracting data from a physical document, which the courts have recognized as well‐understood, routine, and conventional when they are claimed in a generic manner. See MPEP § 2106.05(d)(II).).
And store a translated memory address associated with the next node in a flip-flop as a next node address, (Adding insignificant extra-solution activity (mere data storage) to the judicial exception (MPEP 2106.05(g)) Furthermore, the additional element is directed to receiving or transmitting data over a network / performing repetitive calculations / electronic recordkeeping / storing and retrieving information in memory / electronically scanning or extracting data from a physical document, which the courts have recognized as well‐understood, routine, and conventional when they are claimed in a generic manner. See MPEP § 2106.05(d)(II).).
the circuit performing a single comparison per level without storing a traversal path history; (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)) Furthermore, the additional element is directed to generally linking the use of the judicial exception to a particular technological environment or field of use, which is not indicative of significantly more.).
Regarding claim 12, it is dependent upon claim 11 and thereby incorporates the limitations of, and corresponding analysis applied to claim 11. Further claim 12 recites “wherein the adder circuit is coupled to a counter circuit to receive a current level value. (Generally linking the use of the judicial exception Regarding claim 12, it is dependent upon claim 11 and thereby incorporates the limitations of, and corresponding analysis applied to claim 11. Further claim 12 recites “further comprising: a counter circuit that indicates the current depth level of the decision tree; (In step 2A, Prong 2, and step 2Bthis recites Generally linking the use of the judicial exception to a particular technological environment or field of use) and a lookup table (LUT) circuit configured to output the number of nodes at the current depth level based on a value of the counter circuit. (In step 2A, Prong 2, and step 2B this recites Generally linking the use of the judicial exception to a particular technological environment or field of use). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible.
Regarding claim 13, it is dependent upon claim 11 and thereby incorporates the limitations of, and corresponding analysis applied to claim 11. Further claim 13 recites “further comprising multiple decision trees represented via the data and a decision accumulator, where the circuit is configured to process more than one of the multiple decision trees, and the decision accumulator is configured to determine a final decision based on a decision of each of the multiple decision trees.” (In step 2A, Prong 2, and step 2B this recites Generally linking the use of the judicial exception to a particular technological environment or field of use). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible.
Regarding claim 14, it is dependent upon claim 13 and thereby incorporates the limitations of, and corresponding analysis applied to claim 13. Further claim 14 recites “further configured to: determine the final decision based on a classification determination; (in step 2A, prong 1, this recites a mental process without significantly more. A determination is simply evaluating the classification task and make a judgement.on what the final decision should be) determine the final decision based on a regression determination; (in step 2A, prong 1, this recites a mental process without significantly more. A determination is simply evaluating the regression task and make a judgement.on what the final decision should be) and selectively implement the classification determination and the regression determination.” (In step 2A, Prong 2, and step 2B this recites Generally linking the use of the judicial exception to a particular technological environment or field of use). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible.
Regarding claim 15, it is dependent upon claim 11 and thereby incorporates the limitations of, and corresponding analysis applied to claim 11. Further claim 15 recites “further comprising an interface coupled to the memory and configured to receive the data representing node values from an external system.” (In step 2A, Prong 2, this recites insignificant extra solution activity of mere data transfer which is not indicative of integration into a practical application. In step 2B, this recites a step that stores and retrieves information in memory, which has been determined by the courts to recite a well understood, routine and conventional activity which is not indicative of significantly more (See MPEP 2106.05(d)(II))).
Regarding claim 16, it is dependent upon claim 11 and thereby incorporates the limitations of, and corresponding analysis applied to claim 11. Further claim 16 recites “further comprising the circuit is a processing circuit implementing a Random Forest architecture and the data includes a feature and feature threshold for every node in the Random Forest architecture.” (In step 2A, Prong 2, and step 2B this recites Generally linking the use of the judicial exception to a particular technological environment or field of use). Since the claim does not recite additional elements that either integrate the judicial exception into a practical application, nor provide significantly more than the judicial exception, the claim is not patent eligible.
Regarding claim 17, in Step 1 of the 101 analyses set forth in MPEP 2106, the claim recites A method. A method is one of the four statutory categories.
In Step 2a Pong 1 of the 101 analyses set forth in the MPEP 2106, the examiner has determined that the following limitations recite a process that, under the broadest reasonable interpretation, covers a mental process but for recitation of generic computer components:
“processing, …3 a first node of a selected level of a Random Forest architecture having a decision tree with multiple levels,” (a person can mentally process a first node of a random forest by a process of simply evaluating the first node and making a judgement on how the node is handled (MPEP 2106)).
“calculating, …4, an address of a second node at a next level of the decision tree based on the first decision, the first node's address, and a number of nodes at the selected level;” (a person can mentally do a calculation by a process of simply evaluating the variables and making a judgement on what the output should be (MPEP 2106)).
incrementing a level counter by one each cycle, and resetting the level counter and a current node address to a root node address when the level counter exceeds a preset total number of levels, (a person can mentally a person can mentally increment and reset a node counter and node addresses by a process of simply evaluating the node counter and address and making a judgement on what the node should be. (MPEP 2106)).
“repeating the processing and the calculating for each of the multiple levels of the decision tree before reaching a last level of the decision tree;” (a person can mentally repeat a process by a simple process of evaluating the process and redoing the process again. (MPEP 2106))
If claim limitations, under their broadest reasonable interpretation, covers performance of the limitations as a mental process but for the recitation of generic computer components, then it falls within the mental process grouping of abstract ideas. According, the claim “recites” an abstract idea.
In Step 2a Prong 2 of the 101 analyses set forth in MPEP 2106, the examiner has determined that the following additional elements do not integrate this judicial exception into a practical application:
“…3 via a comparator circuit, …” (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
“the comparator circuit configured to produce a first decision;” (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
“…4via an adder circuit…” (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
storing a translated memory address in a flip-flop as a second node address, (Adding insignificant extra-solution activity (mere data storage) to the judicial exception (MPEP 2106.05(g))).
the circuit performing a single comparison per level without storing a traversal path history (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
“and obtaining an output of the decision tree based on an address of a last node in the last level that was calculated via the adder circuit;” (Adding insignificant extra-solution activity (mere data gathering) to the judicial exception (MPEP 2106.05(g))).
“wherein the adder circuit is coupled to a counter circuit to receive a current level value” (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
Since the claim does not contain any other additional elements that are indicative of integration into a practical application, the claim is “directed” to an abstract idea.
In Step 2b of the 101 analyses set forth in the 2019 PEG, the examiner has determined that the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
“…3 via a comparator circuit, …” (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)) Furthermore, the additional element is directed to generally linking the use of the judicial exception to a particular technological environment or field of use, which is not indicative of significantly more.).
“the comparator circuit configured to produce a first decision;” (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)) Furthermore, the additional element is directed to generally linking the use of the judicial exception to a particular technological environment or field of use, which is not indicative of significantly more.).
“…4via an adder circuit…” (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)) Furthermore, the additional element is directed to generally linking the use of the judicial exception to a particular technological environment or field of use, which is not indicative of significantly more.).
storing a translated memory address in a flip-flop as a second node address, (Adding insignificant extra-solution activity (mere data storage) to the judicial exception (MPEP 2106.05(g)) Furthermore, the additional element is directed to receiving or transmitting data over a network / performing repetitive calculations / electronic recordkeeping / storing and retrieving information in memory / electronically scanning or extracting data from a physical document, which the courts have recognized as well‐understood, routine, and conventional when they are claimed in a generic manner. See MPEP § 2106.05(d)(II).).
the circuit performing a single comparison per level without storing a traversal path history (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)) Furthermore, the additional element is directed to generally linking the use of the judicial exception to a particular technological environment or field of use, which is not indicative of significantly more.).
“and obtaining an output of the decision tree based on an address of a last node in the last level that was calculated via the adder circuit;” (Adding insignificant extra-solution activity (mere data gathering) to the judicial exception (MPEP 2106.05(g)) Furthermore, the additional element is directed to receiving or transmitting data over a network / performing repetitive calculations / electronic recordkeeping / storing and retrieving information in memory / electronically scanning or extracting data from a physical document, which the courts have recognized as well‐understood, routine, and conventional when they are claimed in a generic manner. See MPEP § 2106.05(d)(II).).
“wherein the adder circuit is coupled to a counter circuit to receive a current level value” (Generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)) Furthermore, the additional element is directed to generally linking the use of the judicial exception to a particular technological environment or field of use, which is not indicative of significantly more.).
Regarding claim 18, it is dependent upon claim 17 and thereby incorporates the limitations of, and corresponding analysis applied to claim 17. Further claim 18 recites “further comprising processing multiple decision trees to arrive at multiple decisions, with each processed decision tree providing a respective decision, and determining a final decision based on the multiple decisions.” (in step 2A, prong 1, this recites a mental process without significantly more. A determination is simply evaluating the multiple decision trees and making a judgment on what the final decision for each tree should be and what the final decision should be.)
Regarding claim 19, it is dependent upon claim 18 and thereby incorporates the limitations of, and corresponding analysis applied to claim 18. Further claim 19 recites “further selecting one of a classification task and a regression task to determine the final decision.” (in step 2A, prong 1, this recites a mental process without significantly more. A selection is simply evaluating the task and a judgment weather the final decision should be made through classification and regression.)
Regarding claim 20, it is dependent upon claim 17 and thereby incorporates the limitations of, and corresponding analysis applied to claim 17. Further claim 20 recites “further comprising calculating the first decision based on a feature associated with the first node and a feature threshold, where each node has an associated feature and feature threshold that is stored in a memory.” (in step 2A, prong 1, this recites a mental process without significantly more. A calculation is simply evaluating the data and making a judgement on what the decision should be.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 11, 13, 15-18, and 20 are rejected under 35 U.S.C. 103 as being anticipated by Van Essen et al., “Accelerating a random forest classifier: multi-core, GP-GPU, or FPGA” in view of Barringer et al., “Dynamic Stackless Binary Tree Traversal”.
Regarding Claim 1, VanEssen teaches an apparatus comprising: a circuit (VanEssen pg. 235, Figs. 3&4, Demonstrates decision tree logic Implemented on an FPGA (field programable gate array, that is a circuit) for processing a multiple decision tree architecture, (VanEssen, pg. 232, 1st column, 1st paragraph of Introduction, “an ensemble of decision trees is used to assign a label to an input sample”) the circuit couplable to a memory and (VanEssen pg. 235, Figs. 3&4, Show the FPGAs coupled to memory) configured to: determine a first result from processing a first node of a first decision tree of the multiple decision tree architecture based on a node value from the memory and a feature threshold;( VanEssen pg. 235, Figs. 3&4, Show the processing of a node representing the first node in the decision tree and is also shown that the circuit receives feat_idx (i.e. node value) and threshold (i.e. feature threshold) from memory) compute an address of a second node of the first decision tree based on the first result, a current node address, and a number of nodes in a level of the decision tree to which the current node address belongs, (VanEssen, pg.234, 1st column, Code Snippet, where node_id = (node_id << 1) + (feature < threshold) is equivalent to (second node = (current node address << 1) + (first result) where bit shifting one to the left is doubling the binary number and since a tree has twice as many nodes on the next level as this one this is equivalent to using a number of nodes at a current level) by an adder circuit configured to receive a current level value from a counter circuit, (VanEssen, pg.234, 1st column, teaches “node_id = (node_id << 1) + (feature < threshold)” which is stated in section V to be implemented into hardware, and since there is an addition operation that constitutes the inclusion of an adder circuit in the hardware implementation. Further since a loop is being performed that calculated the current level “for (int lvl = 0; lvl < max_depth; lvl++) {// Tree” and the level is used to determine the how the adder circuit operates “if (lvl < max_depth - 1) { // Split node” the adder circuit is receiving the current level from a counter circuit) …1 , to produce a translated memory address for a next node. (VanEssen, pg.234, 1st column, teaches “node_id = (node_id << 1) + (feature < threshold);” where the node_id represents the current address being bit shifted by 1 representing the address adding an offset of double the current value. Further it is added to a comparator result to generate a translated node address for the next node.) and store the translated memory address in a flip-flop as a next node address, (VanEssen, pg. 235, Fig. 3, demonstrates the FPGA storing the calculated next address in a register A flip flop is interpreted to mean multiple flip flops since a single flip flop is incapable of storing an address on its own. Multiple flip flops or a group of flip flops are then further interpreted to mean a register since a register is a group of flip flops). increment a level counter by one each cycle, and reset the level counter and the current node address to a root node address when the level counter exceeds a preset total number of levels, 2… (VanEssen, pg. 234, Section IV, teaches the incrementing of a level counter by one each cycle. Further VanEssen teaches the counter and the current node address being reset and set to a root node when a threshold (i.e. max_depth) is met.)
VanEssen does not teach 2… the circuit performing a single comparison per level without storing a traversal path history. However, Barringer in analogous art teaches this limitation (Barringer, page 39-44, section 2, teaches the traversal of binary decision (i.e. single comparison per level) trees by calculations and does not maintain a stack recording the path taken (i.e. without storing path history).)
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to combine Barringer’s teaching of a not storing a traversal path with VanEssen’s teaching of a decision tree processing system. The motivation to do so would be to lower the computational and storage costs of processing decision trees allowing them to be processed faster and more efficiently.
Regarding Claim 2, The combination of VanEssen and Barringer teaches the apparatus of claim 1 (and thus the rejection of Claim 1 is incorporated) comprising the circuit further configured to process multiple nodes from different decision trees in parallel (VanEssen, pg.234, 1st column, 1st paragraph of Using OpenMP on a Shared-Memory Multiprocessor “In software, the classification task can be implemented as a doubly nested loop that iterates over samples and trees in the forest. The following code snippet shows the kernel of the classification routine that will be used as the basis for the FPGA and GP-GPU designs… We have found that the most effective way to parallelize this code with OpenMP is to exploit the data parallelism between samples and process each sample independently”) to obtain a decision from each decision tree of the multiple decision tree architecture (VanEssen, pg.234, 1st column, Code Snippet, (see claim 1) where response (decision from each decision tree of the multiple decision tree architecture) += localresult).
Regarding Claim 4, The combination of VanEssen and Barringer teaches the apparatus of claim 1 (and thus the rejection of Claim 1 is incorporated) further comprising the memory and an interface configured to allow storage of node specific data for the multiple decision tree architecture to be stored to the memory (VanEssen, pg. 235. Figs.3&4, The memory in these figures stores the threshold and feat_idx (i.e. node specific data) via an interface that is not disclosed but necessary to allow the node variables to be stored in the first place)., the node specific data representing values for each node of the multiple decision tree architecture (VanEssen, pg. 234, Figs 3 & 4 shows the node specific data being stored for each node in the memory under the section called Node Variables such as feat_idx and threshold).
Regarding Claim 5 The combination of VanEssen and Barringer teaches The apparatus of claim 4 (and thus the rejections of Claim 1 and 4 are incorporated) further comprising the node specific data determined via an external data processing system (VanEssen, pg. 232, 1st column, 1st paragraph of Introduction, “…classification using random forests generated by an off-line machine learning algorithm(i.e. external data processing system)”) and each node specific data indicates a feature and a feature threshold (VanEssen, pg. 235, 2nd column, 9th paragraph of FPGA Implementation, “Internal stages require a feature index and threshold value for each node,.”).
Claim 9 – Canceled
Regarding Claim 10 The combination of VanEssen and Barringer teaches The apparatus of claim 1 (and thus the rejections of Claim 1 is incorporated) further comprising multiple of the circuit configured to operate in parallel to process multiple decision trees simultaneously (VanEssen, pg. 233, 1st column, 3rd paragraph of Challenges and Opportunities, “On the FPGA, the processing of each decision tree(i.e. multiple decision trees) can be executed in parallel(i.e. parallel and simultaneously) by independent hardware(i.e. multiple of the circuit) and the processing of each tree can be pipelined.”).
Regarding Claim 11 VanEssen teaches A circuit comprising: a memory storing data representing node values of a decision tree a comparator circuit configured to: receive data from the memory for a selected node of the decision tree and receive a threshold compare the data and the threshold to determine an output and an adder circuit configured to receive the output, a current node address, and a number of nodes at a current depth level of the decision tree(VanEssen, pg.235, Figs.3&4, Demonstrates decision tree logic Implemented on an FPGA (field programable gate array, that is a circuit) including memory storing node values (i.e. feat_idx and threshold), A comparator circuit that receives node data from memory including the aforementioned threshold and compares them to determine a result, and then also feeds that result (i.e. the output) to an adder circuit that also receives node_idx_q1(i.e. current node address) that has been bit shifted 1 to the left (bit shifting 1 to the left is doubling the binary address which is equivalent to using a number of nodes at a current depth level of the decision tree since there are twice as many nodes in the next level as there are on the current level of the tree).): and calculate a next node address based on the output, the current node address, and the number of nodes at the current depth level, where the next node address is a next selected node to be processed by the comparator circuit, (VanEssen, pg.234, Code Snippet, Where the adders function is represented by: node_id(next node address) = (node_id(current node address) << 1(bit shifting one to the left is doubling the binary number and since a tree has twice as many nodes on the next level as this one this is equivalent to using the number of nodes at the current depth level)) + (feature < threshold)(output) and store a translated memory address associated with the next node in a flip-flop as a next node address, increment a level counter by one each cycle, and reset the level counter and the current node address to a root node address when the level counter exceeds a preset total number of levels, (VanEssen, pg. 234, Section IV, teaches the incrementing of a level counter by one each cycle. Further VanEssen teaches the counter and the current node address being reset and set to a root node when a threshold (i.e. max_depth) is met.) wherein the adder circuit is coupled to a counter circuit to receive a current level value, (VanEssen, pg.234, 1st column, teaches “node_id = (node_id << 1) + (feature < threshold)” which is stated in section