DETAILED ACTION
Response to Arguments
Applicant's arguments filed have been fully considered but they are not persuasive.
Regarding claims 1 and 24, applicant argued on page 11 of arguments that the references do not teach the die overlapping the metal interconnects in the void-defined section in first metal structure because the teaching of Degani that the die is coupled to the dummy circuit 140 of Takiar would contradict the teaching of Takiar that the dummy circuit 130 are in areas not occupied by the conductance pattern. See par [0010] of Takiar. However, Takiar teaches that the "dummy circuit pattern may carry signals to and/ or from the semiconductor die". See par [0057] of Takiar. Therefore, one or ordinary skill in the art would connect the dummy circuit pattern of Takiar to the flip chip micro-joints as taught in Degani in order to provide the IC chip with a high number of input-output interconnections. Claims 1 and 24 remain rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5-9, 11, 13-21, 23-24, 27-29, and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Takiar et la. (WO 2007/005492) (“Takiar”) in view of Degani et al. (US 6,175,158) (“Degani”).
With regard to claim 1, figs. 2-3 and 10 of Takiar discloses a die module package, comprising: a package substrate 100, comprising: a plurality of metal structures (108, 110) parallel to each other in a horizontal direction and sharing a common vertical plane (108, 110), each metal structure (108, 110) among the plurality of metal structures (108, 110) comprising: a metal material (“conductive layers 108 and 110 may be formed of copper”, par [0030]) having a first coefficient of thermal expansion (CTE); a void-defined section (“honeycomb pattern 130”, par [0039]) comprising a plurality of voids (“hexagonal”, par [0039]) disposed in the metal structure 108; one or more metal interconnects 120 each formed by the metal material (“copper”, par [0030]) in the metal structure 108 disposed between (between dummy circuit 130 to the top and dummy circuit 130 on the bottom left of fig. 2) and adjacent voids (top 130 and bottom left 130 in fig. 2) among the plurality of voids 130; and a dielectric material 112 having a second CTE (“solder mask 112”, par [0053]) disposed in at least one void 130’ among the plurality of voids 130 in the void-defined section 130, the second CTE of the dielectric material 112 less than the first CTE of the metal material (“copper”, par [0030]); a die 184 disposed adjacent to the package substrate 100; and at least one die interconnect 188 each coupled to the die 184 and each coupled (“die 184 may be electrically connected to conductive layers 108, 110 of the substrate 100 by wire bonds 188”, par [0056]) to a metal interconnect 120 among the one or more metal interconnects 120 in the void- defined section 130 of a first metal structure 108 among the plurality of metal structures (108, 110).
Takiar does not disclose that at least a portion of an area of the die is oriented to the package substrate to at least partially overlap the one or more metal interconnects in the void-defined section in the first metal structure in a vertical plane.
However, figs. 2-3 of Degani discloses that at least a portion of an area of the die 15 is oriented to the package substrate 21 to at least partially overlap the one or more metal interconnects 39 in the void-defined section (between 36 and 37) in the first metal structure (36, 37) in a vertical plane (15 overlaps 39, fig. 3).
Therefore, it would have been obvious to one of ordinary skill in the art to electrically connect the die to the conductive layers of the substrate of Takiar by flip chip micro-joints as taught in Degani in order to provide the IC chip with a high number of input/output interconnections. See col. 5 ll. 41-43 of Degani.
With regard to claims 3 and 27, figs. 2-3 and 10 of Takiar discloses that the package substrate 100 comprises a plurality of metallization layers (108, 110) parallel to each other; and each metal structure (108, 110) among the plurality of metal structures (108, 110) is disposed in a different metallization layer 110 among the plurality of metallization layers (108, 110).
With regard to claims 5 and 28, figs. 2-3 and 10 of Takiar discloses that the plurality of voids 130 disposed in the metal structure 108 are each completely surrounded by and coupled to the metal material 108 in the metal structure 108.
With regard to claim 6, figs. 2-3 and 10 of Takiar discloses each metal structure 108 of the plurality of metal structures 108 comprises a ground plane (“dummy circuit pattern may provide a path to ground (VSS)”, par [0057]).
With regard to claims 7 and 29, figs. 2-3 and 10 of Takiar discloses that the plurality of voids (voids in dummy circuit pattern 130) in each metal structure 130 has an area that is at least thirty percent (30%) (voids in the dummy circuit pattern 130 makes up at least 30% of the area of dummy circuit pattern 130 in fig. 2) of an area of the metal structure 130.
With regard to claim 8, figs. 2-3 and 10 of Takiar discloses that the plurality of voids (voids of 130) form a perimeter of the void-defined section 130 in the metal structure 130.
With regard to claim 9, figs. 2-3 and 10 of Takiar discloses that the plurality of voids (voids of 130) have a first area (area of voids) that at least eighty-five percent (85%) of a second area of the perimeter (area of pattern 130 at perimeter of 130).
With regard to claims 11 and 31, figs. 2-3 and 10 of Takiar disclose that the first CTE of the metal material (“copper”, par [0030]) of the metal structure 108 is between 13 parts per million (ppm) per Kelvin (K) (ppm/K) and 24 ppm/K (“copper (thermal expansion coefficient: 16.8 (ppm/K))”, par [0142] of Kawamura et al. (US 2021/0084750) (“Kawamura”) cited to show the inherent characteristic of copper. See MPEP sec 2131.01 III.)
With regard to claim 13, figs. 2-3 and 10 of Takiar disclose that the plurality of voids (void in 130, fig. 2) in at least one metal structure 108 among the plurality of metal structures 108 are formed in a repeated pattern 130 in the metal structure 108.
With regard to claim 14, figs. 2-3 and 10 of Takiar disclose that each of the plurality of voids (voids in 130, fig. 2) in at least one metal structure 108 among the plurality of metal structures 108 has a same first pitch in a first direction (direction from left to right in fig. 2) of a first axis and has a same second pitch in a second direction (direction from top to bottom in fig. 2) of a second axis orthogonal to the first axis.
With regard to claim 15, figs. 2-3 and 10 of Takiar disclose that each of the plurality of voids (voids in 130, fig. 2) in at least one metal structure 108 among the plurality of metal structures (108, 110) comprises an elongated void (void of 130) having a first length in a first direction (direction from left to right in fig. 2) of a first axis and a second length in a second direction (direction from top to bottom in fig. 2) in a second axis (top to bottom) orthogonal to the first axis (left to right), wherein the second length is equal (“hexagonal”, par [0039]) to the first length.
With regard to claim 16, fig. 2 of Takiar disclose that each of the plurality of voids (voids of 130) in at least one metal structure among the plurality of metal structures 108 comprises an elongated void (voids of 130) having a first length in a first direction (top to bottom) of a first axis and a second length in a second direction (left to right) in a second axis (left to right) orthogonal to the first axis (top to bottom).
Fig. 2 of Takiar does not disclose that the second length is less than the first length.
However, fig. 7 of Takiar disclose that the second length (length from left to right of letter “C” shape 170’) is less than the first length.
Therefore, it would have been obvious to one of ordinary skill in the art to form the dummy circuit pattern shapes of fig. 2 of Takiar into the letter “C” as taught in fig. 7 of Takiar in order to provide curved shaped that have an advantage in that stresses within the shape are minimized. See par [0050] of Takiar.
With regard to claim 17, figs. 2-3 and 10 of Takiar disclose at least one metal structure 130 among the plurality of metal structures (108, 110) is uniformly deformable (“hexagonal”, par [0039]) along at least two orthogonal axes (left to right and top to bottom, fig. 2).
With regard to claim 18, figs. 2-3 of 10 of Takiar discloses that the plurality of voids (voids in 130) in at least one metal structure 108 among the plurality of metal structures (108, 110) have the same pitch.
With regard to claim 19, fig. 2 of Takiar does not disclose a subset of voids among the plurality of voids in at least one metal structure among the plurality of metal structures are elongated along the same axis.
However, fig. 7 of Takiar discloses a subset of voids 170’ among the plurality of voids 170’ in at least one metal structure among the plurality of metal structures are elongated along the same axis (top to bottom in fig. 7).
Therefore, it would have been obvious to one of ordinary skill in the art to form the dummy circuit pattern shapes of fig. 2 of Takiar into the letter “C” as taught in fig. 7 of Takiar in order to provide curved shaped that have an advantage in that stresses within the shape are minimized. See par [0050] of Takiar.
With regard to claim 20, figs. 2-3 of 10 of Takiar discloses that the void-defined section 130 in at least one metal structure 108 among the plurality of metal structures 108 is a square-shaped (“squares”, par [0039]) void- defined section comprising a plurality of straight voids (“squares”, par [0039]) disposed along a square-shaped perimeter (“squares”, par [0039]) forming a perimeter of the void-defined section.
With regard to claim 21, figs. 2-3 of 10 of Takiar discloses that the void-defined section 130 in at least one metal structure 108 among the plurality of metal structures (108, 110) is a circular-shaped (“contiguous circles”, par [0039]) void- defined section comprising a plurality of convex voids disposed along a circular-shaped perimeter (“contiguous circles”, par [0039]) forming a perimeter of the void-defined section 130.
With regard to claim 23, figs. 2-3 of 10 of Takiar discloses the die module package integrated into a personal digital assistant (PDA) (“PDAs”, par [0004]).
With regard to claim 24, figs 2-3 of 10 of Takiar discloses a method of fabricating a die module package, comprising: forming a package substrate 100, comprising: forming a plurality of metal structures (108, 110) parallel to each other in a horizontal direction and sharing a common vertical plane, each metal structure (108, 110) among the plurality of metal structures (108, 110) comprising: a metal material (“conductive layers 108 and 110 may be formed of copper”, par [0030]) having a first coefficient of thermal expansion (CTE) (CTE of copper); a void-defined section 130 comprising a plurality of voids (void in 130) disposed in the metal structure 108; one or more metal interconnects 120 each formed by the metal material (“copper”, par [0030]) in the metal structure 130 disposed between adjacent voids (void in 130) among the plurality of voids (void in 130); and a dielectric material 112 having a second CTE (CTE of solder mask) disposed in at least one void (void in 130) among the plurality of voids (voids in 130) in the void-defined section 130, the second CTE (CTE of solder mask) of the dielectric material less than the first CTE (CTE of copper) of the metal material (“copper”, par [0030]); forming at least one die interconnect 188 coupled to at least one metal interconnect 120 among the one or more metal interconnects (108, 110) in the void-defined section 130 a metal structure 108 among the plurality of metal structures (108, 110); and coupling a die 184 to the at least one die interconnect 188.
Takiar does not disclose coupling the die to the at least one die interconnect further comprises disposing at least a portion of an area of the die oriented to the package substrate to at least partially overlap the one or more metal interconnects in the void-defined section in the first metal structure in a vertical plane.
However, figs. 2-3 of Degani discloses coupling the die 15 to the at least one die interconnect (“IC chip interconnections”, col. 5 ll. 42) further comprises disposing at least a portion of an area of the die 15 oriented to the package substrate 21 to at least partially overlap the one or more metal interconnects 39 in the void-defined section (between 36 and 37) in the first metal structure (36, 37) in a vertical plane.
Therefore, it would have been obvious to one of ordinary skill in the art to electrically connect the die to the conductive layers of the substrate of Takiar by flip chip micro-joints as taught in Degani in order to provide the IC chip with a high number of input/output interconnections. See col. 5 ll. 41-43 of Degani.
Claims 4 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Takiar et la. (WO 2007/005492) (“Takiar”), Degani et al. (US 6,175,158) (“Degani”), and Tzuang Yang et al. (US 9,978,699) (“Tzuang”).
With regard to claims 4 and 26, figs. 2-3 and 10 of Takiar disclose the first metal structure 108 among the plurality of metal structures (108, 110) is disposed in the first metallization layer 108 among the plurality of metallization layers (108, 110); a second metal structure 110 among the plurality of metal structures (108, 110) is disposed in a second metallization layer 110 among the plurality of metallization layers (108, 110) different from the first metallization layer 108; and further comprising: at least one vertical interconnect access (via) (“vias (not shown) may be provided to transmit electrical signals between the conductance patterns in different layers”, par [0032]) disposed through the plurality of voids 130 in the void-defined section 130 of the first metal structure 108; each via (“vias”, par [0032]) of the at least one via (“vias”, par [0032]) coupled to a metal interconnect 120 among the one or more metal interconnects (108, 110) in the void-defined section 130 of the second metal structure 110.
Takiar and Degani do not disclose a via disposed through a respective void.
However, fig. 4A of Tzuang discloses a via 120 disposed through a respective void 130.
Therefore, it would have been obvious to one of ordinary skill in the art to form the dummy circuit pattern of Takiar surrounding the vertical metal via as taught in Tzuang in order to reduce the interference between different signal lines. See col. 7 ll. 59-60 of Tzuang.
Claims 10 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Takiar et la. (WO 2007/005492) (“Takiar”), Degani et al. (US 6,175,158) (“Degani”), and Shibata et al. (US 2020/0105656) (“Shitbata”).
With regard to claims 10 and 30, figs. 2-3 and 10 of Takiar discloses that the void-defined section 130 of the metal structure 130.
Takiar and Degani do not disclose that the metal structure has a Young's modulus between 100 MegaPascal (MPa) and 50 GigaPascal (GPa).
However, fig. 2 of Shibata discloses that the metal structure 5 has a Young's modulus between 100 MegaPascal (MPa) and 50 GigaPascal (GPa) (“50 GPa”, par [0083]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the dummy circuit pattern of Takiar with the elastic modulus as taught in Shibata in order to provide a conductive pattern made of copper. See par [0082]-[0083] of Shibata.
Claims 12 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Takiar et la. (WO 2007/005492) (“Takiar”), Degani et al. (US 6,175,158) (“Degani”), and Kawamura et al. (US 2021/0084750) (“Kawamura”).
With regard to claims 12 and 32, Takiar and Degani do not disclose that the second CTE of the dielectric material is between 4 ppm/K and 18 ppm/K.
However, fig. 1B of Kawamura discloses that the second CTE of the dielectric material 6 (“polyimide”, par [0144]) is between 4 ppm/K and 18 ppm/K (“thermal expansion coefficient (17 (ppm/K)) of the polyimide”, par [0125]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the solder mask of Takiar with the polyimide as taught in Kawamura in order to provide a wiring circuit board with suppressed reduction of adhesive properties with respect to the insulating layer. See par [0033] of Kawamura.
Allowable Subject Matter
Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/BENJAMIN TZU-HUNG LIU/Primary Examiner, Art Unit 2893