DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 6-7 are objected to because of the following informalities: The terms “claim 5” in claims 6-7 are amended into “claim 1” without the proper markings. The status identifier of claims 6-7, “Original”, are also incorrect and should be “(Currently Amended)” as claims 6-7 are amended. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 and 10-14 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kwak et al. (US 2020/0212267).
Regarding claim 1, Kwak et al. teach a display device (Figs. 2A; [0052]) comprising: pixel electrodes (144; Fig. 2A, [0070]) disposed on a substrate (110; Fig. 2A, [0047]), the pixel electrodes (144) each including a top surface (the top surface of 144) and side surfaces (the side surface of 144); light-emitting diode elements (the 141/142/143 of SPXR and SPXG; Figs. 2A-2B; [0070]) disposed on the pixel electrodes (144), the light-emitting diode elements each (each 141/142/143 of SPXR and SPXG) including a top surface (the top surface of 141/142/143 of SPXR and SPXG) and side surfaces (the side surfaces of 141/142/143 of SPXR and SPXG); an insulating film (171/173, 173 can have the same material as 171, “an insulating film” includes the plural forms as disclosed in paragraph [0049] of the current application; Fig. 2A, [0097]) disposed on both side surfaces (the left and right side surfaces) of each of the pixel electrodes (144) and disposed along both side surfaces (the left and right side surfaces) of each of the light-emitting diode elements (the 141/142/143 of SPXR and SPXGs in Fig. 2A); partition walls (PT; Fig. 2A, [0052]), each of the partition walls (PT) including a top surface (the top horizontal surface of PT; Fig. 2A), a bottom surface (the bottom horizontal surface of PT in Fig. 2A), and side surfaces (the left and right side surfaces of PT), wherein the partition walls (PT) include a conductive material (PT includes a conductor material as disclosed in [0076]); and a common electrode (CE; Fig. 2A, [0052]) disposed along (in parallel) the top surface of each of the partition walls (the top horizontal surface of PT; Fig. 2A) and the top surface of each of the light-emitting diode elements (the top horizonal surface of the 141/142/143 of SPXR and SPXGs; Fig. 2A), wherein the insulating film (171/173) is disposed along (in parallel) the bottom surface (the bottom horizontal surface of PT in Fig. 2A) of each of the partition walls (PT) and along both of the side surfaces (the left and the right side surfaces) of each of the partition walls (PT; see Fig. 2A), and the bottom surface of each of the partition walls (the bottom horizontal surface of PT in Fig. 2A) is a lowest surface of the partition walls (PT; see Fig. 2A), wherein the insulating film (171/173) is in contact with the bottom surface (in contact with the edge of the bottom horizontal surface of PT in Fig. 2A) and the side surfaces (the left and right side surfaces of PT) of each of the partition walls (PT) and side surfaces (the side surfaces of 141/142/143 of SPXR and SPXG) of each of the light-emitting diode elements (the 141/142/143 of SPXR and SPXG).
Regarding claim 2, Kwak et al. teach the display device of claim 1, wherein each of the light-emitting diode elements (each 141/142/143 of SPXR and SPXG) includes a first electrode (141 can be considered as the electrode for conducting hole current; Fig. 2A, [0070]), a light-emitting layer (142; Fig. 2A, [0070]), and a second electrode (143 can be considered as the electrode for conducting electron current; Fig. 2A, [0070]), which are sequentially stacked (see Fig. 2A) in a thickness direction (the vertical direction) of the substrate (110; see Fig. 2A).
Regarding claim 3, Kwak et al. teach the display device of claim 2, wherein the first electrode (141) of each of the light-emitting diode elements (each 141/142/143 of SPXR and SPXG) electrically contacts one of the pixel electrodes (144; see Fig. 2A), and the second electrode (143) of each of the light-emitting diode elements (each 141/142/143 of SPXR and SPXG) electrically contacts the common electrode (CE, through 145 and PT; Figs. 2A-2B, [0083]).
Regarding claim 4, Kwak et al. teach the display device of claim 1, wherein the common electrode (CE) includes a transparent conductive material ([0083]).
Regarding claim 10, Kwak et al. teach the display device of claim 1, wherein a height of a partition wall (the height of the top horizontal surface) of the partition walls (PT) is greater than a height (the height of the top horizontal surface) of a light-emitting diode element of the light-emitting diode elements (141/142/143 of SPXR; see Fig. 2A).
Regarding claim 11, Kwak et al. teach the display device of claim 10, wherein the common electrode (CE) is disposed along both of the side surfaces (the left and right side surfaces) of each of the partition walls (PT; see Fig. 2A).
Regarding claim 12, Kwak et al. teach the display device of claim 10, further comprising: a first wavelength conversion layer (160R; Fig. 2A, [0087]) overlapping a light-emitting diode element (141/142/143 of SPXR) among the light-emitting diode elements (141/142/143 of SPXR and SPXG) in a first emission area (the area directly above and under 160R) in a thickness direction (the vertical direction) of the substrate (110); a second wavelength conversion layer (160G; Fig. 2A, [0088]) overlapping a light-emitting diode element (141/142/143 of SPXG) among the light-emitting diode elements (141/142/143 of SPXR and SPXG) in a second emission area (the area directly above and under 160G) in the thickness direction (the vertical direction) of the substrate (110); and a transparent insulating film (172 in SPXR; Fig. 2A, [0095]) overlapping a light-emitting diode element (141/142/143 of SPXR) among the light-emitting diode elements (141/142/143 of SPXR and SPXG) in a third emission area (the area directly above and under 160R) in the thickness direction (the vertical direction) of the substrate (110; see Fig. 2A).
Regarding claim 13, Kwak et al. teach the display device of claim 12, wherein the first wavelength conversion layer (160R), the second wavelength conversion layer (160G), and the transparent insulating film (172 in SPXR) are disposed on the common electrode (CE; see Fig. 2A).
Regarding claim 14, Kwak et al. teach a display device (Figs. 2A; [0052) comprising: pixel electrodes (144; Fig. 2A, [0070]) disposed on a substrate (110; Fig. 2A, [0047]), the pixel electrodes (144) each including a top surface (the top surface of 144) and side surfaces (the side surface of 144); light-emitting diode elements (the 141/142/143 of SPXR and SPXG; Figs. 2A-2B; [0070]) disposed on the pixel electrodes (144), the light-emitting diode elements each (each 141/142/143 of SPXR and SPXG) including a top surface (the top surface of 141/142/143 of SPXR and SPXG) and side surfaces (the side surfaces of 141/142/143 of SPXR and SPXG); an insulating film (171/173, 173 can have the same material as 171, “an insulating film” includes the plural forms as disclosed in paragraph [0049] of the current application; Fig. 2A, [0097]) disposed on (covering) both side surfaces (the left and right side surfaces) of each of the pixel electrodes (144) and disposed along both side surfaces (the left and right side surfaces) of each of the light-emitting diode elements (the 141/142/143 of SPXR and SPXGs in Fig. 2A); partition walls (PT; Fig. 2A, [0052]) disposed on the insulating film (171/173; Fig. 2A), each of the partition walls (PT) including a top surface (the top horizontal surface of PT; Fig. 2A), a bottom surface (the bottom horizontal surface of PT in Fig. 2A), and side surfaces (the left and right side surfaces of PT), wherein the partition walls (PT) include a conductive material (PT includes a conductor material as disclosed in [0076]); a common electrode (CE; Fig. 2A, [0052]) disposed along (in parallel) the top surface of the partition walls (the top horizontal surface of PT; Fig. 2A) and along the top surface of the light-emitting diode elements (the top horizonal surface of the 141/142/143 of SPXR and SPXGs; Fig. 2A), a first wavelength conversion layer (160R; Fig. 2A, [0087]) overlapping a light-emitting diode element (141/142/143 of SPXR) among the light-emitting diode elements (141/142/143 of SPXR and SPXG) in a first emission area (the area directly above and under 160R) in a thickness direction (the vertical direction) of the substrate (110); a second wavelength conversion layer (160G; Fig. 2A, [0088]) overlapping a light-emitting diode element (141/142/143 of SPXG) among the light-emitting diode elements (141/142/143 of SPXR and SPXG) in a second emission area (the area directly above and under 160G) in the thickness direction (the vertical direction) of the substrate (110); and a transparent insulating film (172 in SPXR; Fig. 2A, [0095]) overlapping a light-emitting diode element (141/142/143 of SPXR) among the light-emitting diode elements (141/142/143 of SPXR and SPXG) in a third emission area (the area directly above and under 160R) in the thickness direction (the vertical direction) of the substrate (110; see Fig. 2A), wherein the first wavelength conversion layer (160R), the second wavelength conversion layer (160G), and the transparent insulating film (172 in SPXR) are disposed between the partition walls (PT; see Fig. 2A), the insulating film (171/173) is disposed along (in parallel) the bottom surface of each of the partition walls (the bottom horizontal surface of PT in Fig. 2A) and along both of the side surfaces (the left and the right side surfaces) of each of the partition walls (PT; see Fig. 2A), and the bottom surface of each of the partition walls (the bottom horizontal surface of PT in Fig. 2A) is a lowest surface of the partition walls (PT; see Fig. 2A), wherein the insulating film (171/173) is in contact with the bottom surface (in contact with the edge of the bottom horizontal surface of PT in Fig. 2A) and side surfaces (the left and right side surfaces of PT) of each of the partition walls (PT) and side surfaces (the side surfaces of 141/142/143 of SPXR and SPXG) of each of the light-emitting diode elements (the 141/142/143 of SPXR and SPXG).
Claim(s) 1, 6-7 and 16 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Iguchi et al. (US 2020/0259055).
Regarding claim 1, Iguchi et al. teach a display device (Fig. 1; [0040]) comprising: pixel electrodes (30; Fig. 1, [0041]) disposed on a substrate (50; Fig. 1, [0040]), the pixel electrodes (30) each including a top surface (the top surface of 30) and side surfaces (the left and right side surfaces of 30); light-emitting diode elements (11/12 and lower portions of 10; see Fig. 1 below; [0045]) disposed on the pixel electrodes (30), the light emitting diode elements each (each 11/12 and lower portions of 10) including a top surface (the top surface of 11/12 and lower portions of 10) and side surfaces (the left and right side surfaces of 11/12 and lower portions of 10); an insulating film (18/22, “an insulating film” includes the plural forms as disclosed in paragraph [0049] of the current application; Figs. 1 and 4, [0045, 0058]) disposed on both side surfaces (the left and right side surfaces) of each of the pixel electrodes (30) and disposed along both side surfaces (the left and right side surfaces) of each of the light-emitting diode elements (the 11/12 and lower portions of 10s in Fig. 1); partition walls (21; Fig. 1, [0041]), each of the partition walls (21) including a top surface (the top horizontal surface of 21; Fig. 1), a bottom surface (the bottom horizontal surface of 21; Fig. 1), and side surfaces (the left and right side surfaces of 21), wherein the partition walls (21) include a conductive material (conductive wiring; [0041]); and a common electrode (an upper portion of 10 in direct contact with each of the 21s, [0041]; see Fig. 1 below) disposed along the top surface of each of the partition walls (the top horizontal surface of 21; Fig. 1) and the top surface of each of the light-emitting diode elements (the top surface of the lower portions of 13 divided by 21s; see Fig. 1 below), wherein the insulating film (18/22) is disposed along the bottom surface of each of the partition walls (the bottom horizontal surface of 21) and along both of the side surfaces (the left or the right side surface) of each of the partition walls (21), and the bottom surface (the bottom horizontal surface of 21) of each of the partition walls (21) is a lowest surface of the partition walls (21; see Fig. 1), wherein the insulating film (18/22) is in contact with the bottom surface (the bottom horizontal surface of 21) and the side surfaces (the left and right side surfaces of 21) of each of the partition walls (21) and side surfaces (the left and right side surfaces of 11/12 and lower portions of 10) of each of the light-emitting diode elements (11/12 and lower portions of 10).
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[AltContent: connector][AltContent: connector][AltContent: connector][AltContent: textbox (light-emitting diode elements)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (common electrode)][AltContent: arrow][AltContent: textbox (22)][AltContent: arrow]
Fig. 1 of Iguchi et al. showing light-emitting diode elements and a common electrode defined by the dash lines.
Regarding claim 6, Iguchi et al. teach the display device of claim 1, wherein the partition walls (21) include an opaque metallic material (copper; [0056-0057]).
Regarding claim 7, Iguchi et al. teach the display device of claim 1, wherein the partition walls (21) are electrically connected to the common electrode (an upper portion of 10 in direct contact with each of the 21s).
Regarding claim 16, Iguchi et al. teach the display device of claim 1, wherein the common electrode (an upper portion of 10 in direct contact with each of the 21s, see Fig. 1 above) is electrically connected to a common connecting electrode (52; Fig. 1, [0040]), and the common connecting electrode (52) is disposed on the substrate (50) through a common electrode connector (31; Fig. 1, [0041]) through the insulating film (18/22; see Fig. 1 above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iguchi et al. (US 2020/0259055) in view of Shin et al. (US 2018/0308420 A1).
Regarding claim 8, Iguchi et al. teach a display device (Fig. 1; [0040]) comprising: pixel electrodes (30; Fig. 1, [0041]) disposed on a substrate (50; Fig. 1, [0040]), the pixel electrodes (30) each including a top surface (the top surface of 30) and side surfaces (the left and right side surfaces of 30); light-emitting diode elements (11/12 and lower portions of 10s; see Fig. 1 above; [0045]) disposed on the pixel electrodes (30), the light-emitting diode element each (each 11/12 and lower portions of 10) including a top surface (the top surface of 11/12 and lower portions of 10) and side surfaces (the left and right side surfaces of 11/12 and lower portions of 10); an insulating film (18/22, “an insulating film” includes the plural forms as disclosed in paragraph [0049] of the current application; Figs. 1 and 4, [0045, 0058]) disposed on both side surfaces (the left and right side surfaces) of each of the pixel electrodes (30) and disposed along both side surfaces (the left and right side surfaces) of each of the light-emitting diode elements (the 11/12 and lower portions of 10s in Fig. 1); partition walls (21; Fig. 1, [0041]) disposed on the insulating film (18/22; Fig. 1), the partition walls (21) each including a top surface (the top horizontal surface of 21; Fig. 1), a bottom surface (the bottom horizontal surface of 21; Fig. 1) and side surfaces (the left and right side surfaces of 21), wherein the partition walls (21) include a conductive material (conductive wiring; [0041]); a common electrode (an upper portion of 10 in direct contact with each of the 21s, [0041]; see Fig. 1 above) disposed along the top surface of the partition walls (the top horizontal surface of 21; Fig. 1) and the top surface of the light-emitting diode elements (the top surface of the lower portions of 13 divided by 21s; see Fig. 1 above), wherein the insulating film (18/22) is disposed along a lowest surface of the partition walls (the bottommost surface of 21; see Fig. 1), wherein the insulating film (18/22) is in contact with the bottom surface (the bottom horizontal surface of 21) and the side surfaces (the left and right side surfaces of 21) of each of the partition walls (21) and side surfaces (the left and right side surfaces of 11/12 and lower portions of 10) of each of the light-emitting diode elements (11/12 and lower portions of 10).
Iguchi et al. do not teach a black matrix disposed on the common electrode and overlapping the partition walls in a thickness direction of the substrate.
In the same field of endeavor of display device, Shin et al. teach a black matrix (920; Fig. 9, [0109]) disposed on the common electrode (a portion of 121 shown in Fig. 5C in contact with 125 is the common electrode of all the LEDs as disclosed in [0065] and is shown in Fig. 8 below; 920 is a part of 900 and 900 is an example embodiment of 360/370/380 in Fig. 8 as disclosed in [0108-0109], i.e. 920 is disposed on the common electrode as shown in Fig. 8 below).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Iguchi et al. and Shin et al., and to further include the wavelength conversion layers, the separator and the color filter 900 having the back matrix 920 of Shin et al. on the top of the Fig. 1 of Iguchi et al. as taught by Shin et al. ([0108-0110]), because the wavelength conversion layers, the separator and the color filter 900 can be used to implement a full color display and to remove effectively the color interference between the pixels as taught by Shin et al. ([0010-0011, 0015-0017]).
The combination of Iguchi et al. and Shin et al. teach that a black matrix overlapping the partition walls in a thickness direction of the substrate because Shin et al. teach that the black matrix 920 which is at the interfaces of 930/940/950 in Fig. 9 of Shin et al. which is equivalent to interfaces of 360/370/308 in Fig. 8 of Shin et al. which overlaps vertically (i.e. in a thickness direction of the substrate 330) the center of the gap between the LEDs in Fig. 8, while Iguchi et al. teach that the partition walls (21) also overlaps vertically (i.e. in a thickness direction of the substrate 50) the center of the gap between the LEDs in Fig. 1 of Iguchi et al.
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[AltContent: rect][AltContent: textbox (Common electrode)][AltContent: arrow]
Fig. 8 of showing the common electrode in the area enclosed by the dash line.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwak et al. as applied to claim 12 above, and further in view of Park et al. (US 2020/0066787 A1).
Regarding claim 15, Kwak et al. teach the display device of claim 12, further comprising: the first wavelength conversion layer (160R); the second wavelength conversion layer (160G); and the transparent insulating film (172 in SPXR).
Kwak et al. do not teach a first color filter disposed on the first wavelength conversion layer; a second color filter disposed on the second wavelength conversion layer; and a third color filter disposed on the transparent insulating film.
In the same field of endeavor of display device, Park et al. teach a first color filter (154R; Fig. 3O, [0079]) disposed on the first wavelength conversion layer (153R; Fig. 3O, [0079]); a second color filter (154G; Fig. 3O, [0079]) disposed on the second wavelength conversion layer (153G; Fig. 3O, [0079]); and a third color filter (154R; Fig. 3O, [0079]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Kwak et al. and Park et al., and to further include the color filter on the top of the wavelength conversion layers of Kwak et al. between the partition walls PTs of Kwak et al. as taught by Park et al. (see Fig. 3O), because the color filters can improve the purity of the color of the light after it has passed through the wavelength conversion layers as taught by Park et al. ([0079]).
The combination of Kwak et al. and Park et al. teach “a third color filter disposed on the transparent insulating film”, because Park et al. teach that a third color filter (154R) disposed on the wavelength conversion layer of red color (153R; ; Fig. 3O, [0079]) and Kwak et al. teach the transparent insulating film (172 in SPXR) is under the wavelength conversion layer of red color (160R; Fig. 2A, [0087]).
Response to Arguments
Applicant's arguments with respect to claims 1, 8 and 14 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yeon et al. (US 20180047780 A1) teach a light emitting device package having partition walls separating the light emitting devices.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HSIN YI HSIEH whose telephone number is (571)270-3043. The examiner can normally be reached 8:30 - 5:00 pm.
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/HSIN YI HSIEH/Primary Examiner, Art Unit 2899 4/20/2026
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