Attorney’s Docket Number: AD3280-US 111079-265241
Filing Date: 09/13/2021
Claimed Priority Date: NA
Applicants: Ecton et al.
Examiner: Aneesa Baig
DETAILED ACTION
This Office action responds to the Amendment filed on 12/01/2025.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The Amendment filed on 12/01/2025, responding to the Office action mailed on 08/29/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Applicant amended claims 1, 10, and 24 and cancelled claims 6, 7, 14, 15. Claims 20-23 are withdrawn from further consideration in response to telephonic restriction completed on 10/28/2024. Accordingly, pending in this application are claims 1-5,8-13,16-9, 24, 25, with claims 20-23 standing withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group Invention, there being no allowable generic or linking claim.
Response to Amendment
Applicants’ amendments to the claims have overcome the previous rejections under U.S.C. 102 and U.S.C. 103, however, some of the previously presented prior art remains relevant, and new grounds for rejection are presented below, as necessitated by Applicant’s amendments.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1,2,3,8 is rejected under 5 U.S.C. 103 as being unpatentable over Yu et al. ( US 20190088581 A1- Hereinafter Yu) in view of Dahlberg et al (US 20180342451 A1, Dahlberg).
Regarding Claim 1, Yu (e.g., Figure 1-12, [0025]-[0040]) shows most aspects of the invention, including an electronic package comprising:
a first layer comprising glass (e.g., dielectric layers 54C+52C+50C [0029] - figure 8 [0024], “Dielectric layers 50A and 54A may be formed of…MethylSilsesQuioxane (MSQ).” MSQ is known to be a spin-on glass (SOG)))
conductive pillars through the first layer (e.g., fine pitch RDLs 56C - fig 8]. Fine pitch RDLs formed of “a composite material including a barrier layer and a copper-containing material over the barrier layer.”) wherein the conductive pillars are continuous from a top of the first layer comprising glass to a bottom of the first layer comprising glass (e.g., 56C is continuous from the top of 54C to the bottom of 50C)
a buildup layer stack on the first layer (e.g., redistribution layer 102), wherein conductive routing (e.g., RDL wiring is electrically connected to 101 [0017]) is through the buildup layer stack; and
a second layer (e.g., dielectric layer 24 [0014]) over a surface of the buildup layer stack; and
a hybrid bonding layer coupled to a side of the fist layer opposite the buildup layer stack, the hybrid bonding layer comprising conductive pads in contact with the conductive pillars (e.g., dielectric layer 64 - [0035] has bond pads 66 in contact with 56C), and the hybrid bonding layer comprising a dielectric layer in contact with the glass of the first layer (e.g., the dielectric 64 is in contact with 54C).
While Yu shows conductive pillars with an uppermost surface at a same level as the top of the first layer, and a bottommost surface at a same level as the bottom of the first layer, it is silent about the hourglass shaped cross-section.
Dahlberg, (e.g., Fig 1-3, 12 [0030]-[0035],[0081][0041]), on the other hand and in a related field of glass layer substrates, teaches conductive pillars in a glass layer with a hourglass shape, with a narrow waist having a diameter less than a diameter of the openings, with an uppermost surface flush with a upper surface of the glass layer, and a bottom surface flush with a bottom surface of the glass layer (e.g., see Fig 1-3 [0041])). The pillars may be metallized using an electroplating process with conductive metals (e.g., [0035]) and in the electroplating process, deposited metal forms a metal bridge at the waist location first, and then metal is deposited on the bridge to finish filling the via to enable a void-free hermetic filling of vias.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have an hourglass shape of the conductive pillars in the structure of Yu, as taught by Dahlberg, to enable void-free filling of an hourglass via.
Regarding claim 2, Yu (e.g., figure 6 and 12, [0014]-[0021]) shows wherein the conductive routing (e.g., {32, 36, 40, 44}) includes a via (e.g., [0017] - “RDLs 32 also include vias”).
Regarding Claim 3, Yu in view of Dahlberg shows a hourglass shape, which is a subset of a hourglass via. See comments from Claim 1 as they would be considered repeated here.
Regarding claim 8, Yu (e.g., Figure 12, [0025]-[0040]) shows wherein a pitch of the conductive pillars (e.g., fine pitch RDLs 56C) is approximately 25 μm or smaller. Yu mentions (e.g., in [0025] “fine pitch RDLs can be formed with pitches smaller than, for example, 0.8 um”).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yu/Dahlberg further in view of Park et al (US 20160338202 A1, Hereinafter Park).
Regarding claim 4, Yu (e.g., Fig 8, 12) discloses conductive routing with a via (e.g., {32, 36, 40, 44}) includes a via ([0017] - “RDLs 32 also include vias”)., however Yu is silent about a via that is narrower closer to the first layer (e.g., 54C+52C+50C) .
Park (e.g., Fig 6, 8A-8F [0088], [0093], [0141] ) on the other hand and in the same field of endeavor, teaches the following:
wherein the via (e.g., 113 [0088]) has a first end with a first width (e.g., bottom of 113) and a second end with a second width (e.g., top of 113) that is smaller than the first width, and wherein the second end is closer to the third layer (e.g., 111A) than the first end (e.g., top of 113 is closer to 111A).
Park also teaches that tapered and reverse tapered vias are known in the art for alternatives for via shape ([0093]).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a reverse tapered via in the structure of Yu/Dahlberg, because tapered vias are known in the semiconductor packaging art as alternate arrangements forming an electrical connection through a substrate layer, as suggested by Park, and selecting among them would have been obvious to the skilled artisan. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007)
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yu/Dahlberg further in view of Kunimoto (US 20130069251 A1- hereinafter Kunimoto).
Regarding claim 9, Yu discloses a first layer. However, Yu does not teach the following:
wherein the first layer (e.g., dielectric layer 54A - figure 8) has a thickness that is approximately 200μm or smaller.
Kunimoto on the other hand an in the same field of endeavor, teaches the following:
wherein the first layer (e.g., Glass layer 10- Figure 6 - [0071]) has a thickness that is approximately 200μm or smaller. (e.g., “a glass substrate layer 10 of which the thickness is reduced to the range of 100 to 300.mu.m is obtained” ([0071]).
Kunimoto achieves this reduced thickness “by machining that is performed in the thickness direction on the surface of the glass substrate 10a opposite to the surface of the glass substrate” (e.g., [0071]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Yu/Dahlberg with Kunimoto with a reasonable expectation of success. One of ordinary skill in the art would be motivated to make this modification to achieve a thin packaging substrate while preventing warpage ([0050]-[0052]).
Response to Arguments
Applicant’s arguments with respect to the claims filed on 12/01/2025, have been considered but are moot in view of the new grounds of rejection.
Allowable Subject Matter
Claims 10-13,16-19,24,25are allowable.
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose semiconductor packaging structures.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEESA RIAZ BAIG whose telephone number is (571)272-0249. The examiner can normally be reached Monday-Friday 8am-5pm EST.
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/ANEESA RIAZ BAIG/Examiner, Art Unit 2814 /WAEL M FAHMY/ Supervisory Patent Examiner, Art Unit 2814