DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 28, 2025 has been entered.
Status of the Claims
Group I, Species 2, was elected.
Amendment filed August 28, 2025 is acknowledged. New claims 26-27 have been added. Claims 6 and 14 have been cancelled. Claims 1, 4, 9, 12, 21 and 24 have been amended. Claims 1-3, 5-13, 15 and 21-27 are pending. Non-elected Species, claims 7 and 15 have been withdrawn from consideration.
Action on merits of claims 1-5, 8-13 and 21-27 follows.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 4, 12 and 24 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There does not appear to be a written description of the claim limitation “wherein the first and second semiconductor device are each an n-channel device” (amended claims 4, 12 and 24) (emphasis added) in the application as filed.
However, FIG. 4C, paragraph [0052], discloses:
A masking material 418 is deposited and patterned to cover one or more of the fins, such as the fin of semiconductor device 404 within the region between spacer structures 412. In some embodiments, masking material 418 is patterned to cover one or more n-channel semiconductor devices while exposing one or more of the p-channel semiconductor devices.
Which means the covered device 404 is a n-channel device and the un-covered device 402 is a p-channel device.
Therefore, the limitation: “wherein the first and second semiconductor device are each an n-channel device” is an un-supported new matter.
Applicant must cancel the un-support new matters in response to the Office Action.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 21-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites the limitation " wherein the spacer includes a dummy channel structure that extends between the source or drain region and the gate electrode" in lines 11-12. There is insufficient antecedent basis for this limitation in the claim.
The limitation “gate electrode” lacks antecedent support.
Therefore, claims 21-25 are indefinite.
Further, there are three “source or drain region”, first, second and third, which of these three “source or drain region” that the “dummy channel structure” extends between?
Therefore, claims 21-25 are indefinite.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-5, 8-13 and 21-27 are rejected under 35 U.S.C. 103 as being unpatentable over LEE et al. (US. Pub. No. 2017/0250180) in view of CHENG et al. (US. Pub. No. 2019/0287864) both of record.
With respect to claim 1, LEE teaches an integrated circuit substantially as claimed including:
a first semiconductor device (12) having a first set of two or more semiconductor nanoribbons (134) extending from a source or drain region (148b); and
a second semiconductor device (10) having a second set of one or more semiconductor nanoribbons (132) extending from the source or drain region (148b), a gate electrode (166a) around the second set of one or more semiconductor ribbon (132), and a spacer (128) along a side of the gate electrode (166a), the second set of semiconductor nanoribbons (132) having a fewer number of nanoribbons than the first set of semiconductor nanoribbons, wherein the spacer (128) includes a structure that extends between the source or drain region (148b) and the gate electrode (166a). (See FIG. 1A).
Thus, LEE is shown to teach all the features of the claim with the exception of explicitly disclosing the spacer includes a dummy channel structure.
However, CHENG teaches an IC including:
a second semiconductor device (184) having a second set of one or more semiconductor nanoribbons (1220A) extending from source or drain region (1206/1208), a gate electrode (212A/214A) around the second set of one or more semiconductor ribbon (1220A), and a spacer along a side of the gate electrode, the second set of semiconductor nanoribbons (1220A) having a fewer number of nanoribbons than a first set of semiconductor nanoribbons (122A-126A), wherein the spacer includes a dummy channel structure (124) that extends between the source or drain region and the gate electrode. (See FIG. 3).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the spacer of LEE having the dummy channel structure that extends between the source or drain region as taught by CHENG for the same intended purpose of providing the second set of semiconductor nanoribbons that have fewer number of nanoribbons than the other set of semiconductor nanoribbons.
With respect to claim 9, LEE teaches an electronic device substantially as claimed, including:
at least one or more dies comprising
a first semiconductor device (12) having a first plurality of semiconductor nanoribbons (134) extending from a source or drain region (148b); and
a second semiconductor device (10) having a second plurality of semiconductor nanoribbons (132) extending from the source or drain region (148b), a gate electrode (162a) around the second plurality of semiconductor nanoribbons (132), and a spacer along a side of the gate electrode (162a), the second plurality of semiconductor ribbons (132) having a fewer number of nanoribbons than the first plurality of semiconductor nanoribbons (134), wherein the spacer includes a structure that extends between the source or drain region and the gate electrode. (See FIG. 1A).
Thus, LEE is shown to teach all the features of the claim with the exception of explicitly disclosing the spacer includes a dummy channel structure.
However, CHENG teaches an electronic device including:
a chip package comprising one or more dies, at least one of the one or more dies comprising a first semiconductor device (174); and
a second semiconductor device (184) having a second of semiconductor nanoribbon (1220A) extending from source or drain region (1206, 1208), a gate electrode around the second of semiconductor nanoribbon (1220A), and a spacer along a side of the gate electrode, the second of semiconductor ribbons (1220A) having a fewer number of nanoribbons than first plurality of semiconductor nanoribbons (122A-126A), wherein the spacer includes a dummy channel structure (124) that extends between the source or drain region (1206-1208) and the gate electrode. (See FIG. 3).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the spacer of LEE having the dummy channel structure that extends between the source or drain region as taught by CHENG for the same intended purpose of providing the second set of semiconductor nanoribbons that have fewer number of nanoribbons than the other set of semiconductor nanoribbons.
With respect to claim 21, As best understood by the Examiner, LEE teaches an integrated circuit substantially as claimed including:
a first semiconductor device (12) having a first total number of first semiconductor bodies (134) extending between a first source or drain region (148c) and a second source or drain region (148b), and a first gate structure (166b) wrapped around the first semiconductor bodies (134);
a second semiconductor device (10) having a second total number of second semiconductor bodies (132) extending between the second source or drain region (148b) and a third source or drain region (148a), and a second gate structure (166a) wrapped around the second semiconductor bodies (132); and
a spacer (128) along a side of the second gate structure (166a),
wherein the first total number of first semiconductor bodies (134) is greater than the second total number of second semiconductor bodies (132), and
wherein the spacer includes a structure that extends between the source or drain region (148a-b) and the gate electrode (166a). (See FIG. 1A).
Thus, LEE is shown to teach all the features of the claim with the exception of explicitly disclosing the spacer includes a dummy channel structure.
However, CHENG teaches an IC including:
a second semiconductor device (184) having a second total number of second semiconductor bodies (1220A) extending between a second source or drain region (1206) and a third source or drain region (1208), and a second gate structure (214A) wrapped around the second semiconductor bodies (1220A), and a spacer along a side of the second gate structure, wherein the spacer includes a dummy channel structure (124) that extends between the source or drain region (1206-1208) and the gate electrode. (See FIG. 3).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the spacer of LEE having the dummy channel structure that extends between the source or drain region as taught by CHENG for the same intended purpose of providing the second set of semiconductor nanoribbons that has fewer number of nanoribbons than the other set of semiconductor nanoribbons.
With respect to claims 2, 10 and 22, a first height between a bottommost nanoribbon and a topmost nanoribbon of the first set of semiconductor nanoribbons (134) of LEE is greater than a second height between a bottommost nanoribbon and a topmost nanoribbon of the second set of semiconductor nanoribbons (132).
With respect to claims 3, 11 and 23, a spacing between adjacent nanoribbons (134) of the first set of semiconductor nanoribbons is substantially the same as a spacing between adjacent nanoribbons (132) of the second set of semiconductor nanoribbons.
With respect to claims 4, 12 and 24, although not explicitly disclosed the channel type of the first and second semiconductor device, however, LEE explicitly discloses: “the second transistor 12 may have a relative higher operating current compared to the first transistor 10”. (¶ [0022]).
Which means two semiconductor devices, 10 and 12, are of the same channel type.
CHENG also teaches: “each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material” (¶ [0033]).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to forming the first (12) and second (10) semiconductor device of LEE being each an n-channel device is within the ability of one having ordinary skill in the art, by implanting appropriate dopant type into the semiconductor material 132, 134.
With respect to claims 5 and 13, the source or drain region (148) of LEE extends above a topmost nanoribbon of the first set of semiconductor nanoribbons (134) by a first height, and the source or drain region extends above a topmost nanoribbon (132) of the second set of semiconductor nanoribbons (132) by a second height that is greater than the first height.
With respect to claim 8, LEE, in view of CHENG, teaches a printed circuit board comprising the integrated circuit of claim 1.
With respect to claim 25, the first source or drain region (148c) and the second source or drain region (148b) of LEE extend above a topmost semiconductor body of the first semiconductor bodies (134) by a first height, and the second source or drain region (148b) and the third source or drain region (148a) extend above a topmost semiconductor body (132) of the second semiconductor bodies by a second height that is greater than the first height.
With respect to claim 26, the first set of semiconductor nanoribbons (134) and the second set of semiconductor nanoribbons (132) of LEE comprise germanium, silicon, or a combination thereof.
With respect to claim 27, the first plurality of semiconductor nanoribbons (134) and the second plurality of semiconductor nanoribbons (132) of LEE comprise germanium, silicon, or a combination thereof.
Response to Arguments
Applicant's arguments filed August 28, 2025 have been fully considered but they are not persuasive.
Applicant argues:
Applicant respectfully disagrees because Lee already provides a structure having one device with fewer nanoribbons compared to another device. Therefore, it is not clear why any aspect of Cheng would be combined with Lee.
However, studying both LEE and CHENG, one having ordinary skill in the art would have easily recognized that there are two ways to form a device with fewer nanoribbons.
LEE’s method for forming fewer ribbons by removing the top two semiconductor layers 102, 104 in the first region (See FIG. 4) before forming the semiconductor ribbons 132 and 134.
CHENG’s method for forming fewer ribbons, however, by etching to remove the top layers and stop at the predetermined number of semiconductor ribbon. (See FIGs. 14-17).
In view of CHENG, the etching would have formed the spacer along the sides of the gate electrode having dummy channel structures. The “dummy channel structure” are the remnants of the ribbons 124, 126, which do not altered the functionality or operability of the device.
Thus, it is obvious that if the “dummy channel structure” is desired, the method of CHENG is preferred, to form a device with fewer number of ribbons.
Otherwise, the method of LEE can be used to form a device with the same, fewer number of ribbons.
“[A] person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103.” KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421, 82 USPQ2d 1385, 1397 (2007).
Conclusion
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/ANH D MAI/ Primary Examiner, Art Unit 2893